修改GPIO导出默认初始值

hc

2024-10-16 50a212ec906f7524620675f0c57357691c26c81f

 kernel/arch/arm/boot/dts/am3517.dtsi
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@@ -1,7 +1,7 @@
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 /*
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  * Device Tree Source for am3517 SoC
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  *
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- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
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  *
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  * This file is licensed under the terms of the GNU General Public License
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  * version 2.  This program is licensed "as is" without any warranty of any
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@@ -10,10 +10,45 @@
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10
 
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 #include "omap3.dtsi"
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+/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
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+/delete-node/ &aes1_target;
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+/delete-node/ &aes2_target;
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+
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 / {
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 	aliases {
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 		serial3 = &uart4;
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 		can = &hecc;
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+	};
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+
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+	cpus {
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+		cpu: cpu@0 {
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+			/* Based on OMAP3630 variants OPP50 and OPP100 */
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+			operating-points-v2 = <&cpu0_opp_table>;
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+
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+			clock-latency = <300000>; /* From legacy driver */
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+		};
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+	};
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+
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+	cpu0_opp_table: opp-table {
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+		compatible = "operating-points-v2-ti-cpu";
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+		syscon = <&scm_conf>;
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+		/*
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+		 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
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+		 * appear to operate at 300MHz as well. Since AM3517 only
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+		 * lists one operating voltage, it will remain fixed at 1.2V
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+		 */
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+		opp50-300000000 {
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+			opp-hz = /bits/ 64 <300000000>;
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+			opp-microvolt = <1200000>;
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+			opp-supported-hw = <0xffffffff 0xffffffff>;
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+			opp-suspend;
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+		};
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+
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+		opp100-600000000 {
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+			opp-hz = /bits/ 64 <600000000>;
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+			opp-microvolt = <1200000>;
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+			opp-supported-hw = <0xffffffff 0xffffffff>;
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+		};
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 	};
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 	ocp@68000000 {
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@@ -43,7 +78,7 @@
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 			clock-names = "ick";
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 		};
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-		davinci_mdio: ethernet@5c030000 {
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+		davinci_mdio: mdio@5c030000 {
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 			compatible = "ti,davinci_mdio";
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 			ti,hwmods = "davinci_mdio";
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 			status = "disabled";
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@@ -88,7 +123,37 @@
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 			interrupts = <24>;
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 			clocks = <&hecc_ck>;
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 		};
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+
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+		/*
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+		 * On am3517 the OCP registers do not seem to be accessible
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+		 * similar to the omap34xx. Maybe SGX is permanently set to
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+		 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
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+		 * write-only at 0x50000e10. We detect SGX based on the SGX
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+		 * revision register instead of the unreadable OCP revision
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+		 * register.
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+		 */
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+		sgx_module: target-module@50000000 {
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+			compatible = "ti,sysc-omap2", "ti,sysc";
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+			reg = <0x50000014 0x4>;
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+			reg-names = "rev";
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+			clocks = <&sgx_fck>, <&sgx_ick>;
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+			clock-names = "fck", "ick";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0 0x50000000 0x4000>;
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+
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+			/*
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+			 * Closed source PowerVR driver, no child device
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+			 * binding or driver in mainline
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+			 */
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+		};
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 	};
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+};
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+
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+/* Not currently working, probably needs at least different clocks */
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+&rng_target {
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+	status = "disabled";
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+	/delete-property/ clocks;
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 };
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 /* Table Table 5-79 of the TRM shows 480ab000 is reserved */
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@@ -108,5 +173,25 @@
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 	status = "disabled";
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 };
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-/include/ "am35xx-clocks.dtsi"
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-/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
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+#include "am35xx-clocks.dtsi"
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+#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
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+
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+/* Preferred always-on timer for clocksource */
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+&timer1_target {
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+	ti,no-reset-on-init;
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+	ti,no-idle;
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+	timer@0 {
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+		assigned-clocks = <&gpt1_fck>;
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+		assigned-clock-parents = <&sys_ck>;
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+	};
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+};
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+
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+/* Preferred timer for clockevent */
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+&timer2_target {
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+	ti,no-reset-on-init;
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+	ti,no-idle;
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+	timer@0 {
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+		assigned-clocks = <&gpt2_fck>;
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+		assigned-clock-parents = <&sys_ck>;
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+	};
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+};