add .BoardConfig.mk package-file

hc

2023-05-31 43fd8d44e8182b691c8ee61d487cec02ca11afd2

 kernel/arch/arm64/boot/dts/rockchip/NK-R36S0.dtsi
..
..
@@ -8,6 +8,7 @@
8
8
 
9
9
 #include <dt-bindings/gpio/gpio.h>
10
10
 #include <dt-bindings/pinctrl/rockchip.h>
11
+#include <dt-bindings/display/media-bus-format.h>
11
12
 #include "rk3568.dtsi"
12
13
 #include "rk3568-evb.dtsi"
13
14
 
..
..
@@ -18,6 +19,7 @@
18
19
 	rk_headset: rk-headset {
19
20
 		compatible = "rockchip_headset";
20
21
 		headset_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
22
+		spk_ctl_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;//AMP_SD_GPIO4_C2_3V3
21
23
 		pinctrl-names = "default";
22
24
 		pinctrl-0 = <&hp_det>;
23
25
 	};
..
..
@@ -58,7 +60,9 @@
58
60
 		regulator-name = "vcc3v3_pcie";
59
61
 		regulator-min-microvolt = <3300000>;
60
62
 		regulator-max-microvolt = <3300000>;
63
+		regulator-always-on;
61
64
 		enable-active-high;
65
+		regulator-boot-on;
62
66
 		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
63
67
 		startup-delay-us = <5000>;
64
68
 		vin-supply = <&dc_12v>;
..
..
@@ -88,13 +92,9 @@
88
92
 
89
93
 	    nk_io_init {
90
94
                 compatible = "nk_io_control";
91
-//				usb_en_oc_gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;  //USB_EN_OC_GPIO0_A5
92
-				lcd_bk_en_gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
93
-				lcd_pwblk_gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;  //LCD0_BKLT_EN_3V3
94
95
 				vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
95
96
                 hub_host2_5V_rest_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
96
97
                 hub_host3_5v_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
97
-//              hub_host3_5V_rest_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 
98
98
                 vcc_5v_io = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;   //VCC5_IO_EN_GPIO1_A4_3V3
99
99
                 vcc_12v_io = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
100
100
                 en_4g_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
..
..
@@ -102,23 +102,55 @@
102
102
                 air_mode_4g_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; //4G_AIR_MODE_GPIO01_B0_3V3
103
103
                 wake_4g_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; //4G_WAKEUP_GPIO01_B1_3V3
104
104
 				hp_en_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;//HP_EN_GPIO3_A6_3V3
105
-                spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3
106
-				
107
-				edp_enable_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
108
-                edp_gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; //7511_GPIO0-GPIO3_D2
109
-				edp_gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; //7511_GPIO1-GPIO3_D3
110
-				edp_gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; //7511_GPIO2-GPIO3_D4
111
-				edp_gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //7511_GPIO3-GPIO3_D5
112
-                edp_reset = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
113
-//              tp_reset = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
114
-//              vddio_mipi = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
115
-		
105
+//              spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3			
116
106
 				wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
117
-
107
+//				pcie_power_en_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;//PCIE_PWREN_H_GPIO0_D4				
118
108
 				pinctrl-names = "default";
119
-				pinctrl-0 = <&nk_io_gpio>;
120
-				nodka_lvds = <9>;
109
+				pinctrl-0 = <&nk_io_gpio>;				
121
110
         };
111
+		
112
+		panel: panel {
113
+				compatible = "simple-panel";
114
+				backlight = <&backlight>;
115
+				power-supply = <&vcc3v3_lcd0_n>;
116
+				enable-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; //LCD0_VDD_H_GPIO2_D4
117
+				reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
118
+				edp-bl-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;  //LCD0_BKLT_EN_3V3
119
+				edp-bl-en = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
120
+				bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
121
+				bpc = <8>;
122
+				prepare-delay-ms = <200>;
123
+				enable-delay-ms = <20>;
124
+				lvds-gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; //7511_GPIO0-GPIO3_D2 
125
+				lvds-gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; //7511_GPIO1-GPIO3_D3 
126
+				lvds-gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; //7511_GPIO2-GPIO3_D4 
127
+				lvds-gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //7511_GPIO3-GPIO3_D5
128
+				nodka-lvds = <15>;
129
+
130
+				display-timings {
131
+                native-mode = <&timing0>;
132
+                timing0: timing0 {
133
+					clock-frequency = <72500000>;
134
+					hactive = <1280>;
135
+					vactive = <800>;
136
+					hfront-porch = <70>;
137
+					hsync-len = <2>;
138
+					hback-porch = <88>;
139
+					vfront-porch = <7>;
140
+					vsync-len = <4>;
141
+					vback-porch = <17>;
142
+					hsync-active = <21>;
143
+					vsync-active = <0>;
144
+					de-active = <0>;
145
+					pixelclk-active = <0>;			
146
+					};
147
+				};
148
+				ports {
149
+					panel_in: endpoint {
150
+					remote-endpoint = <&edp_out>;
151
+						};
152
+					};   
153
+				};
122
154
 };
123
155
 
124
156
 &combphy0_us {
..
..
@@ -134,11 +166,11 @@
134
166
 };
135
167
 
136
168
 &csi2_dphy_hw {
137
-	status = "okay";
169
+	status = "disabled";
138
170
 };
139
171
 
140
172
 &csi2_dphy0 {
141
-	status = "okay";
173
+	status = "disabled";
142
174
 
143
175
 	ports {
144
176
 		#address-cells = <1>;
..
..
@@ -181,8 +213,12 @@
181
213
  * video_phy0 needs to be enabled
182
214
  * when dsi0 is enabled
183
215
  */
216
+&video_phy0 {
217
+	status = "disabled";
218
+};
219
+
184
220
 &dsi0 {
185
-	status = "okay";
221
+	status = "disabled";
186
222
 };
187
223
 
188
224
 &dsi0_in_vp0 {
..
..
@@ -190,7 +226,7 @@
190
226
 };
191
227
 
192
228
 &dsi0_in_vp1 {
193
-	status = "okay";
229
+	status = "disabled";
194
230
 };
195
231
 
196
232
 &dsi0_panel {
..
..
@@ -201,6 +237,10 @@
201
237
  * video_phy1 needs to be enabled
202
238
  * when dsi1 is enabled
203
239
  */
240
+ 
241
+&video_phy1 {
242
+	status = "okay";
243
+}; 
204
244
 &dsi1 {
205
245
 	status = "disabled";
206
246
 };
..
..
@@ -210,29 +250,102 @@
210
250
 };
211
251
 
212
252
 &dsi1_in_vp1 {
213
-	status = "disabled";
253
+	status = "okay";
214
254
 };
215
255
 
216
256
 &dsi1_panel {
217
-	power-supply = <&vcc3v3_lcd1_n>;
257
+	power-supply = <&vcc3v3_lcd1_n>;   //MIPI_3V3EN_GPIO3_A3_d_3V3
258
+    vddio-mipi = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; //MIPI_EN_1V8_GPIO3_A4_d_3V3
259
+    reset-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; //MIPI_RST_L_GPIO3_C7
260
+    vcc-5v-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
261
+    pinctrl-names = "default";
262
+    pinctrl-0 = <&lcd1_rst_gpio>;
218
263
 };
219
264
 
265
+&route_dsi1 {
266
+	status = "disabled";
267
+	connect = <&vp1_out_dsi1>;
268
+};
269
+
270
+
271
+/*
272
+*  edp_start
273
+*/
274
+
220
275
 &edp {
221
-	hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
222
-	status = "okay";
276
+    force-hpd;
277
+    status = "okay";
278
+    ports {
279
+        port@1 {
280
+            reg = <1>;
281
+            edp_out: endpoint {
282
+                remote-endpoint = <&panel_in>;
283
+            };
284
+        };
285
+    };
223
286
 };
224
287
 
225
288
 &edp_phy {
226
-	status = "okay";
289
+  status = "okay";
290
+
227
291
 };
228
292
 
229
293
 &edp_in_vp0 {
230
-	status = "okay";
294
+    status = "disabled";
231
295
 };
232
296
 
233
297
 &edp_in_vp1 {
298
+    status = "okay";
299
+
300
+};
301
+
302
+&route_edp {
303
+    status = "okay";
304
+    connect = <&vp1_out_edp>;
305
+};
306
+
307
+&route_edp {
308
+	status = "okay";
309
+};
310
+/*
311
+*  edp_end
312
+*/
313
+
314
+/*
315
+*  Hdmi_start
316
+*/
317
+
318
+&hdmi {
319
+	status = "okay";
320
+	rockchip,phy-table =
321
+		<92812500  0x8009 0x0000 0x0270>,
322
+		<165000000 0x800b 0x0000 0x026d>,
323
+		<185625000 0x800b 0x0000 0x01ed>,
324
+		<297000000 0x800b 0x0000 0x01ad>,
325
+		<594000000 0x8029 0x0000 0x0088>,
326
+		<000000000 0x0000 0x0000 0x0000>;
327
+};
328
+
329
+&route_hdmi {
330
+	status = "okay";
331
+	connect = <&vp0_out_hdmi>;
332
+};
333
+
334
+&hdmi_in_vp0 {
335
+	status = "okay";
336
+};
337
+
338
+&hdmi_in_vp1 {
234
339
 	status = "disabled";
235
340
 };
341
+
342
+&hdmi_sound {
343
+	status = "okay";
344
+};
345
+
346
+/*
347
+ *  Hdmi_END
348
+*/
236
349
 
237
350
 &gmac0 {
238
351
 	phy-mode = "rgmii";
..
..
@@ -310,9 +423,6 @@
310
423
                 compatible = "nk_mcu";
311
424
                 reg = <0x15>;
312
425
         };
313
-
314
-
315
-
316
426
 };
317
427
 
318
428
 &i2c4 {
..
..
@@ -385,6 +495,19 @@
385
495
 	};
386
496
 };
387
497
 
498
+&i2c5 {
499
+	status = "okay";
500
+
501
+	hym8563: hym8563@51 {
502
+		compatible = "haoyu,hym8563";
503
+		reg = <0x51>;
504
+		#clock-cells = <0>;
505
+		clock-frequency = <32768>;
506
+		clock-output-names = "xin32k";
507
+		/* rtc_int is not connected */
508
+	};
509
+};
510
+
388
511
 &mdio0 {
389
512
 	rgmii_phy0: phy@0 {
390
513
 		compatible = "ethernet-phy-ieee802.3-c22";
..
..
@@ -399,20 +522,14 @@
399
522
 	};
400
523
 };
401
524
 
402
-&video_phy0 {
403
-	status = "okay";
404
-};
405
525
 
406
-&video_phy1 {
407
-	status = "disabled";
408
-};
409
526
 
410
527
 &pcie30phy {
411
528
 	status = "okay";
412
529
 };
413
530
 
414
-&pcie3x2 {
415
-	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
531
+&pcie2x1 {
532
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
416
533
 	vpcie3v3-supply = <&vcc3v3_pcie>;
417
534
 	status = "okay";
418
535
 };
..
..
@@ -427,7 +544,8 @@
427
544
 //	};
428
545
 	headphone {
429
546
 		hp_det: hp-det {
430
-			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>;
547
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>,
548
+							<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
431
549
 		};
432
550
 	};
433
551
 
..
..
@@ -442,6 +560,13 @@
442
560
 			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
443
561
 		};
444
562
 	};
563
+	
564
+	lcd1 {
565
+        lcd1_rst_gpio: lcd1-rst-gpio {
566
+            rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
567
+        };
568
+    };
569
+		
445
570
 	nk_io_init{
446
571
 		nk_io_gpio: nk-io-gpio{
447
572
 			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
..
..
@@ -455,7 +580,6 @@
455
580
 							<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
456
581
 							<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
457
582
 							<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
458
-							<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
459
583
 							<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
460
584
 							<3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
461
585
 							<3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>,
..
..
@@ -467,15 +591,15 @@
467
591
 };
468
592
 
469
593
 &rkisp {
470
-	status = "okay";
594
+	status = "disabled";
471
595
 };
472
596
 
473
597
 &rkisp_mmu {
474
-	status = "okay";
598
+	status = "disabled";
475
599
 };
476
600
 
477
601
 &rkisp_vir0 {
478
-	status = "okay";
602
+	status = "disabled";
479
603
 
480
604
 	port {
481
605
 		#address-cells = <1>;
..
..
@@ -488,15 +612,9 @@
488
612
 	};
489
613
 };
490
614
 
491
-&route_dsi0 {
492
-	status = "okay";
493
-	connect = <&vp1_out_dsi0>;
494
-};
495
615
 
496
-&route_edp {
497
-	status = "okay";
498
-	connect = <&vp0_out_edp>;
499
-};
616
+
617
+
500
618
 
501
619
 &sata2 {
502
620
 	status = "okay";
..
..
@@ -535,12 +653,12 @@
535
653
 };
536
654
 
537
655
 &vcc3v3_lcd0_n {
538
-	gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
656
+	gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; 
539
657
 	enable-active-high;
540
658
 };
541
659
 
542
660
 &vcc3v3_lcd1_n {
543
-	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
661
+	gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; //MIPI_3V3EN_GPIO3_A3_d_3V3
544
662
 	enable-active-high;
545
663
 };
546
664