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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/tools/arch/x86/include/asm/cpufeatures.h
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@@ -13,8 +13,8 @@
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 /*
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  * Defines x86 CPU feature bits
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  */
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-#define NCAPINTS			19	   /* N 32-bit words worth of info */
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-#define NBUGINTS			1	   /* N 32-bit bug flags */
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+#define NCAPINTS			20	   /* N 32-bit words worth of info */
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+#define NBUGINTS			2	   /* N 32-bit bug flags */
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 /*
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  * Note: If the comment begins with a quoted string, that string is used
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@@ -96,7 +96,7 @@
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 #define X86_FEATURE_SYSCALL32		( 3*32+14) /* "" syscall in IA32 userspace */
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 #define X86_FEATURE_SYSENTER32		( 3*32+15) /* "" sysenter in IA32 userspace */
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 #define X86_FEATURE_REP_GOOD		( 3*32+16) /* REP microcode works well */
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-#define X86_FEATURE_MFENCE_RDTSC	( 3*32+17) /* "" MFENCE synchronizes RDTSC */
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+/* FREE!                                ( 3*32+17) */
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 #define X86_FEATURE_LFENCE_RDTSC	( 3*32+18) /* "" LFENCE synchronizes RDTSC */
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 #define X86_FEATURE_ACC_POWER		( 3*32+19) /* AMD Accumulated Power Mechanism */
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 #define X86_FEATURE_NOPL		( 3*32+20) /* The NOPL (0F 1F) instructions */
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@@ -108,6 +108,7 @@
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 #define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */
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 #define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */
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 #define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
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+/* free					( 3*32+29) */
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 #define X86_FEATURE_NONSTOP_TSC_S3	( 3*32+30) /* TSC doesn't stop in S3 state */
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 #define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */
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@@ -200,17 +201,17 @@
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 #define X86_FEATURE_INVPCID_SINGLE	( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
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 #define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */
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 #define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */
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-#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */
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+/* FREE!                                ( 7*32+10) */
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 #define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */
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-#define X86_FEATURE_RETPOLINE		( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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-#define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */
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+#define X86_FEATURE_KERNEL_IBRS		( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
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+#define X86_FEATURE_RSB_VMEXIT		( 7*32+13) /* "" Fill RSB on VM-Exit */
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 #define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */
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 #define X86_FEATURE_CDP_L2		( 7*32+15) /* Code and Data Prioritization L2 */
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 #define X86_FEATURE_MSR_SPEC_CTRL	( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
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 #define X86_FEATURE_SSBD		( 7*32+17) /* Speculative Store Bypass Disable */
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 #define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */
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 #define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* "" Fill RSB on context switches */
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-#define X86_FEATURE_SEV			( 7*32+20) /* AMD Secure Encrypted Virtualization */
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+/* FREE!                                ( 7*32+20) */
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 #define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
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 #define X86_FEATURE_USE_IBRS_FW		( 7*32+22) /* "" Use IBRS during runtime firmware calls */
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 #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* "" Disable Speculative Store Bypass. */
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@@ -218,9 +219,10 @@
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 #define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */
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 #define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */
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 #define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */
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-#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
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+#define X86_FEATURE_ZEN			( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
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 #define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* "" L1TF workaround PTE inversion */
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 #define X86_FEATURE_IBRS_ENHANCED	( 7*32+30) /* Enhanced IBRS */
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+#define X86_FEATURE_MSR_IA32_FEAT_CTL	( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
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 /* Virtualization flags: Linux defined, word 8 */
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 #define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
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@@ -232,6 +234,8 @@
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 #define X86_FEATURE_VMMCALL		( 8*32+15) /* Prefer VMMCALL to VMCALL */
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 #define X86_FEATURE_XENPV		( 8*32+16) /* "" Xen paravirtual guest */
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 #define X86_FEATURE_EPT_AD		( 8*32+17) /* Intel Extended Page Table access-dirty bit */
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+#define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
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+#define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
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 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
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 #define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
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@@ -239,12 +243,14 @@
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 #define X86_FEATURE_BMI1		( 9*32+ 3) /* 1st group bit manipulation extensions */
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 #define X86_FEATURE_HLE			( 9*32+ 4) /* Hardware Lock Elision */
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 #define X86_FEATURE_AVX2		( 9*32+ 5) /* AVX2 instructions */
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+#define X86_FEATURE_FDP_EXCPTN_ONLY	( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */
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 #define X86_FEATURE_SMEP		( 9*32+ 7) /* Supervisor Mode Execution Protection */
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 #define X86_FEATURE_BMI2		( 9*32+ 8) /* 2nd group bit manipulation extensions */
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 #define X86_FEATURE_ERMS		( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */
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 #define X86_FEATURE_INVPCID		( 9*32+10) /* Invalidate Processor Context ID */
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 #define X86_FEATURE_RTM			( 9*32+11) /* Restricted Transactional Memory */
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 #define X86_FEATURE_CQM			( 9*32+12) /* Cache QoS Monitoring */
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+#define X86_FEATURE_ZERO_FCS_FDS	( 9*32+13) /* "" Zero out FPU CS and FPU DS */
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 #define X86_FEATURE_MPX			( 9*32+14) /* Memory Protection Extension */
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 #define X86_FEATURE_RDT_A		( 9*32+15) /* Resource Director Technology Allocation */
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 #define X86_FEATURE_AVX512F		( 9*32+16) /* AVX-512 Foundation */
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@@ -269,24 +275,47 @@
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 #define X86_FEATURE_XGETBV1		(10*32+ 2) /* XGETBV with ECX = 1 instruction */
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 #define X86_FEATURE_XSAVES		(10*32+ 3) /* XSAVES/XRSTORS instructions */
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-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */
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-#define X86_FEATURE_CQM_LLC		(11*32+ 1) /* LLC QoS if 1 */
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+/*
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+ * Extended auxiliary flags: Linux defined - for features scattered in various
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+ * CPUID levels like 0xf, etc.
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+ *
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+ * Reuse free bits when adding new feature flags!
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+ */
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+#define X86_FEATURE_CQM_LLC		(11*32+ 0) /* LLC QoS if 1 */
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+#define X86_FEATURE_CQM_OCCUP_LLC	(11*32+ 1) /* LLC occupancy monitoring */
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+#define X86_FEATURE_CQM_MBM_TOTAL	(11*32+ 2) /* LLC Total MBM monitoring */
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+#define X86_FEATURE_CQM_MBM_LOCAL	(11*32+ 3) /* LLC Local MBM monitoring */
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+#define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
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+#define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
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+#define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */
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+#define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
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+#define X86_FEATURE_ENTRY_IBPB		(11*32+10) /* "" Issue an IBPB on kernel entry */
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+#define X86_FEATURE_RRSBA_CTRL		(11*32+11) /* "" RET prediction control */
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+#define X86_FEATURE_RETPOLINE		(11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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+#define X86_FEATURE_RETPOLINE_LFENCE	(11*32+13) /* "" Use LFENCE for Spectre variant 2 */
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+#define X86_FEATURE_RETHUNK		(11*32+14) /* "" Use REturn THUNK */
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+#define X86_FEATURE_UNRET		(11*32+15) /* "" AMD BTB untrain return */
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+#define X86_FEATURE_RSB_VMEXIT_LITE	(11*32+17) /* "" Fill RSB on VM-Exit when EIBRS is enabled */
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-/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (EDX), word 12 */
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-#define X86_FEATURE_CQM_OCCUP_LLC	(12*32+ 0) /* LLC occupancy monitoring */
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-#define X86_FEATURE_CQM_MBM_TOTAL	(12*32+ 1) /* LLC Total MBM monitoring */
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-#define X86_FEATURE_CQM_MBM_LOCAL	(12*32+ 2) /* LLC Local MBM monitoring */
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+/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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+#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
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+#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
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 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
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 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
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 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
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 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
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+#define X86_FEATURE_RDPRU		(13*32+ 4) /* Read processor register at user level */
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+#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */
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 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */
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 #define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */
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 #define X86_FEATURE_AMD_STIBP		(13*32+15) /* "" Single Thread Indirect Branch Predictors */
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+#define X86_FEATURE_AMD_STIBP_ALWAYS_ON	(13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
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+#define X86_FEATURE_AMD_PPIN		(13*32+23) /* Protected Processor Inventory Number */
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 #define X86_FEATURE_AMD_SSBD		(13*32+24) /* "" Speculative Store Bypass Disable */
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 #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
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 #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
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+#define X86_FEATURE_BTC_NO		(13*32+29) /* "" Not vulnerable to Branch Type Confusion */
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 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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 #define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
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@@ -314,12 +343,14 @@
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 #define X86_FEATURE_AVIC		(15*32+13) /* Virtual Interrupt Controller */
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 #define X86_FEATURE_V_VMSAVE_VMLOAD	(15*32+15) /* Virtual VMSAVE VMLOAD */
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 #define X86_FEATURE_VGIF		(15*32+16) /* Virtual GIF */
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+#define X86_FEATURE_SVME_ADDR_CHK	(15*32+28) /* "" SVME addr check */
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 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
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 #define X86_FEATURE_AVX512VBMI		(16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
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 #define X86_FEATURE_UMIP		(16*32+ 2) /* User Mode Instruction Protection */
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 #define X86_FEATURE_PKU			(16*32+ 3) /* Protection Keys for Userspace */
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 #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
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+#define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
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 #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
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 #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
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 #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
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@@ -331,6 +362,9 @@
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 #define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */
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 #define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */
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 #define X86_FEATURE_CLDEMOTE		(16*32+25) /* CLDEMOTE instruction */
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+#define X86_FEATURE_MOVDIRI		(16*32+27) /* MOVDIRI instruction */
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+#define X86_FEATURE_MOVDIR64B		(16*32+28) /* MOVDIR64B instruction */
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+#define X86_FEATURE_ENQCMD		(16*32+29) /* ENQCMD and ENQCMDS instructions */
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 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
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 #define X86_FEATURE_OVERFLOW_RECOV	(17*32+ 0) /* MCA overflow recovery support */
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@@ -340,12 +374,28 @@
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 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
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 #define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */
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 #define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
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+#define X86_FEATURE_FSRM		(18*32+ 4) /* Fast Short Rep Mov */
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+#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
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+#define X86_FEATURE_SRBDS_CTRL		(18*32+ 9) /* "" SRBDS mitigation MSR available */
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+#define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
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+#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
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+#define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
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+#define X86_FEATURE_TSXLDTRK		(18*32+16) /* TSX Suspend Load Address Tracking */
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 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
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+#define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
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 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
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 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
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 #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
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 #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
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+#define X86_FEATURE_CORE_CAPABILITIES	(18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
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 #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative Store Bypass Disable */
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+
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+/* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
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+#define X86_FEATURE_SME			(19*32+ 0) /* AMD Secure Memory Encryption */
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+#define X86_FEATURE_SEV			(19*32+ 1) /* AMD Secure Encrypted Virtualization */
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+#define X86_FEATURE_VM_PAGE_FLUSH	(19*32+ 2) /* "" VM Page Flush MSR is supported */
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+#define X86_FEATURE_SEV_ES		(19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
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+#define X86_FEATURE_SME_COHERENT	(19*32+10) /* "" AMD hardware-enforced cache coherency */
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 /*
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  * BUG word(s)
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@@ -377,5 +427,13 @@
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 #define X86_BUG_SPECTRE_V2		X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
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 #define X86_BUG_SPEC_STORE_BYPASS	X86_BUG(17) /* CPU is affected by speculative store bypass attack */
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 #define X86_BUG_L1TF			X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
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+#define X86_BUG_MDS			X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
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+#define X86_BUG_MSBDS_ONLY		X86_BUG(20) /* CPU is only affected by the  MSDBS variant of BUG_MDS */
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+#define X86_BUG_SWAPGS			X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
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+#define X86_BUG_TAA			X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
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+#define X86_BUG_ITLB_MULTIHIT		X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
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+#define X86_BUG_SRBDS			X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
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+#define X86_BUG_MMIO_STALE_DATA		X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
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+#define X86_BUG_RETBLEED		X86_BUG(26) /* CPU is affected by RETBleed */
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 #endif /* _ASM_X86_CPUFEATURES_H */