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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/include/uapi/linux/kfd_ioctl.h
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@@ -26,8 +26,12 @@
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 #include <drm/drm.h>
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 #include <linux/ioctl.h>
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+/*
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+ * - 1.1 - initial version
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+ * - 1.3 - Add SMI events support
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+ */
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 #define KFD_IOCTL_MAJOR_VERSION 1
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-#define KFD_IOCTL_MINOR_VERSION 1
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+#define KFD_IOCTL_MINOR_VERSION 3
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 struct kfd_ioctl_get_version_args {
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 	__u32 major_version;	/* from KFD */
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@@ -35,9 +39,10 @@
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 };
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 /* For kfd_ioctl_create_queue_args.queue_type. */
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-#define KFD_IOC_QUEUE_TYPE_COMPUTE	0
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-#define KFD_IOC_QUEUE_TYPE_SDMA		1
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-#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL	2
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+#define KFD_IOC_QUEUE_TYPE_COMPUTE		0x0
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+#define KFD_IOC_QUEUE_TYPE_SDMA			0x1
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+#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL		0x2
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+#define KFD_IOC_QUEUE_TYPE_SDMA_XGMI		0x3
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 #define KFD_MAX_QUEUE_PERCENTAGE	100
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 #define KFD_MAX_QUEUE_PRIORITY		15
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@@ -80,6 +85,14 @@
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 	__u32 queue_id;		/* to KFD */
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 	__u32 num_cu_mask;		/* to KFD */
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 	__u64 cu_mask_ptr;		/* to KFD */
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+};
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+
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+struct kfd_ioctl_get_queue_wave_state_args {
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+	__u64 ctl_stack_address;	/* to KFD */
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+	__u32 ctl_stack_used_size;	/* from KFD */
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+	__u32 save_area_used_size;	/* from KFD */
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+	__u32 queue_id;			/* to KFD */
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+	__u32 pad;
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 };
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 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
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@@ -203,6 +216,11 @@
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 #define KFD_HW_EXCEPTION_GPU_HANG	0
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 #define KFD_HW_EXCEPTION_ECC		1
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+/* For kfd_hsa_memory_exception_data.ErrorType */
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+#define KFD_MEM_ERR_NO_RAS		0
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+#define KFD_MEM_ERR_SRAM_ECC		1
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+#define KFD_MEM_ERR_POISON_CONSUMED	2
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+#define KFD_MEM_ERR_GPU_HANG		3
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 struct kfd_ioctl_create_event_args {
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 	__u64 event_page_offset;	/* from KFD */
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@@ -237,12 +255,17 @@
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 	__u32 imprecise;	/* Can't determine the	exact fault address */
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 };
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-/* memory exception data*/
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+/* memory exception data */
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 struct kfd_hsa_memory_exception_data {
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 	struct kfd_memory_exception_failure failure;
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 	__u64 va;
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 	__u32 gpu_id;
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-	__u32 pad;
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+	__u32 ErrorType; /* 0 = no RAS error,
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+			  * 1 = ECC_SRAM,
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+			  * 2 = Link_SYNFLOOD (poison),
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+			  * 3 = GPU hang (not attributable to a specific cause),
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+			  * other values reserved
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+			  */
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 };
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 /* hw exception data */
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@@ -320,6 +343,7 @@
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 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT		(1 << 1)
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 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR		(1 << 2)
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 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL	(1 << 3)
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+#define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP	(1 << 4)
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 /* Allocation flags: attributes/access options */
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 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE	(1 << 31)
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 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE	(1 << 30)
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@@ -388,6 +412,63 @@
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 	__u64 device_ids_array_ptr;	/* to KFD */
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 	__u32 n_devices;		/* to KFD */
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 	__u32 n_success;		/* to/from KFD */
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+};
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+
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+/* Allocate GWS for specific queue
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+ *
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+ * @queue_id:    queue's id that GWS is allocated for
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+ * @num_gws:     how many GWS to allocate
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+ * @first_gws:   index of the first GWS allocated.
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+ *               only support contiguous GWS allocation
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+ */
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+struct kfd_ioctl_alloc_queue_gws_args {
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+	__u32 queue_id;		/* to KFD */
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+	__u32 num_gws;		/* to KFD */
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+	__u32 first_gws;	/* from KFD */
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+	__u32 pad;
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+};
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+
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+struct kfd_ioctl_get_dmabuf_info_args {
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+	__u64 size;		/* from KFD */
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+	__u64 metadata_ptr;	/* to KFD */
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+	__u32 metadata_size;	/* to KFD (space allocated by user)
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+				 * from KFD (actual metadata size)
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+				 */
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+	__u32 gpu_id;	/* from KFD */
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+	__u32 flags;		/* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
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+	__u32 dmabuf_fd;	/* to KFD */
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+};
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+
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+struct kfd_ioctl_import_dmabuf_args {
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+	__u64 va_addr;	/* to KFD */
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+	__u64 handle;	/* from KFD */
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+	__u32 gpu_id;	/* to KFD */
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+	__u32 dmabuf_fd;	/* to KFD */
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+};
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+
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+/*
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+ * KFD SMI(System Management Interface) events
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+ */
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+enum kfd_smi_event {
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+	KFD_SMI_EVENT_NONE = 0, /* not used */
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+	KFD_SMI_EVENT_VMFAULT = 1, /* event start counting at 1 */
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+	KFD_SMI_EVENT_THERMAL_THROTTLE = 2,
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+	KFD_SMI_EVENT_GPU_PRE_RESET = 3,
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+	KFD_SMI_EVENT_GPU_POST_RESET = 4,
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+};
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+
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+#define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
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+
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+struct kfd_ioctl_smi_events_args {
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+	__u32 gpuid;	/* to KFD */
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+	__u32 anon_fd;	/* from KFD */
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+};
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+
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+/* Register offset inside the remapped mmio page
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+ */
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+enum kfd_mmio_remap {
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+	KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
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+	KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
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 };
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 #define AMDKFD_IOCTL_BASE 'K'
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@@ -475,7 +556,22 @@
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 #define AMDKFD_IOC_SET_CU_MASK		\
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 		AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
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+#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE		\
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+		AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
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+
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+#define AMDKFD_IOC_GET_DMABUF_INFO		\
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+		AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
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+
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+#define AMDKFD_IOC_IMPORT_DMABUF		\
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+		AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
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+
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+#define AMDKFD_IOC_ALLOC_QUEUE_GWS		\
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+		AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
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+
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+#define AMDKFD_IOC_SMI_EVENTS			\
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+		AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args)
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+
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 #define AMDKFD_COMMAND_START		0x01
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-#define AMDKFD_COMMAND_END		0x1B
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+#define AMDKFD_COMMAND_END		0x20
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 #endif