~hc/RK356X_SDK_RELEASE.git

..	..	@@ -273,6 +273,13 @@
273	273	*/
274	274	#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
275	275
	276	+/* 2 plane YCbCr420.
	277	+ * 3 10 bit components and 2 padding bits packed into 4 bytes.
	278	+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
	279	+ * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
	280	+ */
	281	+#define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
	282	+
276	283	/* 3 plane non-subsampled (444) YCbCr
277	284	* 16 bits per component, but only 10 bits are used and 6 bits are padded
278	285	* index 0: Y plane, [15:0] Y:x [10:6] little endian
..	..	@@ -780,6 +787,10 @@
780	787	* and UV. Some SAND-using hardware stores UV in a separate tiled
781	788	* image from Y to reduce the column height, which is not supported
782	789	* with these modifiers.
	790	+ *
	791	+ * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
	792	+ * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
	793	+ * wide, but as this is a 10 bpp format that translates to 96 pixels.
783	794	*/
784	795
785	796	#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
..	..	@@ -1059,14 +1070,43 @@
1059	1070	*/
1060	1071	#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1061	1072
	1073	+/*
	1074	+ * Rockchip modifier format
	1075	+ * tiled modifier format, block size: 8x8,4x4_m0 and 4x4_m1,
	1076	+ * rfbc modifier format, block size: 64x4
	1077	+ *
	1078	+ * bit[55,52] for Rockchip drm modifier type
	1079	+ */
	1080	+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT 52
	1081	+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_MASK 0xf
	1082	+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_TILED 0x0
	1083	+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC 0x1
	1084	+
	1085	+/* bit[3,0] for Rockchip drm modifier block size */
1062	1086	#define ROCKCHIP_TILED_BLOCK_SIZE_MASK 0xf
1063	1087	#define ROCKCHIP_TILED_BLOCK_SIZE_8x8 (1ULL)
1064	1088	#define ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 (2ULL)
1065	1089	#define ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE1 (3ULL)
1066	1090
1067		-#define DRM_FORMAT_MOD_ROCKCHIP_TILED(_mode) fourcc_mod_code(ROCKCHIP, _mode)
	1091	+#define ROCKCHIP_RFBC_BLOCK_SIZE_64x4 (1ULL)
1068	1092
1069		-#define IS_ROCKCHIP_TILED_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_ROCKCHIP)
	1093	+#define DRM_FORMAT_MOD_ROCKCHIP_CODE(__type, __val) \
	1094	+ fourcc_mod_code(ROCKCHIP, ((__u64)(__type) << DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT) \| \
	1095	+ ((__val) & 0x000fffffffffffffULL))
	1096	+
	1097	+/* Rockchip tiled modifier format */
	1098	+#define DRM_FORMAT_MOD_ROCKCHIP_TILED(mode) \
	1099	+ DRM_FORMAT_MOD_ROCKCHIP_CODE(DRM_FORMAT_MOD_ROCKCHIP_TYPE_TILED, mode)
	1100	+#define IS_ROCKCHIP_TILED_MOD(val) \
	1101	+ (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_ROCKCHIP && \
	1102	+ ((val >> DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT) & DRM_FORMAT_MOD_ROCKCHIP_TYPE_MASK) == DRM_FORMAT_MOD_ROCKCHIP_TYPE_TILED)
	1103	+
	1104	+/* Rockchip rfbc modifier format */
	1105	+#define DRM_FORMAT_MOD_ROCKCHIP_RFBC(mode) \
	1106	+ DRM_FORMAT_MOD_ROCKCHIP_CODE(DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC, mode)
	1107	+#define IS_ROCKCHIP_RFBC_MOD(val) \
	1108	+ (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_ROCKCHIP && \
	1109	+ ((val >> DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT) & DRM_FORMAT_MOD_ROCKCHIP_TYPE_MASK) == DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC)
1070	1110
1071	1111	#if defined(__cplusplus)
1072	1112	}