.. | .. |
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13 | 13 | #include <linux/regmap.h> |
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14 | 14 | #include <linux/mfd/core.h> |
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15 | 15 | |
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16 | | -#ifndef HIWORD_UPDATE |
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17 | 16 | #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) |
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18 | 17 | #define HIWORD_MASK(h, l) ((GENMASK((h), (l)) << 16) | GENMASK((h), (l))) |
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19 | 18 | #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16)) |
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20 | | -#endif |
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21 | 19 | |
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22 | 20 | #define RTC_REG(x) ((x) + 0x60000) |
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23 | 21 | #define RTC_SET_SECONDS RTC_REG(0x0) |
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63 | 61 | |
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64 | 62 | #define GRF_REG(x) ((x) + 0x20000) |
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65 | 63 | #define PLUMAGE_GRF_GPIO0A_IOMUX GRF_REG(0x0000) |
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| 64 | +#define GPIO0A0_SEL_MASK HIWORD_MASK(1, 0) |
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| 65 | +#define GPIO0A0_SEL(x) HIWORD_UPDATE(x, 1, 0) |
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| 66 | +#define GPIO0A1_SEL_MASK HIWORD_MASK(3, 2) |
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| 67 | +#define GPIO0A1_SEL(x) HIWORD_UPDATE(x, 3, 2) |
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| 68 | +#define GPIO0A2_SEL_MASK HIWORD_MASK(5, 4) |
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| 69 | +#define GPIO0A2_SEL(x) HIWORD_UPDATE(x, 5, 4) |
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| 70 | +#define GPIO0A3_SEL_MASK HIWORD_MASK(7, 6) |
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| 71 | +#define GPIO0A3_SEL(x) HIWORD_UPDATE(x, 7, 6) |
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| 72 | +#define GPIO0A4_SEL_MASK HIWORD_MASK(9, 8) |
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| 73 | +#define GPIO0A4_SEL(x) HIWORD_UPDATE(x, 9, 8) |
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| 74 | +#define GPIO0A5_SEL_MASK HIWORD_MASK(11, 10) |
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| 75 | +#define GPIO0A5_SEL(x) HIWORD_UPDATE(x, 11, 10) |
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| 76 | +#define GPIO0A6_SEL_MASK HIWORD_MASK(13, 12) |
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| 77 | +#define GPIO0A6_SEL(x) HIWORD_UPDATE(x, 13, 12) |
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| 78 | +#define GPIO0A7_SEL_MASK HIWORD_MASK(15, 14) |
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| 79 | +#define GPIO0A7_SEL(x) HIWORD_UPDATE(x, 15, 14) |
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66 | 80 | #define PLUMAGE_GRF_GPIO0B_IOMUX GRF_REG(0x0008) |
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| 81 | +#define GPIO0B0_SEL_MASK HIWORD_MASK(1, 0) |
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| 82 | +#define GPIO0B0_SEL(x) HIWORD_UPDATE(x, 1, 0) |
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67 | 83 | #define PLUMAGE_GRF_GPIO0C_IOMUX GRF_REG(0x0010) |
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68 | 84 | #define PLUMAGE_GRF_GPIO0D_IOMUX GRF_REG(0x0018) |
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69 | 85 | #define PLUMAGE_GRF_GPIO1A_IOMUX GRF_REG(0x0020) |
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70 | 86 | #define PLUMAGE_GRF_GPIO1B_IOMUX GRF_REG(0x0028) |
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71 | | -#define PIN0_SEL_MASK HIWORD_MASK(1, 0) |
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72 | | -#define PIN0_SEL(x) HIWORD_UPDATE(x, 1, 0) |
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73 | | -#define PIN1_SEL_MASK HIWORD_MASK(3, 2) |
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74 | | -#define PIN1_SEL(x) HIWORD_UPDATE(x, 3, 2) |
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75 | | -#define PIN2_SEL_MASK HIWORD_MASK(5, 4) |
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76 | | -#define PIN2_SEL(x) HIWORD_UPDATE(x, 5, 4) |
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77 | | -#define PIN3_SEL_MASK HIWORD_MASK(7, 6) |
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78 | | -#define PIN3_SEL(x) HIWORD_UPDATE(x, 7, 6) |
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79 | | -#define PIN4_SEL_MASK HIWORD_MASK(9, 8) |
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80 | | -#define PIN4_SEL(x) HIWORD_UPDATE(x, 9, 8) |
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81 | | -#define PIN5_SEL_MASK HIWORD_MASK(11, 10) |
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82 | | -#define PIN5_SEL(x) HIWORD_UPDATE(x, 11, 10) |
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83 | | -#define PIN6_SEL_MASK HIWORD_MASK(13, 12) |
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84 | | -#define PIN6_SEL(x) HIWORD_UPDATE(x, 13, 12) |
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85 | | -#define PIN7_SEL_MASK HIWORD_MASK(15, 14) |
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86 | | -#define PIN7_SEL(x) HIWORD_UPDATE(x, 15, 14) |
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87 | 87 | #define PLUMAGE_GRF_GPIO0A_P GRF_REG(0x0080) |
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88 | 88 | #define PLUMAGE_GRF_GPIO0B_P GRF_REG(0x0084) |
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89 | 89 | #define PLUMAGE_GRF_GPIO0C_P GRF_REG(0x0088) |
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110 | 110 | #define PLUMAGE_GRF_SOC_CON1 GRF_REG(0x0404) |
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111 | 111 | #define PLUMAGE_GRF_SOC_CON2 GRF_REG(0x0408) |
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112 | 112 | #define PLUMAGE_GRF_SOC_CON3 GRF_REG(0x040C) |
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113 | | -#define DCLK_UPSAMPLE_2X4X_MASK HIWORD_MASK(15, 15) |
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114 | | -#define DCLK_UPSAMPLE_2X4X(x) HIWORD_UPDATE(x, 15, 15) |
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115 | 113 | #define VDAC_ENVBG_MASK HIWORD_MASK(12, 12) |
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116 | 114 | #define VDAC_ENVBG(x) HIWORD_UPDATE(x, 12, 12) |
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117 | 115 | #define VDAC_ENSC0_MASK HIWORD_MASK(11, 11) |
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164 | 162 | #define CRU_CLKSEL_CON2 CRU_REG(0x0038) |
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165 | 163 | #define CRU_CLKSEL_CON3 CRU_REG(0x003c) |
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166 | 164 | #define CRU_GATE_CON0 CRU_REG(0x0040) |
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167 | | -#define PCLK_EFUSE_EN_MASK BIT(14 + 16) |
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168 | | -#define PCLK_EFUSE_DISABLE BIT(14) |
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169 | | -#define DCLK_CVBS_1X_PLL_CLK_GATE_MASK HIWORD_MASK(12, 12) |
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170 | | -#define DCLK_CVBS_1X_PLL_CLK_GATE(x) HIWORD_UPDATE(x, 12, 12) |
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171 | | -#define DCLK_CVBS_4X_PLL_CLK_GATE_MASK HIWORD_MASK(11, 11) |
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172 | | -#define DCLK_CVBS_4X_PLL_CLK_GATE(x) HIWORD_UPDATE(x, 11, 11) |
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173 | 165 | #define CRU_SOFTRST_CON0 CRU_REG(0x0050) |
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174 | 166 | #define DRESETN_CVBS_1X_MASK HIWORD_MASK(10, 10) |
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175 | 167 | #define DRESETN_CVBS_1X(x) HIWORD_UPDATE(x, 10, 10) |
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180 | 172 | #define PRESETN_GRF_MASK HIWORD_MASK(3, 3) |
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181 | 173 | #define PRESETN_GRF(x) HIWORD_UPDATE(x, 3, 3) |
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182 | 174 | #define CRU_MAX_REGISTER CRU_SOFTRST_CON0 |
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183 | | - |
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184 | | -#define GPIO0_BASE 0x30000 |
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185 | | -#define GPIO1_BASE 0x40000 |
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186 | | -#define GPIO_SWPORT_DR_L 0x00 |
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187 | | -#define GPIO_SWPORT_DR_H 0x04 |
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188 | | -#define GPIO_SWPORT_DDR_L 0x08 |
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189 | | -#define GPIO_SWPORT_DDR_H 0x0c |
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190 | | -#define GPIO_INT_EN_L 0x10 |
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191 | | -#define GPIO_INT_EN_H 0x14 |
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192 | | -#define GPIO_INT_MASK_L 0x18 |
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193 | | -#define GPIO_INT_MASK_H 0x1c |
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194 | | -#define GPIO_INT_TYPE_L 0x20 |
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195 | | -#define GPIO_INT_TYPE_H 0x24 |
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196 | | -#define GPIO_INT_POLARITY_L 0x28 |
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197 | | -#define GPIO_INT_POLARITY_H 0x2c |
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198 | | -#define GPIO_INT_BOTHEDGE_L 0x30 |
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199 | | -#define GPIO_INT_BOTHEDGE_H 0x34 |
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200 | | -#define GPIO_DEBOUNCE_L 0x38 |
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201 | | -#define GPIO_DEBOUNCE_H 0x3c |
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202 | | -#define GPIO_DBCLK_DIV_EN_L 0x40 |
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203 | | -#define GPIO_DBCLK_DIV_EN_H 0x44 |
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204 | | -#define GPIO_DBCLK_DIV_CON 0x48 |
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205 | | -#define GPIO_INT_STATUS 0x50 |
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206 | | -#define GPIO_INT_RAWSTATUS 0x58 |
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207 | | -#define GPIO_PORT_EOI_L 0x60 |
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208 | | -#define GPIO_PORT_EOI_H 0x64 |
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209 | | -#define GPIO_EXT_PORT 0x70 |
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210 | | -#define GPIO_VER_ID 0x78 |
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211 | | -#define GPIO_MAX_REGISTER (GPIO1_BASE + GPIO_VER_ID) |
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212 | 175 | |
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213 | 176 | #define TVE_REG(x) ((x) + 0x10000) |
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214 | 177 | #define BT656_DECODER_CTRL TVE_REG(0x3D00) |
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.. | .. |
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258 | 221 | struct rk630 { |
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259 | 222 | struct device *dev; |
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260 | 223 | struct i2c_client *client; |
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261 | | - struct clk *ref_clk; |
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262 | 224 | struct regmap *grf; |
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263 | | - struct regmap *pinctrl; |
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264 | 225 | struct regmap *cru; |
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265 | 226 | struct regmap *tve; |
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266 | 227 | struct regmap *rtc; |
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267 | | - struct regmap *efuse; |
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268 | | - struct regmap *codec; |
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269 | 228 | struct gpio_desc *reset_gpio; |
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270 | 229 | int irq; |
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271 | 230 | struct regmap_irq_chip_data *irq_data; |
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272 | 231 | const struct regmap_irq_chip *regmap_irq_chip; |
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273 | 232 | }; |
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274 | 233 | |
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275 | | -extern const struct regmap_config rk630_efuse_regmap_config; |
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276 | 234 | extern const struct regmap_config rk630_rtc_regmap_config; |
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277 | 235 | extern const struct regmap_config rk630_grf_regmap_config; |
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278 | | -extern const struct regmap_config rk630_pinctrl_regmap_config; |
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279 | 236 | extern const struct regmap_config rk630_cru_regmap_config; |
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280 | 237 | extern const struct regmap_config rk630_tve_regmap_config; |
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281 | | -extern const struct regmap_config rk630_codec_regmap_config; |
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282 | 238 | |
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283 | 239 | int rk630_core_probe(struct rk630 *rk630); |
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284 | 240 | int rk630_core_remove(struct rk630 *rk630); |
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