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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c
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..
@@ -1,18 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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- *
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  */
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5
 
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 #include <linux/kernel.h>
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..
@@ -33,18 +21,15 @@
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21
 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT	\
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 	(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
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23
 
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-static void __iomem *apbmisc_base;
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-static void __iomem *strapping_base;
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 static bool long_ram_code;
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+static u32 strapping;
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+static u32 chipid;
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27
 
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 u32 tegra_read_chipid(void)
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 {
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-	if (!apbmisc_base) {
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-		WARN(1, "Tegra Chip ID not yet available\n");
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-		return 0;
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-	}
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+	WARN(!chipid, "Tegra APB MISC not yet available\n");
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-	return readl_relaxed(apbmisc_base + 4);
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+	return chipid;
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 }
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34
 
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 u8 tegra_get_chip_id(void)
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@@ -52,12 +37,46 @@
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 	return (tegra_read_chipid() >> 8) & 0xff;
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 }
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39
 
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+u8 tegra_get_major_rev(void)
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+{
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+	return (tegra_read_chipid() >> 4) & 0xf;
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+}
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+
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+u8 tegra_get_minor_rev(void)
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+{
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+	return (tegra_read_chipid() >> 16) & 0xf;
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+}
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+
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+u8 tegra_get_platform(void)
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+{
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+	return (tegra_read_chipid() >> 20) & 0xf;
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+}
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+
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+bool tegra_is_silicon(void)
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+{
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+	switch (tegra_get_chip_id()) {
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+	case TEGRA194:
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+	case TEGRA234:
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+		if (tegra_get_platform() == 0)
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+			return true;
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+
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+		return false;
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+	}
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+
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+	/*
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+	 * Chips prior to Tegra194 have a different way of determining whether
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+	 * they are silicon or not. Since we never supported simulation on the
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+	 * older Tegra chips, don't bother extracting the information and just
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+	 * report that we're running on silicon.
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+	 */
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+	return true;
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+}
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+
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 u32 tegra_read_straps(void)
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 {
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-	if (strapping_base)
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-		return readl_relaxed(strapping_base);
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-	else
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-		return 0;
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+	WARN(!chipid, "Tegra ABP MISC not yet available\n");
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+
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+	return strapping;
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 }
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81
 
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 u32 tegra_read_ram_code(void)
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@@ -75,46 +94,45 @@
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 static const struct of_device_id apbmisc_match[] __initconst = {
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 	{ .compatible = "nvidia,tegra20-apbmisc", },
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 	{ .compatible = "nvidia,tegra186-misc", },
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+	{ .compatible = "nvidia,tegra194-misc", },
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+	{ .compatible = "nvidia,tegra234-misc", },
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 	{},
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 };
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101
 
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 void __init tegra_init_revision(void)
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 {
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-	u32 id, chip_id, minor_rev;
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-	int rev;
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+	u8 chip_id, minor_rev;
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-	id = tegra_read_chipid();
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-	chip_id = (id >> 8) & 0xff;
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-	minor_rev = (id >> 16) & 0xf;
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+	chip_id = tegra_get_chip_id();
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+	minor_rev = tegra_get_minor_rev();
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108
 
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 	switch (minor_rev) {
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 	case 1:
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-		rev = TEGRA_REVISION_A01;
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+		tegra_sku_info.revision = TEGRA_REVISION_A01;
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 		break;
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 	case 2:
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-		rev = TEGRA_REVISION_A02;
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+		tegra_sku_info.revision = TEGRA_REVISION_A02;
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 		break;
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 	case 3:
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 		if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
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 					   tegra_fuse_read_spare(19)))
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-			rev = TEGRA_REVISION_A03p;
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+			tegra_sku_info.revision = TEGRA_REVISION_A03p;
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 		else
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-			rev = TEGRA_REVISION_A03;
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+			tegra_sku_info.revision = TEGRA_REVISION_A03;
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 		break;
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 	case 4:
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-		rev = TEGRA_REVISION_A04;
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+		tegra_sku_info.revision = TEGRA_REVISION_A04;
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 		break;
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 	default:
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-		rev = TEGRA_REVISION_UNKNOWN;
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+		tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
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 	}
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-
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-	tegra_sku_info.revision = rev;
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129
 
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 	tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
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 }
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132
 
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 void __init tegra_init_apbmisc(void)
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 {
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+	void __iomem *apbmisc_base, *strapping_base;
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 	struct resource apbmisc, straps;
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 	struct device_node *np;
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138
 
..
..
@@ -171,13 +189,21 @@
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 		}
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 	}
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-	apbmisc_base = ioremap_nocache(apbmisc.start, resource_size(&apbmisc));
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-	if (!apbmisc_base)
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+	apbmisc_base = ioremap(apbmisc.start, resource_size(&apbmisc));
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+	if (!apbmisc_base) {
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194
 		pr_err("failed to map APBMISC registers\n");
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+	} else {
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+		chipid = readl_relaxed(apbmisc_base + 4);
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+		iounmap(apbmisc_base);
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+	}
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-	strapping_base = ioremap_nocache(straps.start, resource_size(&straps));
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-	if (!strapping_base)
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+	strapping_base = ioremap(straps.start, resource_size(&straps));
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+	if (!strapping_base) {
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 		pr_err("failed to map strapping options registers\n");
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+	} else {
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+		strapping = readl_relaxed(strapping_base);
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+		iounmap(strapping_base);
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+	}
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207
 
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 	long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
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 }