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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/soc/rockchip/rockchip_debug.c
..
..
@@ -59,7 +59,11 @@
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 #include <linux/irq.h>
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 #include <linux/delay.h>
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61
 
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-#include "../../staging/android/fiq_debugger/fiq_debugger_priv.h"
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+#if IS_ENABLED(CONFIG_ROCKCHIP_MINIDUMP)
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+#include <soc/rockchip/rk_minidump.h>
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+#endif
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+
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+#include "fiq_debugger/fiq_debugger_priv.h"
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 #include "rockchip_debug.h"
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68
 
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 #define EDPCSR_LO			0x0a0
..
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@@ -85,6 +89,22 @@
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 extern struct atomic_notifier_head hardlock_notifier_list;
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90
 extern struct atomic_notifier_head rcu_stall_notifier_list;
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91
 
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+static inline void rockchip_debug_serror_enable(void)
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+{
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+#ifdef CONFIG_ARM64
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+	/* enable SError */
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+	asm volatile("msr	daifclr, #0x4");
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+#endif
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+}
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+
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+static inline void rockchip_debug_serror_disable(void)
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+{
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+#ifdef CONFIG_ARM64
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+	/* disable SError */
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+	asm volatile("msr	daifset, #0x4");
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+#endif
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+}
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+
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 #if IS_ENABLED(CONFIG_FIQ_DEBUGGER)
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 static int rockchip_debug_dump_edpcsr(struct fiq_debugger_output *output)
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 {
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@@ -96,10 +116,7 @@
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 	void __iomem *base;
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 	u32 pu = 0, online = 0;
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118
 
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-#ifdef CONFIG_ARM64
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-	/* disable SError */
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-	asm volatile("msr	daifset, #0x4");
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-#endif
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+	rockchip_debug_serror_disable();
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120
 
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 	while (rockchip_cpu_debug[i]) {
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 		online = cpu_online(i);
..
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@@ -154,11 +171,7 @@
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 		printed = 0;
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 	}
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173
 
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-#ifdef CONFIG_ARM64
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-	/* enable SError */
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-	asm volatile("msr	daifclr, #0x4");
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-#endif
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-
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+	rockchip_debug_serror_enable();
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 	return NOTIFY_OK;
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 }
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177
 
..
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@@ -173,8 +186,7 @@
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 	void __iomem *base;
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 	u32 pu = 0, online = 0;
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188
 
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-	/* disable SError */
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-	asm volatile("msr	daifset, #0x4");
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+	rockchip_debug_serror_disable();
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190
 
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 	while (rockchip_cs_pmu[i]) {
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 		online = cpu_online(i);
..
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@@ -233,8 +245,7 @@
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 		prev_pc = NULL;
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 		printed = 0;
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 	}
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-	/* enable SError */
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-	asm volatile("msr	daifclr, #0x4");
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+	rockchip_debug_serror_enable();
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 	return NOTIFY_OK;
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 }
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 #else
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@@ -243,7 +254,6 @@
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 	return 0;
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 }
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 #endif
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-
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257
 
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 int rockchip_debug_dump_pcsr(struct fiq_debugger_output *output)
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 {
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@@ -267,10 +277,7 @@
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 	void __iomem *base;
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 	u32 pu = 0;
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279
 
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-#ifdef CONFIG_ARM64
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-	/* disable SError */
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-	asm volatile("msr	daifset, #0x4");
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-#endif
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+	rockchip_debug_serror_disable();
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281
 
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 	/*
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 	 * The panic handler will try to shut down the other CPUs.
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@@ -324,11 +331,6 @@
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 		printed = 0;
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 	}
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333
 
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-#ifdef CONFIG_ARM64
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-	/* enable SError */
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-	asm volatile("msr	daifclr, #0x4");
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-#endif
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-
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 	return NOTIFY_OK;
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 }
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..
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@@ -344,8 +346,7 @@
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 	void __iomem *base;
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 	u32 pu = 0;
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348
 
347
-	/* disable SError */
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-	asm volatile("msr	daifset, #0x4");
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+	rockchip_debug_serror_disable();
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350
 
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 	/*
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 	 * The panic handler will try to shut down the other CPUs.
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@@ -403,8 +404,7 @@
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 		prev_pc = NULL;
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 		printed = 0;
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 	}
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-	/* enable SError */
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-	asm volatile("msr	daifclr, #0x4");
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+
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 	return NOTIFY_OK;
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 }
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 #else
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@@ -425,7 +425,7 @@
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 	struct irq_desc *desc;
426
426
 
427
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 	if (i > nr_irqs)
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-		return -EINVAL;
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+		return -1;
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429
 
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 	/* print header and calculate the width of the first column */
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 	if (i == 0) {
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@@ -439,15 +439,15 @@
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439
 	}
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440
 
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 	desc = irq_to_desc(i);
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-	if (!desc)
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-		return -EINVAL;
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+	if (!desc || (desc->status_use_accessors & IRQ_HIDDEN))
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+		goto outsparse;
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444
 
445
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 	if (desc->kstat_irqs)
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 		for_each_possible_cpu(j)
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 			any_count |= *per_cpu_ptr(desc->kstat_irqs, j);
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448
 
449
-	if ((!desc->action || (desc->action && desc->action == &chained_action)) && !any_count)
450
-		return -EINVAL;
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+	if ((!desc->action) && !any_count)
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+		goto outsparse;
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451
 
452
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 	buf += sprintf(buf, "%*d: ", prec, i);
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453
 	for_each_possible_cpu(j)
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@@ -463,7 +463,7 @@
463
463
 		buf += sprintf(buf, " %8s", "None");
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 	}
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465
 	if (desc->irq_data.domain)
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-		buf += sprintf(buf, " %*d", prec, (int) desc->irq_data.hwirq);
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+		buf += sprintf(buf, " %*lu", prec, desc->irq_data.hwirq);
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467
 	else
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 		buf += sprintf(buf, " %*s", prec, "");
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469
 #ifdef CONFIG_GENERIC_IRQ_SHOW_LEVEL
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@@ -481,6 +481,8 @@
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481
 
482
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 	sprintf(buf, "\n");
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483
 	return 0;
484
+outsparse:
485
+	return -1;
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486
 }
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487
 
486
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 static void rockchip_panic_notify_dump_irqs(void)
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@@ -506,8 +508,73 @@
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 	rockchip_panic_notify_dump_irqs();
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 	return NOTIFY_OK;
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510
 }
511
+
512
+static int rockchip_hardlock_notify(struct notifier_block *nb,
513
+				    unsigned long event, void *p)
514
+{
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+	u64 pmpcsr;
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+	int el;
517
+	u32 pu = 0;
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+	void *pc = NULL;
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+	void __iomem *base;
520
+	unsigned long edpcsr;
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+	unsigned long cpu = event;
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+
523
+	rockchip_debug_serror_disable();
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+
525
+	pu = (u32)readl(rockchip_cpu_debug[cpu] + EDPRSR) & EDPRSR_PU;
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+	if (pu != EDPRSR_PU) {
527
+		pr_err("CPU%ld power down\n", cpu);
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+		return NOTIFY_OK;
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+	}
530
+
531
+	if (edpcsr_present) {
532
+		base = rockchip_cpu_debug[cpu];
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+		/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
534
+		writel(EDLAR_UNLOCK, base + EDLAR);
535
+		if (sizeof(edpcsr) == 8)
536
+			edpcsr = ((u64)readl(base + EDPCSR_LO)) |
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+				 ((u64)readl(base + EDPCSR_HI) << 32);
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+		else
539
+			edpcsr = (u32)readl(base + EDPCSR_LO);
540
+
541
+		/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
542
+		pc = (void *)(edpcsr & ~1);
543
+	} else {
544
+		base = rockchip_cs_pmu[cpu];
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+		pmpcsr = ((u64)readl(base + PMPCSR_LO)) |
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+			 ((u64)readl(base + PMPCSR_HI) << 32);
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+		el = (pmpcsr >> 61) & 0x3;
548
+		if (el == 2)
549
+			pmpcsr |= 0xff00000000000000;
550
+		else
551
+			pmpcsr &= 0x0fffffffffffffff;
552
+		/* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
553
+		pc = (void *)(pmpcsr & ~1);
554
+	}
555
+
556
+	rockchip_debug_serror_enable();
557
+
558
+#if IS_ENABLED(CONFIG_ROCKCHIP_MINIDUMP)
559
+	rk_minidump_hardlock_notify(nb, event, pc);
560
+#endif
561
+
562
+#if !IS_ENABLED(CONFIG_BOOTPARAM_HARDLOCKUP_PANIC)
563
+	rockchip_panic_notify(nb, event, p);
564
+#endif
565
+	return NOTIFY_OK;
566
+}
567
+
509
568
 static struct notifier_block rockchip_panic_nb = {
510
569
 	.notifier_call = rockchip_panic_notify,
570
+};
571
+
572
+static struct notifier_block rockchip_rcu_stall_nb = {
573
+	.notifier_call = rockchip_panic_notify,
574
+};
575
+
576
+static struct notifier_block rockchip_hardlock_nb = {
577
+	.notifier_call = rockchip_hardlock_notify,
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578
 };
512
579
 
513
580
 static const struct of_device_id rockchip_debug_dt_match[] __initconst = {
..
..
@@ -525,7 +592,6 @@
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592
 	},
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593
 	{ /* sentinel */ },
527
594
 };
528
-
529
595
 
530
596
 static int __init rockchip_debug_init(void)
531
597
 {
..
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@@ -569,14 +635,15 @@
569
635
 		return -ENODEV;
570
636
 
571
637
 	atomic_notifier_chain_register(&panic_notifier_list,
572
-					&rockchip_panic_nb);
638
+				       &rockchip_panic_nb);
639
+	if (IS_ENABLED(CONFIG_NO_GKI)) {
640
+		if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
641
+			atomic_notifier_chain_register(&hardlock_notifier_list,
642
+						       &rockchip_hardlock_nb);
573
643
 
574
-	if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
575
-		atomic_notifier_chain_register(&hardlock_notifier_list,
576
-						&rockchip_panic_nb);
577
-
578
-	atomic_notifier_chain_register(&rcu_stall_notifier_list,
579
-					&rockchip_panic_nb);
644
+		atomic_notifier_chain_register(&rcu_stall_notifier_list,
645
+					       &rockchip_rcu_stall_nb);
646
+	}
580
647
 
581
648
 	return 0;
582
649
 }
..
..
@@ -588,13 +655,14 @@
588
655
 
589
656
 	atomic_notifier_chain_unregister(&panic_notifier_list,
590
657
 					 &rockchip_panic_nb);
658
+	if (IS_ENABLED(CONFIG_NO_GKI)) {
659
+		if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
660
+			atomic_notifier_chain_unregister(&hardlock_notifier_list,
661
+							 &rockchip_hardlock_nb);
591
662
 
592
-	if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
593
-		atomic_notifier_chain_unregister(&hardlock_notifier_list,
594
-						 &rockchip_panic_nb);
595
-
596
-	atomic_notifier_chain_unregister(&rcu_stall_notifier_list,
597
-					 &rockchip_panic_nb);
663
+		atomic_notifier_chain_unregister(&rcu_stall_notifier_list,
664
+						 &rockchip_rcu_stall_nb);
665
+	}
598
666
 
599
667
 	while (rockchip_cpu_debug[i])
600
668
 		iounmap(rockchip_cpu_debug[i++]);