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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/soc/bcm/brcmstb/pm/pm-arm.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * ARM-specific support for Broadcom STB S2/S3/S5 power management
34  *
....@@ -8,15 +9,6 @@
89  *     treat this mode like a soft power-off, with wakeup allowed from AON
910  *
1011  * Copyright © 2014-2017 Broadcom
11
- *
12
- * This program is free software; you can redistribute it and/or modify
13
- * it under the terms of the GNU General Public License version 2 as
14
- * published by the Free Software Foundation.
15
- *
16
- * This program is distributed in the hope that it will be useful,
17
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
18
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19
- * GNU General Public License for more details.
2012  */
2113 
2214 #define pr_fmt(fmt) "brcmstb-pm: " fmt
....@@ -689,13 +681,14 @@
689681 	const struct of_device_id *of_id = NULL;
690682 	struct device_node *dn;
691683 	void __iomem *base;
692
-	int ret, i;
684
+	int ret, i, s;
693685 
694686 	/* AON ctrl registers */
695687 	base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL);
696688 	if (IS_ERR(base)) {
697689 		pr_err("error mapping AON_CTRL\n");
698
-		return PTR_ERR(base);
690
+		ret = PTR_ERR(base);
691
+		goto aon_err;
699692 	}
700693 	ctrl.aon_ctrl_base = base;
701694 
....@@ -705,8 +698,10 @@
705698 		/* Assume standard offset */
706699 		ctrl.aon_sram = ctrl.aon_ctrl_base +
707700 				     AON_CTRL_SYSTEM_DATA_RAM_OFS;
701
+		s = 0;
708702 	} else {
709703 		ctrl.aon_sram = base;
704
+		s = 1;
710705 	}
711706 
712707 	writel_relaxed(0, ctrl.aon_sram + AON_REG_PANIC);
....@@ -716,7 +711,8 @@
716711 				     (const void **)&ddr_phy_data);
717712 	if (IS_ERR(base)) {
718713 		pr_err("error mapping DDR PHY\n");
719
-		return PTR_ERR(base);
714
+		ret = PTR_ERR(base);
715
+		goto ddr_phy_err;
720716 	}
721717 	ctrl.support_warm_boot = ddr_phy_data->supports_warm_boot;
722718 	ctrl.pll_status_offset = ddr_phy_data->pll_status_offset;
....@@ -736,17 +732,20 @@
736732 	for_each_matching_node(dn, ddr_shimphy_dt_ids) {
737733 		i = ctrl.num_memc;
738734 		if (i >= MAX_NUM_MEMC) {
735
+			of_node_put(dn);
739736 			pr_warn("too many MEMCs (max %d)\n", MAX_NUM_MEMC);
740737 			break;
741738 		}
742739 
743740 		base = of_io_request_and_map(dn, 0, dn->full_name);
744741 		if (IS_ERR(base)) {
742
+			of_node_put(dn);
745743 			if (!ctrl.support_warm_boot)
746744 				break;
747745 
748746 			pr_err("error mapping DDR SHIMPHY %d\n", i);
749
-			return PTR_ERR(base);
747
+			ret = PTR_ERR(base);
748
+			goto ddr_shimphy_err;
750749 		}
751750 		ctrl.memcs[i].ddr_shimphy_base = base;
752751 		ctrl.num_memc++;
....@@ -757,14 +756,18 @@
757756 	for_each_matching_node(dn, brcmstb_memc_of_match) {
758757 		base = of_iomap(dn, 0);
759758 		if (!base) {
759
+			of_node_put(dn);
760760 			pr_err("error mapping DDR Sequencer %d\n", i);
761
-			return -ENOMEM;
761
+			ret = -ENOMEM;
762
+			goto brcmstb_memc_err;
762763 		}
763764 
764765 		of_id = of_match_node(brcmstb_memc_of_match, dn);
765766 		if (!of_id) {
766767 			iounmap(base);
767
-			return -EINVAL;
768
+			of_node_put(dn);
769
+			ret = -EINVAL;
770
+			goto brcmstb_memc_err;
768771 		}
769772 
770773 		ddr_seq_data = of_id->data;
....@@ -784,20 +787,24 @@
784787 	dn = of_find_matching_node(NULL, sram_dt_ids);
785788 	if (!dn) {
786789 		pr_err("SRAM not found\n");
787
-		return -EINVAL;
790
+		ret = -EINVAL;
791
+		goto brcmstb_memc_err;
788792 	}
789793 
790794 	ret = brcmstb_init_sram(dn);
795
+	of_node_put(dn);
791796 	if (ret) {
792797 		pr_err("error setting up SRAM for PM\n");
793
-		return ret;
798
+		goto brcmstb_memc_err;
794799 	}
795800 
796801 	ctrl.pdev = pdev;
797802 
798803 	ctrl.s3_params = kmalloc(sizeof(*ctrl.s3_params), GFP_KERNEL);
799
-	if (!ctrl.s3_params)
800
-		return -ENOMEM;
804
+	if (!ctrl.s3_params) {
805
+		ret = -ENOMEM;
806
+		goto s3_params_err;
807
+	}
801808 	ctrl.s3_params_pa = dma_map_single(&pdev->dev, ctrl.s3_params,
802809 					   sizeof(*ctrl.s3_params),
803810 					   DMA_TO_DEVICE);
....@@ -817,7 +824,21 @@
817824 
818825 out:
819826 	kfree(ctrl.s3_params);
827
+s3_params_err:
828
+	iounmap(ctrl.boot_sram);
829
+brcmstb_memc_err:
830
+	for (i--; i >= 0; i--)
831
+		iounmap(ctrl.memcs[i].ddr_ctrl);
832
+ddr_shimphy_err:
833
+	for (i = 0; i < ctrl.num_memc; i++)
834
+		iounmap(ctrl.memcs[i].ddr_shimphy_base);
820835 
836
+	iounmap(ctrl.memcs[0].ddr_phy_base);
837
+ddr_phy_err:
838
+	iounmap(ctrl.aon_ctrl_base);
839
+	if (s)
840
+		iounmap(ctrl.aon_sram);
841
+aon_err:
821842 	pr_warn("PM: initialization failed with code %d\n", ret);
822843 
823844 	return ret;