~hc/RK356X_SDK_RELEASE.git

..	..	@@ -17,6 +17,7 @@
17	17	#include <linux/debugfs.h>
18	18	#include <linux/delay.h>
19	19	#include <linux/export.h>
	20	+#include <linux/gpio/consumer.h>
20	21	#include <linux/interrupt.h>
21	22	#include <linux/iopoll.h>
22	23	#include <linux/irq.h>
..	..	@@ -30,6 +31,7 @@
30	31	#include <linux/of_platform.h>
31	32	#include <linux/pci.h>
32	33	#include <linux/phy/phy.h>
	34	+#include <linux/pinctrl/consumer.h>
33	35	#include <linux/platform_device.h>
34	36	#include <linux/reset.h>
35	37	#include <linux/sizes.h>
..	..	@@ -95,7 +97,8 @@
95	97	#define AFI_MSI_EN_VEC7 0xa8
96	98
97	99	#define AFI_CONFIGURATION 0xac
98		-#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
	100	+#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
	101	+#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31)
99	102
100	103	#define AFI_FPCI_ERROR_MASKS 0xb0
101	104
..	..	@@ -159,13 +162,14 @@
159	162	#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211 (0x1 << 20)
160	163	#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
161	164	#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111 (0x2 << 20)
	165	+#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(x) (1 << ((x) + 29))
	166	+#define AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL (0x7 << 29)
162	167
163	168	#define AFI_FUSE 0x104
164	169	#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
165	170
166	171	#define AFI_PEX0_CTRL 0x110
167	172	#define AFI_PEX1_CTRL 0x118
168		-#define AFI_PEX2_CTRL 0x128
169	173	#define AFI_PEX_CTRL_RST (1 << 0)
170	174	#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
171	175	#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
..	..	@@ -177,19 +181,66 @@
177	181
178	182	#define AFI_PEXBIAS_CTRL_0 0x168
179	183
	184	+#define RP_ECTL_2_R1 0x00000e84
	185	+#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff
	186	+
	187	+#define RP_ECTL_4_R1 0x00000e8c
	188	+#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK (0xffff << 16)
	189	+#define RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT 16
	190	+
	191	+#define RP_ECTL_5_R1 0x00000e90
	192	+#define RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK 0xffffffff
	193	+
	194	+#define RP_ECTL_6_R1 0x00000e94
	195	+#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff
	196	+
	197	+#define RP_ECTL_2_R2 0x00000ea4
	198	+#define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff
	199	+
	200	+#define RP_ECTL_4_R2 0x00000eac
	201	+#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK (0xffff << 16)
	202	+#define RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT 16
	203	+
	204	+#define RP_ECTL_5_R2 0x00000eb0
	205	+#define RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK 0xffffffff
	206	+
	207	+#define RP_ECTL_6_R2 0x00000eb4
	208	+#define RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK 0xffffffff
	209	+
180	210	#define RP_VEND_XP 0x00000f00
181		-#define RP_VEND_XP_DL_UP (1 << 30)
	211	+#define RP_VEND_XP_DL_UP (1 << 30)
	212	+#define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27)
	213	+#define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28)
	214	+#define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18)
	215	+
	216	+#define RP_VEND_CTL0 0x00000f44
	217	+#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12)
	218	+#define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12)
	219	+
	220	+#define RP_VEND_CTL1 0x00000f48
	221	+#define RP_VEND_CTL1_ERPT (1 << 13)
	222	+
	223	+#define RP_VEND_XP_BIST 0x00000f4c
	224	+#define RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28)
182	225
183	226	#define RP_VEND_CTL2 0x00000fa8
184	227	#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
185	228
186	229	#define RP_PRIV_MISC 0x00000fe0
187		-#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
188		-#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
	230	+#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
	231	+#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
	232	+#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK (0x7f << 16)
	233	+#define RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD (0xf << 16)
	234	+#define RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE (1 << 23)
	235	+#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK (0x7f << 24)
	236	+#define RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD (0xf << 24)
	237	+#define RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE (1 << 31)
189	238
190	239	#define RP_LINK_CONTROL_STATUS 0x00000090
191	240	#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
192	241	#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
	242	+
	243	+#define RP_LINK_CONTROL_STATUS_2 0x000000b0
193	244
194	245	#define PADS_CTL_SEL 0x0000009c
195	246
..	..	@@ -226,14 +277,15 @@
226	277	#define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
227	278
228	279	#define PME_ACK_TIMEOUT 10000
	280	+#define LINK_RETRAIN_TIMEOUT 100000 /* in usec */
229	281
230	282	struct tegra_msi {
231	283	struct msi_controller chip;
232	284	DECLARE_BITMAP(used, INT_PCI_MSI_NR);
233	285	struct irq_domain *domain;
234		- unsigned long pages;
235	286	struct mutex lock;
236		- u64 phys;
	287	+ void *virt;
	288	+ dma_addr_t phys;
237	289	int irq;
238	290	};
239	291
..	..	@@ -249,10 +301,12 @@
249	301	unsigned int num_ports;
250	302	const struct tegra_pcie_port_soc *ports;
251	303	unsigned int msi_base_shift;
	304	+ unsigned long afi_pex2_ctrl;
252	305	u32 pads_pll_ctl;
253	306	u32 tx_ref_sel;
254	307	u32 pads_refclk_cfg0;
255	308	u32 pads_refclk_cfg1;
	309	+ u32 update_fc_threshold;
256	310	bool has_pex_clkreq_en;
257	311	bool has_pex_bias_ctrl;
258	312	bool has_intr_prsnt_sense;
..	..	@@ -260,6 +314,23 @@
260	314	bool has_gen2;
261	315	bool force_pca_enable;
262	316	bool program_uphy;
	317	+ bool update_clamp_threshold;
	318	+ bool program_deskew_time;
	319	+ bool update_fc_timer;
	320	+ bool has_cache_bars;
	321	+ struct {
	322	+ struct {
	323	+ u32 rp_ectl_2_r1;
	324	+ u32 rp_ectl_4_r1;
	325	+ u32 rp_ectl_5_r1;
	326	+ u32 rp_ectl_6_r1;
	327	+ u32 rp_ectl_2_r2;
	328	+ u32 rp_ectl_4_r2;
	329	+ u32 rp_ectl_5_r2;
	330	+ u32 rp_ectl_6_r2;
	331	+ } regs;
	332	+ bool enable;
	333	+ } ectl;
263	334	};
264	335
265	336	static inline struct tegra_msi to_tegra_msi(struct msi_controller chip)
..	..	@@ -276,16 +347,6 @@
276	347	int irq;
277	348
278	349	struct resource cs;
279		- struct resource io;
280		- struct resource pio;
281		- struct resource mem;
282		- struct resource prefetch;
283		- struct resource busn;
284		-
285		- struct {
286		- resource_size_t mem;
287		- resource_size_t io;
288		- } offset;
289	350
290	351	struct clk *pex_clk;
291	352	struct clk *afi_clk;
..	..	@@ -321,6 +382,8 @@
321	382	unsigned int lanes;
322	383
323	384	struct phy **phys;
	385	+
	386	+ struct gpio_desc *reset_gpio;
324	387	};
325	388
326	389	struct tegra_pcie_bus {
..	..	@@ -440,6 +503,7 @@
440	503
441	504	static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
442	505	{
	506	+ const struct tegra_pcie_soc *soc = port->pcie->soc;
443	507	unsigned long ret = 0;
444	508
445	509	switch (port->index) {
..	..	@@ -452,7 +516,7 @@
452	516	break;
453	517
454	518	case 2:
455		- ret = AFI_PEX2_CTRL;
	519	+ ret = soc->afi_pex2_ctrl;
456	520	break;
457	521	}
458	522
..	..	@@ -465,15 +529,145 @@
465	529	unsigned long value;
466	530
467	531	/* pulse reset signal */
468		- value = afi_readl(port->pcie, ctrl);
469		- value &= ~AFI_PEX_CTRL_RST;
470		- afi_writel(port->pcie, value, ctrl);
	532	+ if (port->reset_gpio) {
	533	+ gpiod_set_value(port->reset_gpio, 1);
	534	+ } else {
	535	+ value = afi_readl(port->pcie, ctrl);
	536	+ value &= ~AFI_PEX_CTRL_RST;
	537	+ afi_writel(port->pcie, value, ctrl);
	538	+ }
471	539
472	540	usleep_range(1000, 2000);
473	541
474		- value = afi_readl(port->pcie, ctrl);
475		- value \|= AFI_PEX_CTRL_RST;
476		- afi_writel(port->pcie, value, ctrl);
	542	+ if (port->reset_gpio) {
	543	+ gpiod_set_value(port->reset_gpio, 0);
	544	+ } else {
	545	+ value = afi_readl(port->pcie, ctrl);
	546	+ value \|= AFI_PEX_CTRL_RST;
	547	+ afi_writel(port->pcie, value, ctrl);
	548	+ }
	549	+}
	550	+
	551	+static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
	552	+{
	553	+ const struct tegra_pcie_soc *soc = port->pcie->soc;
	554	+ u32 value;
	555	+
	556	+ /* Enable AER capability */
	557	+ value = readl(port->base + RP_VEND_CTL1);
	558	+ value \|= RP_VEND_CTL1_ERPT;
	559	+ writel(value, port->base + RP_VEND_CTL1);
	560	+
	561	+ /* Optimal settings to enhance bandwidth */
	562	+ value = readl(port->base + RP_VEND_XP);
	563	+ value \|= RP_VEND_XP_OPPORTUNISTIC_ACK;
	564	+ value \|= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
	565	+ writel(value, port->base + RP_VEND_XP);
	566	+
	567	+ /*
	568	+ * LTSSM will wait for DLLP to finish before entering L1 or L2,
	569	+ * to avoid truncation of PM messages which results in receiver errors
	570	+ */
	571	+ value = readl(port->base + RP_VEND_XP_BIST);
	572	+ value \|= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
	573	+ writel(value, port->base + RP_VEND_XP_BIST);
	574	+
	575	+ value = readl(port->base + RP_PRIV_MISC);
	576	+ value \|= RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE;
	577	+ value \|= RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE;
	578	+
	579	+ if (soc->update_clamp_threshold) {
	580	+ value &= ~(RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK \|
	581	+ RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK);
	582	+ value \|= RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD \|
	583	+ RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD;
	584	+ }
	585	+
	586	+ writel(value, port->base + RP_PRIV_MISC);
	587	+}
	588	+
	589	+static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
	590	+{
	591	+ const struct tegra_pcie_soc *soc = port->pcie->soc;
	592	+ u32 value;
	593	+
	594	+ value = readl(port->base + RP_ECTL_2_R1);
	595	+ value &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK;
	596	+ value \|= soc->ectl.regs.rp_ectl_2_r1;
	597	+ writel(value, port->base + RP_ECTL_2_R1);
	598	+
	599	+ value = readl(port->base + RP_ECTL_4_R1);
	600	+ value &= ~RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK;
	601	+ value \|= soc->ectl.regs.rp_ectl_4_r1 <<
	602	+ RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT;
	603	+ writel(value, port->base + RP_ECTL_4_R1);
	604	+
	605	+ value = readl(port->base + RP_ECTL_5_R1);
	606	+ value &= ~RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK;
	607	+ value \|= soc->ectl.regs.rp_ectl_5_r1;
	608	+ writel(value, port->base + RP_ECTL_5_R1);
	609	+
	610	+ value = readl(port->base + RP_ECTL_6_R1);
	611	+ value &= ~RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK;
	612	+ value \|= soc->ectl.regs.rp_ectl_6_r1;
	613	+ writel(value, port->base + RP_ECTL_6_R1);
	614	+
	615	+ value = readl(port->base + RP_ECTL_2_R2);
	616	+ value &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK;
	617	+ value \|= soc->ectl.regs.rp_ectl_2_r2;
	618	+ writel(value, port->base + RP_ECTL_2_R2);
	619	+
	620	+ value = readl(port->base + RP_ECTL_4_R2);
	621	+ value &= ~RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK;
	622	+ value \|= soc->ectl.regs.rp_ectl_4_r2 <<
	623	+ RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT;
	624	+ writel(value, port->base + RP_ECTL_4_R2);
	625	+
	626	+ value = readl(port->base + RP_ECTL_5_R2);
	627	+ value &= ~RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK;
	628	+ value \|= soc->ectl.regs.rp_ectl_5_r2;
	629	+ writel(value, port->base + RP_ECTL_5_R2);
	630	+
	631	+ value = readl(port->base + RP_ECTL_6_R2);
	632	+ value &= ~RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK;
	633	+ value \|= soc->ectl.regs.rp_ectl_6_r2;
	634	+ writel(value, port->base + RP_ECTL_6_R2);
	635	+}
	636	+
	637	+static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
	638	+{
	639	+ const struct tegra_pcie_soc *soc = port->pcie->soc;
	640	+ u32 value;
	641	+
	642	+ /*
	643	+ * Sometimes link speed change from Gen2 to Gen1 fails due to
	644	+ * instability in deskew logic on lane-0. Increase the deskew
	645	+ * retry time to resolve this issue.
	646	+ */
	647	+ if (soc->program_deskew_time) {
	648	+ value = readl(port->base + RP_VEND_CTL0);
	649	+ value &= ~RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK;
	650	+ value \|= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
	651	+ writel(value, port->base + RP_VEND_CTL0);
	652	+ }
	653	+
	654	+ if (soc->update_fc_timer) {
	655	+ value = readl(port->base + RP_VEND_XP);
	656	+ value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
	657	+ value \|= soc->update_fc_threshold;
	658	+ writel(value, port->base + RP_VEND_XP);
	659	+ }
	660	+
	661	+ /*
	662	+ * PCIe link doesn't come up with few legacy PCIe endpoints if
	663	+ * root port advertises both Gen-1 and Gen-2 speeds in Tegra.
	664	+ * Hence, the strategy followed here is to initially advertise
	665	+ * only Gen-1 and after link is up, retrain link to Gen-2 speed
	666	+ */
	667	+ value = readl(port->base + RP_LINK_CONTROL_STATUS_2);
	668	+ value &= ~PCI_EXP_LNKSTA_CLS;
	669	+ value \|= PCI_EXP_LNKSTA_CLS_2_5GB;
	670	+ writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
477	671	}
478	672
479	673	static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
..	..	@@ -500,6 +694,13 @@
500	694	value \|= RP_VEND_CTL2_PCA_ENABLE;
501	695	writel(value, port->base + RP_VEND_CTL2);
502	696	}
	697	+
	698	+ tegra_pcie_enable_rp_features(port);
	699	+
	700	+ if (soc->ectl.enable)
	701	+ tegra_pcie_program_ectl_settings(port);
	702	+
	703	+ tegra_pcie_apply_sw_fixup(port);
503	704	}
504	705
505	706	static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
..	..	@@ -521,6 +722,12 @@
521	722
522	723	value &= ~AFI_PEX_CTRL_REFCLK_EN;
523	724	afi_writel(port->pcie, value, ctrl);
	725	+
	726	+ /* disable PCIe port and set CLKREQ# as GPIO to allow PLLE power down */
	727	+ value = afi_readl(port->pcie, AFI_PCIE_CONFIG);
	728	+ value \|= AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
	729	+ value \|= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);
	730	+ afi_writel(port->pcie, value, AFI_PCIE_CONFIG);
524	731	}
525	732
526	733	static void tegra_pcie_port_free(struct tegra_pcie_port *port)
..	..	@@ -554,38 +761,6 @@
554	761	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_relax_enable);
555	762	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_relax_enable);
556	763	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_relax_enable);
557		-
558		-static int tegra_pcie_request_resources(struct tegra_pcie *pcie)
559		-{
560		- struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
561		- struct list_head *windows = &host->windows;
562		- struct device *dev = pcie->dev;
563		- int err;
564		-
565		- pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
566		- pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
567		- pci_add_resource_offset(windows, &pcie->prefetch, pcie->offset.mem);
568		- pci_add_resource(windows, &pcie->busn);
569		-
570		- err = devm_request_pci_bus_resources(dev, windows);
571		- if (err < 0) {
572		- pci_free_resource_list(windows);
573		- return err;
574		- }
575		-
576		- pci_remap_iospace(&pcie->pio, pcie->io.start);
577		-
578		- return 0;
579		-}
580		-
581		-static void tegra_pcie_free_resources(struct tegra_pcie *pcie)
582		-{
583		- struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
584		- struct list_head *windows = &host->windows;
585		-
586		- pci_unmap_iospace(&pcie->pio);
587		- pci_free_resource_list(windows);
588		-}
589	764
590	765	static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
591	766	{
..	..	@@ -638,7 +813,7 @@
638	813	* do not pollute kernel log with master abort reports since they
639	814	* happen a lot during enumeration
640	815	*/
641		- if (code == AFI_INTR_MASTER_ABORT)
	816	+ if (code == AFI_INTR_MASTER_ABORT \|\| code == AFI_INTR_PE_PRSNT_SENSE)
642	817	dev_dbg(dev, "%s, signature: %08x\n", err_msg[code], signature);
643	818	else
644	819	dev_err(dev, "%s, signature: %08x\n", err_msg[code], signature);
..	..	@@ -667,36 +842,49 @@
667	842	*/
668	843	static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
669	844	{
670		- u32 fpci_bar, size, axi_address;
	845	+ u32 size;
	846	+ struct resource_entry *entry;
	847	+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
671	848
672	849	/* Bar 0: type 1 extended configuration space */
673	850	size = resource_size(&pcie->cs);
674	851	afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START);
675	852	afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
676	853
677		- /* Bar 1: downstream IO bar */
678		- fpci_bar = 0xfdfc0000;
679		- size = resource_size(&pcie->io);
680		- axi_address = pcie->io.start;
681		- afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
682		- afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
683		- afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
	854	+ resource_list_for_each_entry(entry, &bridge->windows) {
	855	+ u32 fpci_bar, axi_address;
	856	+ struct resource *res = entry->res;
684	857
685		- /* Bar 2: prefetchable memory BAR */
686		- fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) \| 0x1;
687		- size = resource_size(&pcie->prefetch);
688		- axi_address = pcie->prefetch.start;
689		- afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
690		- afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
691		- afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
	858	+ size = resource_size(res);
692	859
693		- /* Bar 3: non prefetchable memory BAR */
694		- fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) \| 0x1;
695		- size = resource_size(&pcie->mem);
696		- axi_address = pcie->mem.start;
697		- afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
698		- afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
699		- afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
	860	+ switch (resource_type(res)) {
	861	+ case IORESOURCE_IO:
	862	+ /* Bar 1: downstream IO bar */
	863	+ fpci_bar = 0xfdfc0000;
	864	+ axi_address = pci_pio_to_address(res->start);
	865	+ afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
	866	+ afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
	867	+ afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
	868	+ break;
	869	+ case IORESOURCE_MEM:
	870	+ fpci_bar = (((res->start >> 12) & 0x0fffffff) << 4) \| 0x1;
	871	+ axi_address = res->start;
	872	+
	873	+ if (res->flags & IORESOURCE_PREFETCH) {
	874	+ /* Bar 2: prefetchable memory BAR */
	875	+ afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
	876	+ afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
	877	+ afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
	878	+
	879	+ } else {
	880	+ /* Bar 3: non prefetchable memory BAR */
	881	+ afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
	882	+ afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
	883	+ afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
	884	+ }
	885	+ break;
	886	+ }
	887	+ }
700	888
701	889	/* NULL out the remaining BARs as they are not used */
702	890	afi_writel(pcie, 0, AFI_AXI_BAR4_START);
..	..	@@ -707,11 +895,13 @@
707	895	afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
708	896	afi_writel(pcie, 0, AFI_FPCI_BAR5);
709	897
710		- /* map all upstream transactions as uncached */
711		- afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
712		- afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
713		- afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
714		- afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
	898	+ if (pcie->soc->has_cache_bars) {
	899	+ /* map all upstream transactions as uncached */
	900	+ afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
	901	+ afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
	902	+ afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
	903	+ afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
	904	+ }
715	905
716	906	/* MSI translations are setup only when needed */
717	907	afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
..	..	@@ -855,7 +1045,6 @@
855	1045	static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
856	1046	{
857	1047	struct device *dev = pcie->dev;
858		- const struct tegra_pcie_soc *soc = pcie->soc;
859	1048	struct tegra_pcie_port *port;
860	1049	int err;
861	1050
..	..	@@ -880,12 +1069,6 @@
880	1069	return err;
881	1070	}
882	1071	}
883		-
884		- /* Configure the reference clock driver */
885		- pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
886		-
887		- if (soc->num_ports > 2)
888		- pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
889	1072
890	1073	return 0;
891	1074	}
..	..	@@ -921,13 +1104,11 @@
921	1104	return 0;
922	1105	}
923	1106
924		-static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
	1107	+static void tegra_pcie_enable_controller(struct tegra_pcie *pcie)
925	1108	{
926		- struct device *dev = pcie->dev;
927	1109	const struct tegra_pcie_soc *soc = pcie->soc;
928	1110	struct tegra_pcie_port *port;
929	1111	unsigned long value;
930		- int err;
931	1112
932	1113	/* enable PLL power down */
933	1114	if (pcie->phy) {
..	..	@@ -945,9 +1126,12 @@
945	1126	value = afi_readl(pcie, AFI_PCIE_CONFIG);
946	1127	value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
947	1128	value \|= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL \| pcie->xbar_config;
	1129	+ value \|= AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO_ALL;
948	1130
949		- list_for_each_entry(port, &pcie->ports, list)
	1131	+ list_for_each_entry(port, &pcie->ports, list) {
950	1132	value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
	1133	+ value &= ~AFI_PCIE_CONFIG_PCIE_CLKREQ_GPIO(port->index);
	1134	+ }
951	1135
952	1136	afi_writel(pcie, value, AFI_PCIE_CONFIG);
953	1137
..	..	@@ -961,20 +1145,10 @@
961	1145	afi_writel(pcie, value, AFI_FUSE);
962	1146	}
963	1147
964		- if (soc->program_uphy) {
965		- err = tegra_pcie_phy_power_on(pcie);
966		- if (err < 0) {
967		- dev_err(dev, "failed to power on PHY(s): %d\n", err);
968		- return err;
969		- }
970		- }
971		-
972		- /* take the PCIe interface module out of reset */
973		- reset_control_deassert(pcie->pcie_xrst);
974		-
975		- /* finally enable PCIe */
	1148	+ /* Disable AFI dynamic clock gating and enable PCIe */
976	1149	value = afi_readl(pcie, AFI_CONFIGURATION);
977	1150	value \|= AFI_CONFIGURATION_EN_FPCI;
	1151	+ value \|= AFI_CONFIGURATION_CLKEN_OVERRIDE;
978	1152	afi_writel(pcie, value, AFI_CONFIGURATION);
979	1153
980	1154	value = AFI_INTR_EN_INI_SLVERR \| AFI_INTR_EN_INI_DECERR \|
..	..	@@ -992,22 +1166,6 @@
992	1166
993	1167	/* disable all exceptions */
994	1168	afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
995		-
996		- return 0;
997		-}
998		-
999		-static void tegra_pcie_disable_controller(struct tegra_pcie *pcie)
1000		-{
1001		- int err;
1002		-
1003		- reset_control_assert(pcie->pcie_xrst);
1004		-
1005		- if (pcie->soc->program_uphy) {
1006		- err = tegra_pcie_phy_power_off(pcie);
1007		- if (err < 0)
1008		- dev_err(pcie->dev, "failed to power off PHY(s): %d\n",
1009		- err);
1010		- }
1011	1169	}
1012	1170
1013	1171	static void tegra_pcie_power_off(struct tegra_pcie *pcie)
..	..	@@ -1017,13 +1175,11 @@
1017	1175	int err;
1018	1176
1019	1177	reset_control_assert(pcie->afi_rst);
1020		- reset_control_assert(pcie->pex_rst);
1021	1178
1022	1179	clk_disable_unprepare(pcie->pll_e);
1023	1180	if (soc->has_cml_clk)
1024	1181	clk_disable_unprepare(pcie->cml_clk);
1025	1182	clk_disable_unprepare(pcie->afi_clk);
1026		- clk_disable_unprepare(pcie->pex_clk);
1027	1183
1028	1184	if (!dev->pm_domain)
1029	1185	tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
..	..	@@ -1051,46 +1207,66 @@
1051	1207	if (err < 0)
1052	1208	dev_err(dev, "failed to enable regulators: %d\n", err);
1053	1209
1054		- if (dev->pm_domain) {
1055		- err = clk_prepare_enable(pcie->pex_clk);
	1210	+ if (!dev->pm_domain) {
	1211	+ err = tegra_powergate_power_on(TEGRA_POWERGATE_PCIE);
1056	1212	if (err) {
1057		- dev_err(dev, "failed to enable PEX clock: %d\n", err);
1058		- return err;
	1213	+ dev_err(dev, "failed to power ungate: %d\n", err);
	1214	+ goto regulator_disable;
1059	1215	}
1060		- reset_control_deassert(pcie->pex_rst);
1061		- } else {
1062		- err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
1063		- pcie->pex_clk,
1064		- pcie->pex_rst);
	1216	+ err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_PCIE);
1065	1217	if (err) {
1066		- dev_err(dev, "powerup sequence failed: %d\n", err);
1067		- return err;
	1218	+ dev_err(dev, "failed to remove clamp: %d\n", err);
	1219	+ goto powergate;
1068	1220	}
1069	1221	}
1070		-
1071		- reset_control_deassert(pcie->afi_rst);
1072	1222
1073	1223	err = clk_prepare_enable(pcie->afi_clk);
1074	1224	if (err < 0) {
1075	1225	dev_err(dev, "failed to enable AFI clock: %d\n", err);
1076		- return err;
	1226	+ goto powergate;
1077	1227	}
1078	1228
1079	1229	if (soc->has_cml_clk) {
1080	1230	err = clk_prepare_enable(pcie->cml_clk);
1081	1231	if (err < 0) {
1082	1232	dev_err(dev, "failed to enable CML clock: %d\n", err);
1083		- return err;
	1233	+ goto disable_afi_clk;
1084	1234	}
1085	1235	}
1086	1236
1087	1237	err = clk_prepare_enable(pcie->pll_e);
1088	1238	if (err < 0) {
1089	1239	dev_err(dev, "failed to enable PLLE clock: %d\n", err);
1090		- return err;
	1240	+ goto disable_cml_clk;
1091	1241	}
1092	1242
	1243	+ reset_control_deassert(pcie->afi_rst);
	1244	+
1093	1245	return 0;
	1246	+
	1247	+disable_cml_clk:
	1248	+ if (soc->has_cml_clk)
	1249	+ clk_disable_unprepare(pcie->cml_clk);
	1250	+disable_afi_clk:
	1251	+ clk_disable_unprepare(pcie->afi_clk);
	1252	+powergate:
	1253	+ if (!dev->pm_domain)
	1254	+ tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
	1255	+regulator_disable:
	1256	+ regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
	1257	+
	1258	+ return err;
	1259	+}
	1260	+
	1261	+static void tegra_pcie_apply_pad_settings(struct tegra_pcie *pcie)
	1262	+{
	1263	+ const struct tegra_pcie_soc *soc = pcie->soc;
	1264	+
	1265	+ /* Configure the reference clock driver */
	1266	+ pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
	1267	+
	1268	+ if (soc->num_ports > 2)
	1269	+ pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
1094	1270	}
1095	1271
1096	1272	static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
..	..	@@ -1176,7 +1352,7 @@
1176	1352	phy = devm_of_phy_get(dev, np, name);
1177	1353	kfree(name);
1178	1354
1179		- if (IS_ERR(phy) && PTR_ERR(phy) == -ENODEV)
	1355	+ if (PTR_ERR(phy) == -ENODEV)
1180	1356	phy = NULL;
1181	1357
1182	1358	return phy;
..	..	@@ -1261,7 +1437,7 @@
1261	1437	{
1262	1438	struct device *dev = pcie->dev;
1263	1439	struct platform_device *pdev = to_platform_device(dev);
1264		- struct resource pads, afi, *res;
	1440	+ struct resource *res;
1265	1441	const struct tegra_pcie_soc *soc = pcie->soc;
1266	1442	int err;
1267	1443
..	..	@@ -1285,15 +1461,13 @@
1285	1461	}
1286	1462	}
1287	1463
1288		- pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
1289		- pcie->pads = devm_ioremap_resource(dev, pads);
	1464	+ pcie->pads = devm_platform_ioremap_resource_byname(pdev, "pads");
1290	1465	if (IS_ERR(pcie->pads)) {
1291	1466	err = PTR_ERR(pcie->pads);
1292	1467	goto phys_put;
1293	1468	}
1294	1469
1295		- afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
1296		- pcie->afi = devm_ioremap_resource(dev, afi);
	1470	+ pcie->afi = devm_platform_ioremap_resource_byname(pdev, "afi");
1297	1471	if (IS_ERR(pcie->afi)) {
1298	1472	err = PTR_ERR(pcie->afi);
1299	1473	goto phys_put;
..	..	@@ -1319,10 +1493,8 @@
1319	1493
1320	1494	/* request interrupt */
1321	1495	err = platform_get_irq_byname(pdev, "intr");
1322		- if (err < 0) {
1323		- dev_err(dev, "failed to get IRQ: %d\n", err);
	1496	+ if (err < 0)
1324	1497	goto phys_put;
1325		- }
1326	1498
1327	1499	pcie->irq = err;
1328	1500
..	..	@@ -1537,10 +1709,8 @@
1537	1709	}
1538	1710
1539	1711	err = platform_get_irq_byname(pdev, "msi");
1540		- if (err < 0) {
1541		- dev_err(dev, "failed to get IRQ: %d\n", err);
1542		- goto err;
1543		- }
	1712	+ if (err < 0)
	1713	+ goto free_irq_domain;
1544	1714
1545	1715	msi->irq = err;
1546	1716
..	..	@@ -1548,17 +1718,35 @@
1548	1718	tegra_msi_irq_chip.name, pcie);
1549	1719	if (err < 0) {
1550	1720	dev_err(dev, "failed to request IRQ: %d\n", err);
1551		- goto err;
	1721	+ goto free_irq_domain;
1552	1722	}
1553	1723
1554		- /* setup AFI/FPCI range */
1555		- msi->pages = __get_free_pages(GFP_KERNEL, 0);
1556		- msi->phys = virt_to_phys((void *)msi->pages);
	1724	+ /* Though the PCIe controller can address >32-bit address space, to
	1725	+ * facilitate endpoints that support only 32-bit MSI target address,
	1726	+ * the mask is set to 32-bit to make sure that MSI target address is
	1727	+ * always a 32-bit address
	1728	+ */
	1729	+ err = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
	1730	+ if (err < 0) {
	1731	+ dev_err(dev, "failed to set DMA coherent mask: %d\n", err);
	1732	+ goto free_irq;
	1733	+ }
	1734	+
	1735	+ msi->virt = dma_alloc_attrs(dev, PAGE_SIZE, &msi->phys, GFP_KERNEL,
	1736	+ DMA_ATTR_NO_KERNEL_MAPPING);
	1737	+ if (!msi->virt) {
	1738	+ dev_err(dev, "failed to allocate DMA memory for MSI\n");
	1739	+ err = -ENOMEM;
	1740	+ goto free_irq;
	1741	+ }
	1742	+
1557	1743	host->msi = &msi->chip;
1558	1744
1559	1745	return 0;
1560	1746
1561		-err:
	1747	+free_irq:
	1748	+ free_irq(msi->irq, pcie);
	1749	+free_irq_domain:
1562	1750	irq_domain_remove(msi->domain);
1563	1751	return err;
1564	1752	}
..	..	@@ -1595,7 +1783,8 @@
1595	1783	struct tegra_msi *msi = &pcie->msi;
1596	1784	unsigned int i, irq;
1597	1785
1598		- free_pages(msi->pages, 0);
	1786	+ dma_free_attrs(pcie->dev, PAGE_SIZE, msi->virt, msi->phys,
	1787	+ DMA_ATTR_NO_KERNEL_MAPPING);
1599	1788
1600	1789	if (msi->irq > 0)
1601	1790	free_irq(msi->irq, pcie);
..	..	@@ -1629,6 +1818,15 @@
1629	1818	afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1630	1819
1631	1820	return 0;
	1821	+}
	1822	+
	1823	+static void tegra_pcie_disable_interrupts(struct tegra_pcie *pcie)
	1824	+{
	1825	+ u32 value;
	1826	+
	1827	+ value = afi_readl(pcie, AFI_INTR_MASK);
	1828	+ value &= ~AFI_INTR_MASK_INT_MASK;
	1829	+ afi_writel(pcie, value, AFI_INTR_MASK);
1632	1830	}
1633	1831
1634	1832	static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
..	..	@@ -1796,7 +1994,7 @@
1796	1994	pcie->supplies[i++].supply = "hvdd-pex";
1797	1995	pcie->supplies[i++].supply = "vddio-pexctl-aud";
1798	1996	} else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
1799		- pcie->num_supplies = 6;
	1997	+ pcie->num_supplies = 3;
1800	1998
1801	1999	pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1802	2000	sizeof(*pcie->supplies),
..	..	@@ -1804,14 +2002,11 @@
1804	2002	if (!pcie->supplies)
1805	2003	return -ENOMEM;
1806	2004
1807		- pcie->supplies[i++].supply = "avdd-pll-uerefe";
1808	2005	pcie->supplies[i++].supply = "hvddio-pex";
1809	2006	pcie->supplies[i++].supply = "dvddio-pex";
1810		- pcie->supplies[i++].supply = "dvdd-pex-pll";
1811		- pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1812	2007	pcie->supplies[i++].supply = "vddio-pex-ctl";
1813	2008	} else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1814		- pcie->num_supplies = 7;
	2009	+ pcie->num_supplies = 4;
1815	2010
1816	2011	pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1817	2012	sizeof(*pcie->supplies),
..	..	@@ -1821,11 +2016,8 @@
1821	2016
1822	2017	pcie->supplies[i++].supply = "avddio-pex";
1823	2018	pcie->supplies[i++].supply = "dvddio-pex";
1824		- pcie->supplies[i++].supply = "avdd-pex-pll";
1825	2019	pcie->supplies[i++].supply = "hvdd-pex";
1826		- pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1827	2020	pcie->supplies[i++].supply = "vddio-pex-ctl";
1828		- pcie->supplies[i++].supply = "avdd-pll-erefe";
1829	2021	} else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1830	2022	bool need_pexa = false, need_pexb = false;
1831	2023
..	..	@@ -1899,81 +2091,16 @@
1899	2091	struct device *dev = pcie->dev;
1900	2092	struct device_node np = dev->of_node, port;
1901	2093	const struct tegra_pcie_soc *soc = pcie->soc;
1902		- struct of_pci_range_parser parser;
1903		- struct of_pci_range range;
1904	2094	u32 lanes = 0, mask = 0;
1905	2095	unsigned int lane = 0;
1906		- struct resource res;
1907	2096	int err;
1908		-
1909		- if (of_pci_range_parser_init(&parser, np)) {
1910		- dev_err(dev, "missing \"ranges\" property\n");
1911		- return -EINVAL;
1912		- }
1913		-
1914		- for_each_of_pci_range(&parser, &range) {
1915		- err = of_pci_range_to_resource(&range, np, &res);
1916		- if (err < 0)
1917		- return err;
1918		-
1919		- switch (res.flags & IORESOURCE_TYPE_BITS) {
1920		- case IORESOURCE_IO:
1921		- /* Track the bus -> CPU I/O mapping offset. */
1922		- pcie->offset.io = res.start - range.pci_addr;
1923		-
1924		- memcpy(&pcie->pio, &res, sizeof(res));
1925		- pcie->pio.name = np->full_name;
1926		-
1927		- /*
1928		- * The Tegra PCIe host bridge uses this to program the
1929		- * mapping of the I/O space to the physical address,
1930		- * so we override the .start and .end fields here that
1931		- * of_pci_range_to_resource() converted to I/O space.
1932		- * We also set the IORESOURCE_MEM type to clarify that
1933		- * the resource is in the physical memory space.
1934		- */
1935		- pcie->io.start = range.cpu_addr;
1936		- pcie->io.end = range.cpu_addr + range.size - 1;
1937		- pcie->io.flags = IORESOURCE_MEM;
1938		- pcie->io.name = "I/O";
1939		-
1940		- memcpy(&res, &pcie->io, sizeof(res));
1941		- break;
1942		-
1943		- case IORESOURCE_MEM:
1944		- /*
1945		- * Track the bus -> CPU memory mapping offset. This
1946		- * assumes that the prefetchable and non-prefetchable
1947		- * regions will be the last of type IORESOURCE_MEM in
1948		- * the ranges property.
1949		- * */
1950		- pcie->offset.mem = res.start - range.pci_addr;
1951		-
1952		- if (res.flags & IORESOURCE_PREFETCH) {
1953		- memcpy(&pcie->prefetch, &res, sizeof(res));
1954		- pcie->prefetch.name = "prefetchable";
1955		- } else {
1956		- memcpy(&pcie->mem, &res, sizeof(res));
1957		- pcie->mem.name = "non-prefetchable";
1958		- }
1959		- break;
1960		- }
1961		- }
1962		-
1963		- err = of_pci_parse_bus_range(np, &pcie->busn);
1964		- if (err < 0) {
1965		- dev_err(dev, "failed to parse ranges property: %d\n", err);
1966		- pcie->busn.name = np->name;
1967		- pcie->busn.start = 0;
1968		- pcie->busn.end = 0xff;
1969		- pcie->busn.flags = IORESOURCE_BUS;
1970		- }
1971	2097
1972	2098	/* parse root ports */
1973	2099	for_each_child_of_node(np, port) {
1974	2100	struct tegra_pcie_port *rp;
1975	2101	unsigned int index;
1976	2102	u32 value;
	2103	+ char *label;
1977	2104
1978	2105	err = of_pci_get_devfn(port);
1979	2106	if (err < 0) {
..	..	@@ -2033,8 +2160,36 @@
2033	2160	rp->np = port;
2034	2161
2035	2162	rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs);
2036		- if (IS_ERR(rp->base))
2037		- return PTR_ERR(rp->base);
	2163	+ if (IS_ERR(rp->base)) {
	2164	+ err = PTR_ERR(rp->base);
	2165	+ goto err_node_put;
	2166	+ }
	2167	+
	2168	+ label = devm_kasprintf(dev, GFP_KERNEL, "pex-reset-%u", index);
	2169	+ if (!label) {
	2170	+ err = -ENOMEM;
	2171	+ goto err_node_put;
	2172	+ }
	2173	+
	2174	+ /*
	2175	+ * Returns -ENOENT if reset-gpios property is not populated
	2176	+ * and in this case fall back to using AFI per port register
	2177	+ * to toggle PERST# SFIO line.
	2178	+ */
	2179	+ rp->reset_gpio = devm_gpiod_get_from_of_node(dev, port,
	2180	+ "reset-gpios", 0,
	2181	+ GPIOD_OUT_LOW,
	2182	+ label);
	2183	+ if (IS_ERR(rp->reset_gpio)) {
	2184	+ if (PTR_ERR(rp->reset_gpio) == -ENOENT) {
	2185	+ rp->reset_gpio = NULL;
	2186	+ } else {
	2187	+ dev_err(dev, "failed to get reset GPIO: %ld\n",
	2188	+ PTR_ERR(rp->reset_gpio));
	2189	+ err = PTR_ERR(rp->reset_gpio);
	2190	+ goto err_node_put;
	2191	+ }
	2192	+ }
2038	2193
2039	2194	list_add_tail(&rp->list, &pcie->ports);
2040	2195	}
..	..	@@ -2087,7 +2242,7 @@
2087	2242	} while (--timeout);
2088	2243
2089	2244	if (!timeout) {
2090		- dev_err(dev, "link %u down, retrying\n", port->index);
	2245	+ dev_dbg(dev, "link %u down, retrying\n", port->index);
2091	2246	goto retry;
2092	2247	}
2093	2248
..	..	@@ -2109,6 +2264,64 @@
2109	2264	return false;
2110	2265	}
2111	2266
	2267	+static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie)
	2268	+{
	2269	+ struct device *dev = pcie->dev;
	2270	+ struct tegra_pcie_port *port;
	2271	+ ktime_t deadline;
	2272	+ u32 value;
	2273	+
	2274	+ list_for_each_entry(port, &pcie->ports, list) {
	2275	+ /*
	2276	+ * "Supported Link Speeds Vector" in "Link Capabilities 2"
	2277	+ * is not supported by Tegra. tegra_pcie_change_link_speed()
	2278	+ * is called only for Tegra chips which support Gen2.
	2279	+ * So there no harm if supported link speed is not verified.
	2280	+ */
	2281	+ value = readl(port->base + RP_LINK_CONTROL_STATUS_2);
	2282	+ value &= ~PCI_EXP_LNKSTA_CLS;
	2283	+ value \|= PCI_EXP_LNKSTA_CLS_5_0GB;
	2284	+ writel(value, port->base + RP_LINK_CONTROL_STATUS_2);
	2285	+
	2286	+ /*
	2287	+ * Poll until link comes back from recovery to avoid race
	2288	+ * condition.
	2289	+ */
	2290	+ deadline = ktime_add_us(ktime_get(), LINK_RETRAIN_TIMEOUT);
	2291	+
	2292	+ while (ktime_before(ktime_get(), deadline)) {
	2293	+ value = readl(port->base + RP_LINK_CONTROL_STATUS);
	2294	+ if ((value & PCI_EXP_LNKSTA_LT) == 0)
	2295	+ break;
	2296	+
	2297	+ usleep_range(2000, 3000);
	2298	+ }
	2299	+
	2300	+ if (value & PCI_EXP_LNKSTA_LT)
	2301	+ dev_warn(dev, "PCIe port %u link is in recovery\n",
	2302	+ port->index);
	2303	+
	2304	+ /* Retrain the link */
	2305	+ value = readl(port->base + RP_LINK_CONTROL_STATUS);
	2306	+ value \|= PCI_EXP_LNKCTL_RL;
	2307	+ writel(value, port->base + RP_LINK_CONTROL_STATUS);
	2308	+
	2309	+ deadline = ktime_add_us(ktime_get(), LINK_RETRAIN_TIMEOUT);
	2310	+
	2311	+ while (ktime_before(ktime_get(), deadline)) {
	2312	+ value = readl(port->base + RP_LINK_CONTROL_STATUS);
	2313	+ if ((value & PCI_EXP_LNKSTA_LT) == 0)
	2314	+ break;
	2315	+
	2316	+ usleep_range(2000, 3000);
	2317	+ }
	2318	+
	2319	+ if (value & PCI_EXP_LNKSTA_LT)
	2320	+ dev_err(dev, "failed to retrain link of port %u\n",
	2321	+ port->index);
	2322	+ }
	2323	+}
	2324	+
2112	2325	static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
2113	2326	{
2114	2327	struct device *dev = pcie->dev;
..	..	@@ -2119,7 +2332,12 @@
2119	2332	port->index, port->lanes);
2120	2333
2121	2334	tegra_pcie_port_enable(port);
	2335	+ }
2122	2336
	2337	+ /* Start LTSSM from Tegra side */
	2338	+ reset_control_deassert(pcie->pcie_xrst);
	2339	+
	2340	+ list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2123	2341	if (tegra_pcie_port_check_link(port))
2124	2342	continue;
2125	2343
..	..	@@ -2128,11 +2346,16 @@
2128	2346	tegra_pcie_port_disable(port);
2129	2347	tegra_pcie_port_free(port);
2130	2348	}
	2349	+
	2350	+ if (pcie->soc->has_gen2)
	2351	+ tegra_pcie_change_link_speed(pcie);
2131	2352	}
2132	2353
2133	2354	static void tegra_pcie_disable_ports(struct tegra_pcie *pcie)
2134	2355	{
2135	2356	struct tegra_pcie_port port, tmp;
	2357	+
	2358	+ reset_control_assert(pcie->pcie_xrst);
2136	2359
2137	2360	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
2138	2361	tegra_pcie_port_disable(port);
..	..	@@ -2157,6 +2380,11 @@
2157	2380	.has_gen2 = false,
2158	2381	.force_pca_enable = false,
2159	2382	.program_uphy = true,
	2383	+ .update_clamp_threshold = false,
	2384	+ .program_deskew_time = false,
	2385	+ .update_fc_timer = false,
	2386	+ .has_cache_bars = true,
	2387	+ .ectl.enable = false,
2160	2388	};
2161	2389
2162	2390	static const struct tegra_pcie_port_soc tegra30_pcie_ports[] = {
..	..	@@ -2169,6 +2397,7 @@
2169	2397	.num_ports = 3,
2170	2398	.ports = tegra30_pcie_ports,
2171	2399	.msi_base_shift = 8,
	2400	+ .afi_pex2_ctrl = 0x128,
2172	2401	.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2173	2402	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2174	2403	.pads_refclk_cfg0 = 0xfa5cfa5c,
..	..	@@ -2180,6 +2409,11 @@
2180	2409	.has_gen2 = false,
2181	2410	.force_pca_enable = false,
2182	2411	.program_uphy = true,
	2412	+ .update_clamp_threshold = false,
	2413	+ .program_deskew_time = false,
	2414	+ .update_fc_timer = false,
	2415	+ .has_cache_bars = false,
	2416	+ .ectl.enable = false,
2183	2417	};
2184	2418
2185	2419	static const struct tegra_pcie_soc tegra124_pcie = {
..	..	@@ -2196,6 +2430,11 @@
2196	2430	.has_gen2 = true,
2197	2431	.force_pca_enable = false,
2198	2432	.program_uphy = true,
	2433	+ .update_clamp_threshold = true,
	2434	+ .program_deskew_time = false,
	2435	+ .update_fc_timer = false,
	2436	+ .has_cache_bars = false,
	2437	+ .ectl.enable = false,
2199	2438	};
2200	2439
2201	2440	static const struct tegra_pcie_soc tegra210_pcie = {
..	..	@@ -2205,6 +2444,8 @@
2205	2444	.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2206	2445	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2207	2446	.pads_refclk_cfg0 = 0x90b890b8,
	2447	+ /* FC threshold is bit[25:18] */
	2448	+ .update_fc_threshold = 0x01800000,
2208	2449	.has_pex_clkreq_en = true,
2209	2450	.has_pex_bias_ctrl = true,
2210	2451	.has_intr_prsnt_sense = true,
..	..	@@ -2212,6 +2453,23 @@
2212	2453	.has_gen2 = true,
2213	2454	.force_pca_enable = true,
2214	2455	.program_uphy = true,
	2456	+ .update_clamp_threshold = true,
	2457	+ .program_deskew_time = true,
	2458	+ .update_fc_timer = true,
	2459	+ .has_cache_bars = false,
	2460	+ .ectl = {
	2461	+ .regs = {
	2462	+ .rp_ectl_2_r1 = 0x0000000f,
	2463	+ .rp_ectl_4_r1 = 0x00000067,
	2464	+ .rp_ectl_5_r1 = 0x55010000,
	2465	+ .rp_ectl_6_r1 = 0x00000001,
	2466	+ .rp_ectl_2_r2 = 0x0000008f,
	2467	+ .rp_ectl_4_r2 = 0x000000c7,
	2468	+ .rp_ectl_5_r2 = 0x55010000,
	2469	+ .rp_ectl_6_r2 = 0x00000001,
	2470	+ },
	2471	+ .enable = true,
	2472	+ },
2215	2473	};
2216	2474
2217	2475	static const struct tegra_pcie_port_soc tegra186_pcie_ports[] = {
..	..	@@ -2224,6 +2482,7 @@
2224	2482	.num_ports = 3,
2225	2483	.ports = tegra186_pcie_ports,
2226	2484	.msi_base_shift = 8,
	2485	+ .afi_pex2_ctrl = 0x19c,
2227	2486	.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2228	2487	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2229	2488	.pads_refclk_cfg0 = 0x80b880b8,
..	..	@@ -2235,6 +2494,11 @@
2235	2494	.has_gen2 = true,
2236	2495	.force_pca_enable = false,
2237	2496	.program_uphy = false,
	2497	+ .update_clamp_threshold = false,
	2498	+ .program_deskew_time = false,
	2499	+ .update_fc_timer = false,
	2500	+ .has_cache_bars = false,
	2501	+ .ectl.enable = false,
2238	2502	};
2239	2503
2240	2504	static const struct of_device_id tegra_pcie_of_match[] = {
..	..	@@ -2304,36 +2568,14 @@
2304	2568	return 0;
2305	2569	}
2306	2570
2307		-static const struct seq_operations tegra_pcie_ports_seq_ops = {
	2571	+static const struct seq_operations tegra_pcie_ports_sops = {
2308	2572	.start = tegra_pcie_ports_seq_start,
2309	2573	.next = tegra_pcie_ports_seq_next,
2310	2574	.stop = tegra_pcie_ports_seq_stop,
2311	2575	.show = tegra_pcie_ports_seq_show,
2312	2576	};
2313	2577
2314		-static int tegra_pcie_ports_open(struct inode inode, struct file file)
2315		-{
2316		- struct tegra_pcie *pcie = inode->i_private;
2317		- struct seq_file *s;
2318		- int err;
2319		-
2320		- err = seq_open(file, &tegra_pcie_ports_seq_ops);
2321		- if (err)
2322		- return err;
2323		-
2324		- s = file->private_data;
2325		- s->private = pcie;
2326		-
2327		- return 0;
2328		-}
2329		-
2330		-static const struct file_operations tegra_pcie_ports_ops = {
2331		- .owner = THIS_MODULE,
2332		- .open = tegra_pcie_ports_open,
2333		- .read = seq_read,
2334		- .llseek = seq_lseek,
2335		- .release = seq_release,
2336		-};
	2578	+DEFINE_SEQ_ATTRIBUTE(tegra_pcie_ports);
2337	2579
2338	2580	static void tegra_pcie_debugfs_exit(struct tegra_pcie *pcie)
2339	2581	{
..	..	@@ -2341,24 +2583,12 @@
2341	2583	pcie->debugfs = NULL;
2342	2584	}
2343	2585
2344		-static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
	2586	+static void tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
2345	2587	{
2346		- struct dentry *file;
2347		-
2348	2588	pcie->debugfs = debugfs_create_dir("pcie", NULL);
2349		- if (!pcie->debugfs)
2350		- return -ENOMEM;
2351	2589
2352		- file = debugfs_create_file("ports", S_IFREG \| S_IRUGO, pcie->debugfs,
2353		- pcie, &tegra_pcie_ports_ops);
2354		- if (!file)
2355		- goto remove;
2356		-
2357		- return 0;
2358		-
2359		-remove:
2360		- tegra_pcie_debugfs_exit(pcie);
2361		- return -ENOMEM;
	2590	+ debugfs_create_file("ports", S_IFREG \| S_IRUGO, pcie->debugfs, pcie,
	2591	+ &tegra_pcie_ports_fops);
2362	2592	}
2363	2593
2364	2594	static int tegra_pcie_probe(struct platform_device *pdev)
..	..	@@ -2366,7 +2596,6 @@
2366	2596	struct device *dev = &pdev->dev;
2367	2597	struct pci_host_bridge *host;
2368	2598	struct tegra_pcie *pcie;
2369		- struct pci_bus *child;
2370	2599	int err;
2371	2600
2372	2601	host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
..	..	@@ -2404,40 +2633,20 @@
2404	2633	goto pm_runtime_put;
2405	2634	}
2406	2635
2407		- err = tegra_pcie_request_resources(pcie);
2408		- if (err)
2409		- goto pm_runtime_put;
2410		-
2411		- host->busnr = pcie->busn.start;
2412		- host->dev.parent = &pdev->dev;
2413	2636	host->ops = &tegra_pcie_ops;
2414	2637	host->map_irq = tegra_pcie_map_irq;
2415		- host->swizzle_irq = pci_common_swizzle;
2416	2638
2417		- err = pci_scan_root_bus_bridge(host);
	2639	+ err = pci_host_probe(host);
2418	2640	if (err < 0) {
2419	2641	dev_err(dev, "failed to register host: %d\n", err);
2420		- goto free_resources;
	2642	+ goto pm_runtime_put;
2421	2643	}
2422	2644
2423		- pci_bus_size_bridges(host->bus);
2424		- pci_bus_assign_resources(host->bus);
2425		-
2426		- list_for_each_entry(child, &host->bus->children, node)
2427		- pcie_bus_configure_settings(child);
2428		-
2429		- pci_bus_add_devices(host->bus);
2430		-
2431		- if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2432		- err = tegra_pcie_debugfs_init(pcie);
2433		- if (err < 0)
2434		- dev_err(dev, "failed to setup debugfs: %d\n", err);
2435		- }
	2645	+ if (IS_ENABLED(CONFIG_DEBUG_FS))
	2646	+ tegra_pcie_debugfs_init(pcie);
2436	2647
2437	2648	return 0;
2438	2649
2439		-free_resources:
2440		- tegra_pcie_free_resources(pcie);
2441	2650	pm_runtime_put:
2442	2651	pm_runtime_put_sync(pcie->dev);
2443	2652	pm_runtime_disable(pcie->dev);
..	..	@@ -2458,7 +2667,6 @@
2458	2667
2459	2668	pci_stop_root_bus(host->bus);
2460	2669	pci_remove_root_bus(host->bus);
2461		- tegra_pcie_free_resources(pcie);
2462	2670	pm_runtime_put_sync(pcie->dev);
2463	2671	pm_runtime_disable(pcie->dev);
2464	2672
..	..	@@ -2477,16 +2685,32 @@
2477	2685	{
2478	2686	struct tegra_pcie *pcie = dev_get_drvdata(dev);
2479	2687	struct tegra_pcie_port *port;
	2688	+ int err;
2480	2689
2481	2690	list_for_each_entry(port, &pcie->ports, list)
2482	2691	tegra_pcie_pme_turnoff(port);
2483	2692
2484	2693	tegra_pcie_disable_ports(pcie);
2485	2694
	2695	+ /*
	2696	+ * AFI_INTR is unmasked in tegra_pcie_enable_controller(), mask it to
	2697	+ * avoid unwanted interrupts raised by AFI after pex_rst is asserted.
	2698	+ */
	2699	+ tegra_pcie_disable_interrupts(pcie);
	2700	+
	2701	+ if (pcie->soc->program_uphy) {
	2702	+ err = tegra_pcie_phy_power_off(pcie);
	2703	+ if (err < 0)
	2704	+ dev_err(dev, "failed to power off PHY(s): %d\n", err);
	2705	+ }
	2706	+
	2707	+ reset_control_assert(pcie->pex_rst);
	2708	+ clk_disable_unprepare(pcie->pex_clk);
	2709	+
2486	2710	if (IS_ENABLED(CONFIG_PCI_MSI))
2487	2711	tegra_pcie_disable_msi(pcie);
2488	2712
2489		- tegra_pcie_disable_controller(pcie);
	2713	+ pinctrl_pm_select_idle_state(dev);
2490	2714	tegra_pcie_power_off(pcie);
2491	2715
2492	2716	return 0;
..	..	@@ -2502,20 +2726,45 @@
2502	2726	dev_err(dev, "tegra pcie power on fail: %d\n", err);
2503	2727	return err;
2504	2728	}
2505		- err = tegra_pcie_enable_controller(pcie);
2506		- if (err) {
2507		- dev_err(dev, "tegra pcie controller enable fail: %d\n", err);
	2729	+
	2730	+ err = pinctrl_pm_select_default_state(dev);
	2731	+ if (err < 0) {
	2732	+ dev_err(dev, "failed to disable PCIe IO DPD: %d\n", err);
2508	2733	goto poweroff;
2509	2734	}
	2735	+
	2736	+ tegra_pcie_enable_controller(pcie);
2510	2737	tegra_pcie_setup_translations(pcie);
2511	2738
2512	2739	if (IS_ENABLED(CONFIG_PCI_MSI))
2513	2740	tegra_pcie_enable_msi(pcie);
2514	2741
	2742	+ err = clk_prepare_enable(pcie->pex_clk);
	2743	+ if (err) {
	2744	+ dev_err(dev, "failed to enable PEX clock: %d\n", err);
	2745	+ goto pex_dpd_enable;
	2746	+ }
	2747	+
	2748	+ reset_control_deassert(pcie->pex_rst);
	2749	+
	2750	+ if (pcie->soc->program_uphy) {
	2751	+ err = tegra_pcie_phy_power_on(pcie);
	2752	+ if (err < 0) {
	2753	+ dev_err(dev, "failed to power on PHY(s): %d\n", err);
	2754	+ goto disable_pex_clk;
	2755	+ }
	2756	+ }
	2757	+
	2758	+ tegra_pcie_apply_pad_settings(pcie);
2515	2759	tegra_pcie_enable_ports(pcie);
2516	2760
2517	2761	return 0;
2518	2762
	2763	+disable_pex_clk:
	2764	+ reset_control_assert(pcie->pex_rst);
	2765	+ clk_disable_unprepare(pcie->pex_clk);
	2766	+pex_dpd_enable:
	2767	+ pinctrl_pm_select_idle_state(dev);
2519	2768	poweroff:
2520	2769	tegra_pcie_power_off(pcie);
2521	2770