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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/net/ethernet/intel/e1000e/regs.h
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@@ -18,11 +18,15 @@
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 #define E1000_FEXTNVM	0x00028	/* Future Extended NVM - RW */
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 #define E1000_FEXTNVM3	0x0003C	/* Future Extended NVM 3 - RW */
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 #define E1000_FEXTNVM4	0x00024	/* Future Extended NVM 4 - RW */
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+#define E1000_FEXTNVM5	0x00014	/* Future Extended NVM 5 - RW */
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 #define E1000_FEXTNVM6	0x00010	/* Future Extended NVM 6 - RW */
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 #define E1000_FEXTNVM7	0x000E4	/* Future Extended NVM 7 - RW */
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+#define E1000_FEXTNVM8	0x5BB0	/* Future Extended NVM 8 - RW */
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 #define E1000_FEXTNVM9	0x5BB4	/* Future Extended NVM 9 - RW */
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 #define E1000_FEXTNVM11	0x5BBC	/* Future Extended NVM 11 - RW */
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+#define E1000_FEXTNVM12	0x5BC0	/* Future Extended NVM 12 - RW */
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 #define E1000_PCIEANACFG	0x00F18	/* PCIE Analog Config */
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+#define E1000_DPGFR	0x00FAC	/* Dynamic Power Gate Force Control Register */
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 #define E1000_FCT	0x00030	/* Flow Control Type - RW */
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 #define E1000_VET	0x00038	/* VLAN Ether Type - RW */
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 #define E1000_ICR	0x000C0	/* Interrupt Cause Read - R/clr */
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@@ -234,4 +238,7 @@
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 #define E1000_RXMTRL	0x0B634	/* Time sync Rx EtherType and Msg Type - RW */
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 #define E1000_RXUDP	0x0B638	/* Time Sync Rx UDP Port - RW */
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+/* PHY registers */
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+#define I82579_DFT_CTRL	PHY_REG(769, 20)
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+
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 #endif