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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/net/ethernet/freescale/gianfar.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * drivers/net/ethernet/freescale/gianfar.h
34  *
....@@ -10,11 +11,6 @@
1011  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1112  *
1213  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13
- *
14
- * This program is free software; you can redistribute  it and/or modify it
15
- * under  the terms of  the GNU General  Public License as published by the
16
- * Free Software Foundation;  either version 2 of the  License, or (at your
17
- * option) any later version.
1814  *
1915  *  Still left to do:
2016  *      -Add support for module parameters
....@@ -71,10 +67,7 @@
7167 /* Number of bytes to align the rx bufs to */
7268 #define RXBUF_ALIGNMENT 64
7369 
74
-#define PHY_INIT_TIMEOUT 100000
75
-
7670 #define DRV_NAME "gfar-enet"
77
-extern const char gfar_driver_version[];
7871 
7972 /* MAXIMUM NUMBER OF QUEUES SUPPORTED */
8073 #define MAX_TX_QS	0x8
....@@ -92,19 +85,15 @@
9285 #define GFAR_RX_MAX_RING_SIZE   256
9386 #define GFAR_TX_MAX_RING_SIZE   256
9487 
95
-#define GFAR_MAX_FIFO_THRESHOLD 511
96
-#define GFAR_MAX_FIFO_STARVE	511
97
-#define GFAR_MAX_FIFO_STARVE_OFF 511
98
-
9988 #define FBTHR_SHIFT        24
10089 #define DEFAULT_RX_LFC_THR  16
10190 #define DEFAULT_LFC_PTVVAL  4
10291 
103
-/* prevent fragmenation by HW in DSA environments */
104
-#define GFAR_RXB_SIZE roundup(1536 + 8, 64)
105
-#define GFAR_SKBFRAG_SIZE (RXBUF_ALIGNMENT + GFAR_RXB_SIZE \
106
-			  + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
10792 #define GFAR_RXB_TRUESIZE 2048
93
+#define GFAR_SKBFRAG_OVR (RXBUF_ALIGNMENT \
94
+			  + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
95
+#define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
96
+#define GFAR_SKBFRAG_SIZE (GFAR_RXB_SIZE + GFAR_SKBFRAG_OVR)
10897 
10998 #define TX_RING_MOD_MASK(size) (size-1)
11099 #define RX_RING_MOD_MASK(size) (size-1)
....@@ -113,9 +102,6 @@
113102 #define DEFAULT_FIFO_TX_THR 0x100
114103 #define DEFAULT_FIFO_TX_STARVE 0x40
115104 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
116
-#define DEFAULT_BD_STASH 1
117
-#define DEFAULT_STASH_LENGTH	96
118
-#define DEFAULT_STASH_INDEX	0
119105 
120106 /* The number of Exact Match registers */
121107 #define GFAR_EM_NUM	15
....@@ -142,15 +128,6 @@
142128 
143129 #define DEFAULT_RX_COALESCE 0
144130 #define DEFAULT_RXCOUNT	0
145
-
146
-#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
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-		| SUPPORTED_10baseT_Full \
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-		| SUPPORTED_100baseT_Half \
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-		| SUPPORTED_100baseT_Full \
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-		| SUPPORTED_Autoneg \
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-		| SUPPORTED_MII)
152
-
153
-#define GFAR_SUPPORTED_GBIT SUPPORTED_1000baseT_Full
154131 
155132 /* TBI register addresses */
156133 #define MII_TBICON		0x11
....@@ -188,8 +165,6 @@
188165 #define ECNTRL_R100		0x00000008
189166 #define ECNTRL_REDUCED_MII_MODE	0x00000004
190167 #define ECNTRL_SGMII_MODE	0x00000002
191
-
192
-#define MRBLR_INIT_SETTINGS	DEFAULT_RX_BUFFER_SIZE
193168 
194169 #define MINFLR_INIT_SETTINGS	0x00000040
195170 
....@@ -269,12 +244,6 @@
269244 
270245 #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
271246 #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
272
-
273
-#define skip_bd(bdp, stride, base, ring_size) ({ \
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-	typeof(bdp) new_bd = (bdp) + (stride); \
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-	(new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
276
-
277
-#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
278247 
279248 #define RCTRL_TS_ENABLE 	0x01000000
280249 #define RCTRL_PAL_MASK		0x001f0000
....@@ -388,11 +357,6 @@
388357 
389358 #define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT)
390359 #define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT)
391
-
392
-/* Fifo management */
393
-#define FIFO_TX_THR_MASK	0x01ff
394
-#define FIFO_TX_STARVE_MASK	0x01ff
395
-#define FIFO_TX_STARVE_OFF_MASK	0x01ff
396360 
397361 /* Attribute fields */
398362 
....@@ -1330,16 +1294,9 @@
13301294 	return bdp_dma;
13311295 }
13321296 
1333
-irqreturn_t gfar_receive(int irq, void *dev_id);
13341297 int startup_gfar(struct net_device *dev);
13351298 void stop_gfar(struct net_device *dev);
1336
-void reset_gfar(struct net_device *dev);
13371299 void gfar_mac_reset(struct gfar_private *priv);
1338
-void gfar_halt(struct gfar_private *priv);
1339
-void gfar_start(struct gfar_private *priv);
1340
-void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable,
1341
-		   u32 regnum, u32 read);
1342
-void gfar_configure_coalescing_all(struct gfar_private *priv);
13431300 int gfar_set_features(struct net_device *dev, netdev_features_t features);
13441301 
13451302 extern const struct ethtool_ops gfar_ethtool_ops;
....@@ -1351,13 +1308,6 @@
13511308 #define RQFCR_PID_VID_MASK 0xFFFFF000
13521309 #define RQFCR_PID_PORT_MASK 0xFFFF0000
13531310 #define RQFCR_PID_MAC_MASK 0xFF000000
1354
-
1355
-struct gfar_mask_entry {
1356
-	unsigned int mask; /* The mask value which is valid form start to end */
1357
-	unsigned int start;
1358
-	unsigned int end;
1359
-	unsigned int block; /* Same block values indicate depended entries */
1360
-};
13611311 
13621312 /* Represents a receive filer table entry */
13631313 struct gfar_filer_entry {