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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/mtd/nand/raw/atmel/nand-controller.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Copyright 2017 ATMEL
34  * Copyright 2017 Free Electrons
....@@ -28,10 +29,6 @@
2829  *
2930  *   Add Nand Flash Controller support for SAMA5 SoC
3031  *	Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
31
- *
32
- * This program is free software; you can redistribute it and/or modify
33
- * it under the terms of the GNU General Public License version 2 as
34
- * published by the Free Software Foundation.
3532  *
3633  * A few words about the naming convention in this file. This convention
3734  * applies to structure and function names.
....@@ -65,6 +62,7 @@
6562 #include <linux/iopoll.h>
6663 #include <linux/platform_device.h>
6764 #include <linux/regmap.h>
65
+#include <soc/at91/atmel-sfr.h>
6866 
6967 #include "pmecc.h"
7068 
....@@ -202,8 +200,10 @@
202200 	void (*nand_init)(struct atmel_nand_controller *nc,
203201 			  struct atmel_nand *nand);
204202 	int (*ecc_init)(struct nand_chip *chip);
205
-	int (*setup_data_interface)(struct atmel_nand *nand, int csline,
206
-				    const struct nand_data_interface *conf);
203
+	int (*setup_interface)(struct atmel_nand *nand, int csline,
204
+			       const struct nand_interface_config *conf);
205
+	int (*exec_op)(struct atmel_nand *nand,
206
+		       const struct nand_operation *op, bool check_only);
207207 };
208208 
209209 struct atmel_nand_controller_caps {
....@@ -211,6 +211,7 @@
211211 	bool legacy_of_bindings;
212212 	u32 ale_offs;
213213 	u32 cle_offs;
214
+	const char *ebi_csa_regmap_name;
214215 	const struct atmel_nand_controller_ops *ops;
215216 };
216217 
....@@ -231,10 +232,15 @@
231232 	return container_of(ctl, struct atmel_nand_controller, base);
232233 }
233234 
235
+struct atmel_smc_nand_ebi_csa_cfg {
236
+	u32 offs;
237
+	u32 nfd0_on_d16;
238
+};
239
+
234240 struct atmel_smc_nand_controller {
235241 	struct atmel_nand_controller base;
236
-	struct regmap *matrix;
237
-	unsigned int ebi_csa_offs;
242
+	struct regmap *ebi_csa_regmap;
243
+	struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
238244 };
239245 
240246 static inline struct atmel_smc_nand_controller *
....@@ -255,6 +261,7 @@
255261 	struct regmap *io;
256262 	struct atmel_nfc_op op;
257263 	struct completion complete;
264
+	u32 cfg;
258265 	int irq;
259266 
260267 	/* Only used when instantiating from legacy DT bindings. */
....@@ -398,6 +405,7 @@
398405 
399406 	dma_async_issue_pending(nc->dmac);
400407 	wait_for_completion(&finished);
408
+	dma_unmap_single(nc->dev, buf_dma, len, dir);
401409 
402410 	return 0;
403411 
....@@ -408,153 +416,6 @@
408416 	dev_dbg(nc->dev, "Fall back to CPU I/O\n");
409417 
410418 	return -EIO;
411
-}
412
-
413
-static u8 atmel_nand_read_byte(struct mtd_info *mtd)
414
-{
415
-	struct nand_chip *chip = mtd_to_nand(mtd);
416
-	struct atmel_nand *nand = to_atmel_nand(chip);
417
-
418
-	return ioread8(nand->activecs->io.virt);
419
-}
420
-
421
-static u16 atmel_nand_read_word(struct mtd_info *mtd)
422
-{
423
-	struct nand_chip *chip = mtd_to_nand(mtd);
424
-	struct atmel_nand *nand = to_atmel_nand(chip);
425
-
426
-	return ioread16(nand->activecs->io.virt);
427
-}
428
-
429
-static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
430
-{
431
-	struct nand_chip *chip = mtd_to_nand(mtd);
432
-	struct atmel_nand *nand = to_atmel_nand(chip);
433
-
434
-	if (chip->options & NAND_BUSWIDTH_16)
435
-		iowrite16(byte | (byte << 8), nand->activecs->io.virt);
436
-	else
437
-		iowrite8(byte, nand->activecs->io.virt);
438
-}
439
-
440
-static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
441
-{
442
-	struct nand_chip *chip = mtd_to_nand(mtd);
443
-	struct atmel_nand *nand = to_atmel_nand(chip);
444
-	struct atmel_nand_controller *nc;
445
-
446
-	nc = to_nand_controller(chip->controller);
447
-
448
-	/*
449
-	 * If the controller supports DMA, the buffer address is DMA-able and
450
-	 * len is long enough to make DMA transfers profitable, let's trigger
451
-	 * a DMA transfer. If it fails, fallback to PIO mode.
452
-	 */
453
-	if (nc->dmac && virt_addr_valid(buf) &&
454
-	    len >= MIN_DMA_LEN &&
455
-	    !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
456
-				     DMA_FROM_DEVICE))
457
-		return;
458
-
459
-	if (chip->options & NAND_BUSWIDTH_16)
460
-		ioread16_rep(nand->activecs->io.virt, buf, len / 2);
461
-	else
462
-		ioread8_rep(nand->activecs->io.virt, buf, len);
463
-}
464
-
465
-static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
466
-{
467
-	struct nand_chip *chip = mtd_to_nand(mtd);
468
-	struct atmel_nand *nand = to_atmel_nand(chip);
469
-	struct atmel_nand_controller *nc;
470
-
471
-	nc = to_nand_controller(chip->controller);
472
-
473
-	/*
474
-	 * If the controller supports DMA, the buffer address is DMA-able and
475
-	 * len is long enough to make DMA transfers profitable, let's trigger
476
-	 * a DMA transfer. If it fails, fallback to PIO mode.
477
-	 */
478
-	if (nc->dmac && virt_addr_valid(buf) &&
479
-	    len >= MIN_DMA_LEN &&
480
-	    !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
481
-				     len, DMA_TO_DEVICE))
482
-		return;
483
-
484
-	if (chip->options & NAND_BUSWIDTH_16)
485
-		iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
486
-	else
487
-		iowrite8_rep(nand->activecs->io.virt, buf, len);
488
-}
489
-
490
-static int atmel_nand_dev_ready(struct mtd_info *mtd)
491
-{
492
-	struct nand_chip *chip = mtd_to_nand(mtd);
493
-	struct atmel_nand *nand = to_atmel_nand(chip);
494
-
495
-	return gpiod_get_value(nand->activecs->rb.gpio);
496
-}
497
-
498
-static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
499
-{
500
-	struct nand_chip *chip = mtd_to_nand(mtd);
501
-	struct atmel_nand *nand = to_atmel_nand(chip);
502
-
503
-	if (cs < 0 || cs >= nand->numcs) {
504
-		nand->activecs = NULL;
505
-		chip->dev_ready = NULL;
506
-		return;
507
-	}
508
-
509
-	nand->activecs = &nand->cs[cs];
510
-
511
-	if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
512
-		chip->dev_ready = atmel_nand_dev_ready;
513
-}
514
-
515
-static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
516
-{
517
-	struct nand_chip *chip = mtd_to_nand(mtd);
518
-	struct atmel_nand *nand = to_atmel_nand(chip);
519
-	struct atmel_hsmc_nand_controller *nc;
520
-	u32 status;
521
-
522
-	nc = to_hsmc_nand_controller(chip->controller);
523
-
524
-	regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
525
-
526
-	return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
527
-}
528
-
529
-static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
530
-{
531
-	struct nand_chip *chip = mtd_to_nand(mtd);
532
-	struct atmel_nand *nand = to_atmel_nand(chip);
533
-	struct atmel_hsmc_nand_controller *nc;
534
-
535
-	nc = to_hsmc_nand_controller(chip->controller);
536
-
537
-	atmel_nand_select_chip(mtd, cs);
538
-
539
-	if (!nand->activecs) {
540
-		regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
541
-			     ATMEL_HSMC_NFC_CTRL_DIS);
542
-		return;
543
-	}
544
-
545
-	if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
546
-		chip->dev_ready = atmel_hsmc_nand_dev_ready;
547
-
548
-	regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
549
-			   ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
550
-			   ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
551
-			   ATMEL_HSMC_NFC_CFG_RSPARE |
552
-			   ATMEL_HSMC_NFC_CFG_WSPARE,
553
-			   ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
554
-			   ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
555
-			   ATMEL_HSMC_NFC_CFG_RSPARE);
556
-	regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
557
-		     ATMEL_HSMC_NFC_CTRL_EN);
558419 }
559420 
560421 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
....@@ -607,53 +468,250 @@
607468 	return ret;
608469 }
609470 
610
-static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
611
-				     unsigned int ctrl)
471
+static void atmel_nand_data_in(struct atmel_nand *nand, void *buf,
472
+			       unsigned int len, bool force_8bit)
612473 {
613
-	struct nand_chip *chip = mtd_to_nand(mtd);
474
+	struct atmel_nand_controller *nc;
475
+
476
+	nc = to_nand_controller(nand->base.controller);
477
+
478
+	/*
479
+	 * If the controller supports DMA, the buffer address is DMA-able and
480
+	 * len is long enough to make DMA transfers profitable, let's trigger
481
+	 * a DMA transfer. If it fails, fallback to PIO mode.
482
+	 */
483
+	if (nc->dmac && virt_addr_valid(buf) &&
484
+	    len >= MIN_DMA_LEN && !force_8bit &&
485
+	    !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
486
+				     DMA_FROM_DEVICE))
487
+		return;
488
+
489
+	if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
490
+		ioread16_rep(nand->activecs->io.virt, buf, len / 2);
491
+	else
492
+		ioread8_rep(nand->activecs->io.virt, buf, len);
493
+}
494
+
495
+static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf,
496
+				unsigned int len, bool force_8bit)
497
+{
498
+	struct atmel_nand_controller *nc;
499
+
500
+	nc = to_nand_controller(nand->base.controller);
501
+
502
+	/*
503
+	 * If the controller supports DMA, the buffer address is DMA-able and
504
+	 * len is long enough to make DMA transfers profitable, let's trigger
505
+	 * a DMA transfer. If it fails, fallback to PIO mode.
506
+	 */
507
+	if (nc->dmac && virt_addr_valid(buf) &&
508
+	    len >= MIN_DMA_LEN && !force_8bit &&
509
+	    !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
510
+				     len, DMA_TO_DEVICE))
511
+		return;
512
+
513
+	if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
514
+		iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
515
+	else
516
+		iowrite8_rep(nand->activecs->io.virt, buf, len);
517
+}
518
+
519
+static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms)
520
+{
521
+	if (nand->activecs->rb.type == ATMEL_NAND_NO_RB)
522
+		return nand_soft_waitrdy(&nand->base, timeout_ms);
523
+
524
+	return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio,
525
+				 timeout_ms);
526
+}
527
+
528
+static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand,
529
+				   unsigned int timeout_ms)
530
+{
531
+	struct atmel_hsmc_nand_controller *nc;
532
+	u32 status, mask;
533
+
534
+	if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
535
+		return atmel_nand_waitrdy(nand, timeout_ms);
536
+
537
+	nc = to_hsmc_nand_controller(nand->base.controller);
538
+	mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
539
+	return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR,
540
+					       status, status & mask,
541
+					       10, timeout_ms * 1000);
542
+}
543
+
544
+static void atmel_nand_select_target(struct atmel_nand *nand,
545
+				     unsigned int cs)
546
+{
547
+	nand->activecs = &nand->cs[cs];
548
+}
549
+
550
+static void atmel_hsmc_nand_select_target(struct atmel_nand *nand,
551
+					  unsigned int cs)
552
+{
553
+	struct mtd_info *mtd = nand_to_mtd(&nand->base);
554
+	struct atmel_hsmc_nand_controller *nc;
555
+	u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
556
+		  ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
557
+		  ATMEL_HSMC_NFC_CFG_RSPARE;
558
+
559
+	nand->activecs = &nand->cs[cs];
560
+	nc = to_hsmc_nand_controller(nand->base.controller);
561
+	if (nc->cfg == cfg)
562
+		return;
563
+
564
+	regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
565
+			   ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
566
+			   ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
567
+			   ATMEL_HSMC_NFC_CFG_RSPARE |
568
+			   ATMEL_HSMC_NFC_CFG_WSPARE,
569
+			   cfg);
570
+	nc->cfg = cfg;
571
+}
572
+
573
+static int atmel_smc_nand_exec_instr(struct atmel_nand *nand,
574
+				     const struct nand_op_instr *instr)
575
+{
576
+	struct atmel_nand_controller *nc;
577
+	unsigned int i;
578
+
579
+	nc = to_nand_controller(nand->base.controller);
580
+	switch (instr->type) {
581
+	case NAND_OP_CMD_INSTR:
582
+		writeb(instr->ctx.cmd.opcode,
583
+		       nand->activecs->io.virt + nc->caps->cle_offs);
584
+		return 0;
585
+	case NAND_OP_ADDR_INSTR:
586
+		for (i = 0; i < instr->ctx.addr.naddrs; i++)
587
+			writeb(instr->ctx.addr.addrs[i],
588
+			       nand->activecs->io.virt + nc->caps->ale_offs);
589
+		return 0;
590
+	case NAND_OP_DATA_IN_INSTR:
591
+		atmel_nand_data_in(nand, instr->ctx.data.buf.in,
592
+				   instr->ctx.data.len,
593
+				   instr->ctx.data.force_8bit);
594
+		return 0;
595
+	case NAND_OP_DATA_OUT_INSTR:
596
+		atmel_nand_data_out(nand, instr->ctx.data.buf.out,
597
+				    instr->ctx.data.len,
598
+				    instr->ctx.data.force_8bit);
599
+		return 0;
600
+	case NAND_OP_WAITRDY_INSTR:
601
+		return atmel_nand_waitrdy(nand,
602
+					  instr->ctx.waitrdy.timeout_ms);
603
+	default:
604
+		break;
605
+	}
606
+
607
+	return -EINVAL;
608
+}
609
+
610
+static int atmel_smc_nand_exec_op(struct atmel_nand *nand,
611
+				  const struct nand_operation *op,
612
+				  bool check_only)
613
+{
614
+	unsigned int i;
615
+	int ret = 0;
616
+
617
+	if (check_only)
618
+		return 0;
619
+
620
+	atmel_nand_select_target(nand, op->cs);
621
+	gpiod_set_value(nand->activecs->csgpio, 0);
622
+	for (i = 0; i < op->ninstrs; i++) {
623
+		ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]);
624
+		if (ret)
625
+			break;
626
+	}
627
+	gpiod_set_value(nand->activecs->csgpio, 1);
628
+
629
+	return ret;
630
+}
631
+
632
+static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip,
633
+				    const struct nand_subop *subop)
634
+{
614635 	struct atmel_nand *nand = to_atmel_nand(chip);
615636 	struct atmel_hsmc_nand_controller *nc;
637
+	unsigned int i, j;
616638 
617639 	nc = to_hsmc_nand_controller(chip->controller);
618640 
619
-	if (ctrl & NAND_ALE) {
620
-		if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
621
-			return;
641
+	nc->op.cs = nand->activecs->id;
642
+	for (i = 0; i < subop->ninstrs; i++) {
643
+		const struct nand_op_instr *instr = &subop->instrs[i];
622644 
623
-		nc->op.addrs[nc->op.naddrs++] = dat;
624
-	} else if (ctrl & NAND_CLE) {
625
-		if (nc->op.ncmds > 1)
626
-			return;
645
+		if (instr->type == NAND_OP_CMD_INSTR) {
646
+			nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode;
647
+			continue;
648
+		}
627649 
628
-		nc->op.cmds[nc->op.ncmds++] = dat;
650
+		for (j = nand_subop_get_addr_start_off(subop, i);
651
+		     j < nand_subop_get_num_addr_cyc(subop, i); j++) {
652
+			nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j];
653
+			nc->op.naddrs++;
654
+		}
629655 	}
630656 
631
-	if (dat == NAND_CMD_NONE) {
632
-		nc->op.cs = nand->activecs->id;
633
-		atmel_nfc_exec_op(nc, true);
634
-	}
657
+	return atmel_nfc_exec_op(nc, true);
635658 }
636659 
637
-static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
638
-				unsigned int ctrl)
660
+static int atmel_hsmc_exec_rw(struct nand_chip *chip,
661
+			      const struct nand_subop *subop)
639662 {
640
-	struct nand_chip *chip = mtd_to_nand(mtd);
663
+	const struct nand_op_instr *instr = subop->instrs;
641664 	struct atmel_nand *nand = to_atmel_nand(chip);
642
-	struct atmel_nand_controller *nc;
643665 
644
-	nc = to_nand_controller(chip->controller);
666
+	if (instr->type == NAND_OP_DATA_IN_INSTR)
667
+		atmel_nand_data_in(nand, instr->ctx.data.buf.in,
668
+				   instr->ctx.data.len,
669
+				   instr->ctx.data.force_8bit);
670
+	else
671
+		atmel_nand_data_out(nand, instr->ctx.data.buf.out,
672
+				    instr->ctx.data.len,
673
+				    instr->ctx.data.force_8bit);
645674 
646
-	if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
647
-		if (ctrl & NAND_NCE)
648
-			gpiod_set_value(nand->activecs->csgpio, 0);
649
-		else
650
-			gpiod_set_value(nand->activecs->csgpio, 1);
651
-	}
675
+	return 0;
676
+}
652677 
653
-	if (ctrl & NAND_ALE)
654
-		writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
655
-	else if (ctrl & NAND_CLE)
656
-		writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
678
+static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip,
679
+				   const struct nand_subop *subop)
680
+{
681
+	const struct nand_op_instr *instr = subop->instrs;
682
+	struct atmel_nand *nand = to_atmel_nand(chip);
683
+
684
+	return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms);
685
+}
686
+
687
+static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER(
688
+	NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr,
689
+		NAND_OP_PARSER_PAT_CMD_ELEM(true),
690
+		NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
691
+		NAND_OP_PARSER_PAT_CMD_ELEM(true)),
692
+	NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
693
+		NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)),
694
+	NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
695
+		NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)),
696
+	NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy,
697
+		NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
698
+);
699
+
700
+static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand,
701
+				   const struct nand_operation *op,
702
+				   bool check_only)
703
+{
704
+	int ret;
705
+
706
+	if (check_only)
707
+		return nand_op_parser_exec_op(&nand->base,
708
+					      &atmel_hsmc_op_parser, op, true);
709
+
710
+	atmel_hsmc_nand_select_target(nand, op->cs);
711
+	ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op,
712
+				     false);
713
+
714
+	return ret;
657715 }
658716 
659717 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
....@@ -853,7 +911,7 @@
853911 	if (ret)
854912 		return ret;
855913 
856
-	atmel_nand_write_buf(mtd, buf, mtd->writesize);
914
+	nand_write_data_op(chip, buf, mtd->writesize, false);
857915 
858916 	ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
859917 	if (ret) {
....@@ -863,20 +921,18 @@
863921 
864922 	atmel_nand_pmecc_disable(chip, raw);
865923 
866
-	atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
924
+	nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
867925 
868926 	return nand_prog_page_end_op(chip);
869927 }
870928 
871
-static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
872
-				       struct nand_chip *chip, const u8 *buf,
929
+static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
873930 				       int oob_required, int page)
874931 {
875932 	return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
876933 }
877934 
878
-static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
879
-					   struct nand_chip *chip,
935
+static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
880936 					   const u8 *buf, int oob_required,
881937 					   int page)
882938 {
....@@ -895,25 +951,29 @@
895951 	if (ret)
896952 		return ret;
897953 
898
-	atmel_nand_read_buf(mtd, buf, mtd->writesize);
899
-	atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
954
+	ret = nand_read_data_op(chip, buf, mtd->writesize, false, false);
955
+	if (ret)
956
+		goto out_disable;
957
+
958
+	ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false);
959
+	if (ret)
960
+		goto out_disable;
900961 
901962 	ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
902963 
964
+out_disable:
903965 	atmel_nand_pmecc_disable(chip, raw);
904966 
905967 	return ret;
906968 }
907969 
908
-static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
909
-				      struct nand_chip *chip, u8 *buf,
970
+static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
910971 				      int oob_required, int page)
911972 {
912973 	return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
913974 }
914975 
915
-static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
916
-					  struct nand_chip *chip, u8 *buf,
976
+static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
917977 					  int oob_required, int page)
918978 {
919979 	return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
....@@ -926,8 +986,9 @@
926986 	struct mtd_info *mtd = nand_to_mtd(chip);
927987 	struct atmel_nand *nand = to_atmel_nand(chip);
928988 	struct atmel_hsmc_nand_controller *nc;
929
-	int ret, status;
989
+	int ret;
930990 
991
+	atmel_hsmc_nand_select_target(nand, chip->cur_cs);
931992 	nc = to_hsmc_nand_controller(chip->controller);
932993 
933994 	atmel_nfc_copy_to_sram(chip, buf, false);
....@@ -958,25 +1019,12 @@
9581019 	if (ret)
9591020 		return ret;
9601021 
961
-	atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
1022
+	nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
9621023 
963
-	nc->op.cmds[0] = NAND_CMD_PAGEPROG;
964
-	nc->op.ncmds = 1;
965
-	nc->op.cs = nand->activecs->id;
966
-	ret = atmel_nfc_exec_op(nc, false);
967
-	if (ret)
968
-		dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
969
-			ret);
970
-
971
-	status = chip->waitfunc(mtd, chip);
972
-	if (status & NAND_STATUS_FAIL)
973
-		return -EIO;
974
-
975
-	return ret;
1024
+	return nand_prog_page_end_op(chip);
9761025 }
9771026 
978
-static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
979
-					    struct nand_chip *chip,
1027
+static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
9801028 					    const u8 *buf, int oob_required,
9811029 					    int page)
9821030 {
....@@ -984,8 +1032,7 @@
9841032 					      false);
9851033 }
9861034 
987
-static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
988
-						struct nand_chip *chip,
1035
+static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
9891036 						const u8 *buf,
9901037 						int oob_required, int page)
9911038 {
....@@ -1002,6 +1049,7 @@
10021049 	struct atmel_hsmc_nand_controller *nc;
10031050 	int ret;
10041051 
1052
+	atmel_hsmc_nand_select_target(nand, chip->cur_cs);
10051053 	nc = to_hsmc_nand_controller(chip->controller);
10061054 
10071055 	/*
....@@ -1009,12 +1057,9 @@
10091057 	 * connected to a native SoC R/B pin. If that's not the case, fallback
10101058 	 * to the non-optimized one.
10111059 	 */
1012
-	if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
1013
-		nand_read_page_op(chip, page, 0, NULL, 0);
1014
-
1060
+	if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
10151061 		return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
10161062 						raw);
1017
-	}
10181063 
10191064 	nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
10201065 
....@@ -1047,16 +1092,14 @@
10471092 	return ret;
10481093 }
10491094 
1050
-static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1051
-					   struct nand_chip *chip, u8 *buf,
1095
+static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
10521096 					   int oob_required, int page)
10531097 {
10541098 	return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
10551099 					     false);
10561100 }
10571101 
1058
-static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1059
-					       struct nand_chip *chip,
1102
+static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
10601103 					       u8 *buf, int oob_required,
10611104 					       int page)
10621105 {
....@@ -1066,7 +1109,10 @@
10661109 
10671110 static int atmel_nand_pmecc_init(struct nand_chip *chip)
10681111 {
1112
+	const struct nand_ecc_props *requirements =
1113
+		nanddev_get_ecc_requirements(&chip->base);
10691114 	struct mtd_info *mtd = nand_to_mtd(chip);
1115
+	struct nand_device *nanddev = mtd_to_nanddev(mtd);
10701116 	struct atmel_nand *nand = to_atmel_nand(chip);
10711117 	struct atmel_nand_controller *nc;
10721118 	struct atmel_pmecc_user_req req;
....@@ -1091,19 +1137,19 @@
10911137 			chip->ecc.size = val;
10921138 	}
10931139 
1094
-	if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1140
+	if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
10951141 		req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
10961142 	else if (chip->ecc.strength)
10971143 		req.ecc.strength = chip->ecc.strength;
1098
-	else if (chip->ecc_strength_ds)
1099
-		req.ecc.strength = chip->ecc_strength_ds;
1144
+	else if (requirements->strength)
1145
+		req.ecc.strength = requirements->strength;
11001146 	else
11011147 		req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
11021148 
11031149 	if (chip->ecc.size)
11041150 		req.ecc.sectorsize = chip->ecc.size;
1105
-	else if (chip->ecc_step_ds)
1106
-		req.ecc.sectorsize = chip->ecc_step_ds;
1151
+	else if (requirements->step_size)
1152
+		req.ecc.sectorsize = requirements->step_size;
11071153 	else
11081154 		req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
11091155 
....@@ -1122,14 +1168,14 @@
11221168 	if (IS_ERR(nand->pmecc))
11231169 		return PTR_ERR(nand->pmecc);
11241170 
1125
-	chip->ecc.algo = NAND_ECC_BCH;
1171
+	chip->ecc.algo = NAND_ECC_ALGO_BCH;
11261172 	chip->ecc.size = req.ecc.sectorsize;
11271173 	chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
11281174 	chip->ecc.strength = req.ecc.strength;
11291175 
11301176 	chip->options |= NAND_NO_SUBPAGE_WRITE;
11311177 
1132
-	mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1178
+	mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
11331179 
11341180 	return 0;
11351181 }
....@@ -1141,15 +1187,15 @@
11411187 
11421188 	nc = to_nand_controller(chip->controller);
11431189 
1144
-	switch (chip->ecc.mode) {
1145
-	case NAND_ECC_NONE:
1146
-	case NAND_ECC_SOFT:
1190
+	switch (chip->ecc.engine_type) {
1191
+	case NAND_ECC_ENGINE_TYPE_NONE:
1192
+	case NAND_ECC_ENGINE_TYPE_SOFT:
11471193 		/*
11481194 		 * Nothing to do, the core will initialize everything for us.
11491195 		 */
11501196 		break;
11511197 
1152
-	case NAND_ECC_HW:
1198
+	case NAND_ECC_ENGINE_TYPE_ON_HOST:
11531199 		ret = atmel_nand_pmecc_init(chip);
11541200 		if (ret)
11551201 			return ret;
....@@ -1163,7 +1209,7 @@
11631209 	default:
11641210 		/* Other modes are not supported. */
11651211 		dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1166
-			chip->ecc.mode);
1212
+			chip->ecc.engine_type);
11671213 		return -ENOTSUPP;
11681214 	}
11691215 
....@@ -1178,7 +1224,7 @@
11781224 	if (ret)
11791225 		return ret;
11801226 
1181
-	if (chip->ecc.mode != NAND_ECC_HW)
1227
+	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
11821228 		return 0;
11831229 
11841230 	/* Adjust the ECC operations for the HSMC IP. */
....@@ -1191,7 +1237,7 @@
11911237 }
11921238 
11931239 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1194
-					const struct nand_data_interface *conf,
1240
+					const struct nand_interface_config *conf,
11951241 					struct atmel_smc_cs_conf *smcconf)
11961242 {
11971243 	u32 ncycles, totalcycles, timeps, mckperiodps;
....@@ -1201,7 +1247,7 @@
12011247 	nc = to_nand_controller(nand->base.controller);
12021248 
12031249 	/* DDR interface not supported. */
1204
-	if (conf->type != NAND_SDR_IFACE)
1250
+	if (!nand_interface_is_sdr(conf))
12051251 		return -ENOTSUPP;
12061252 
12071253 	/*
....@@ -1420,9 +1466,9 @@
14201466 	return 0;
14211467 }
14221468 
1423
-static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1469
+static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,
14241470 					int csline,
1425
-					const struct nand_data_interface *conf)
1471
+					const struct nand_interface_config *conf)
14261472 {
14271473 	struct atmel_nand_controller *nc;
14281474 	struct atmel_smc_cs_conf smcconf;
....@@ -1445,9 +1491,9 @@
14451491 	return 0;
14461492 }
14471493 
1448
-static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1494
+static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,
14491495 					int csline,
1450
-					const struct nand_data_interface *conf)
1496
+					const struct nand_interface_config *conf)
14511497 {
14521498 	struct atmel_hsmc_nand_controller *nc;
14531499 	struct atmel_smc_cs_conf smcconf;
....@@ -1475,10 +1521,9 @@
14751521 	return 0;
14761522 }
14771523 
1478
-static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1479
-					const struct nand_data_interface *conf)
1524
+static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
1525
+				      const struct nand_interface_config *conf)
14801526 {
1481
-	struct nand_chip *chip = mtd_to_nand(mtd);
14821527 	struct atmel_nand *nand = to_atmel_nand(chip);
14831528 	struct atmel_nand_controller *nc;
14841529 
....@@ -1488,7 +1533,19 @@
14881533 	    (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
14891534 		return -EINVAL;
14901535 
1491
-	return nc->caps->ops->setup_data_interface(nand, csline, conf);
1536
+	return nc->caps->ops->setup_interface(nand, csline, conf);
1537
+}
1538
+
1539
+static int atmel_nand_exec_op(struct nand_chip *chip,
1540
+			      const struct nand_operation *op,
1541
+			      bool check_only)
1542
+{
1543
+	struct atmel_nand *nand = to_atmel_nand(chip);
1544
+	struct atmel_nand_controller *nc;
1545
+
1546
+	nc = to_nand_controller(nand->base.controller);
1547
+
1548
+	return nc->caps->ops->exec_op(nand, op, check_only);
14921549 }
14931550 
14941551 static void atmel_nand_init(struct atmel_nand_controller *nc,
....@@ -1500,30 +1557,19 @@
15001557 	mtd->dev.parent = nc->dev;
15011558 	nand->base.controller = &nc->base;
15021559 
1503
-	chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1504
-	chip->read_byte = atmel_nand_read_byte;
1505
-	chip->read_word = atmel_nand_read_word;
1506
-	chip->write_byte = atmel_nand_write_byte;
1507
-	chip->read_buf = atmel_nand_read_buf;
1508
-	chip->write_buf = atmel_nand_write_buf;
1509
-	chip->select_chip = atmel_nand_select_chip;
1510
-
1511
-	if (nc->mck && nc->caps->ops->setup_data_interface)
1512
-		chip->setup_data_interface = atmel_nand_setup_data_interface;
1513
-
1514
-	/* Some NANDs require a longer delay than the default one (20us). */
1515
-	chip->chip_delay = 40;
1560
+	if (!nc->mck || !nc->caps->ops->setup_interface)
1561
+		chip->options |= NAND_KEEP_TIMINGS;
15161562 
15171563 	/*
15181564 	 * Use a bounce buffer when the buffer passed by the MTD user is not
15191565 	 * suitable for DMA.
15201566 	 */
15211567 	if (nc->dmac)
1522
-		chip->options |= NAND_USE_BOUNCE_BUFFER;
1568
+		chip->options |= NAND_USES_DMA;
15231569 
15241570 	/* Default to HW ECC if pmecc is available. */
15251571 	if (nc->pmecc)
1526
-		chip->ecc.mode = NAND_ECC_HW;
1572
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
15271573 }
15281574 
15291575 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
....@@ -1536,25 +1582,20 @@
15361582 	atmel_nand_init(nc, nand);
15371583 
15381584 	smc_nc = to_smc_nand_controller(chip->controller);
1539
-	if (!smc_nc->matrix)
1585
+	if (!smc_nc->ebi_csa_regmap)
15401586 		return;
15411587 
15421588 	/* Attach the CS to the NAND Flash logic. */
15431589 	for (i = 0; i < nand->numcs; i++)
1544
-		regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1590
+		regmap_update_bits(smc_nc->ebi_csa_regmap,
1591
+				   smc_nc->ebi_csa->offs,
15451592 				   BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1546
-}
15471593 
1548
-static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1549
-				 struct atmel_nand *nand)
1550
-{
1551
-	struct nand_chip *chip = &nand->base;
1552
-
1553
-	atmel_nand_init(nc, nand);
1554
-
1555
-	/* Overload some methods for the HSMC controller. */
1556
-	chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1557
-	chip->select_chip = atmel_hsmc_nand_select_chip;
1594
+	if (smc_nc->ebi_csa->nfd0_on_d16)
1595
+		regmap_update_bits(smc_nc->ebi_csa_regmap,
1596
+				   smc_nc->ebi_csa->offs,
1597
+				   smc_nc->ebi_csa->nfd0_on_d16,
1598
+				   smc_nc->ebi_csa->nfd0_on_d16);
15581599 }
15591600 
15601601 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
....@@ -1588,9 +1629,7 @@
15881629 		return ERR_PTR(-EINVAL);
15891630 	}
15901631 
1591
-	nand = devm_kzalloc(nc->dev,
1592
-			    sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1593
-			    GFP_KERNEL);
1632
+	nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
15941633 	if (!nand) {
15951634 		dev_err(nc->dev, "Failed to allocate NAND object\n");
15961635 		return ERR_PTR(-ENOMEM);
....@@ -1598,9 +1637,8 @@
15981637 
15991638 	nand->numcs = numcs;
16001639 
1601
-	gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1602
-						      &np->fwnode, GPIOD_IN,
1603
-						      "nand-det");
1640
+	gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np),
1641
+				     "det", GPIOD_IN, "nand-det");
16041642 	if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
16051643 		dev_err(nc->dev,
16061644 			"Failed to get detect gpio (err = %ld)\n",
....@@ -1644,9 +1682,10 @@
16441682 			nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
16451683 			nand->cs[i].rb.id = val;
16461684 		} else {
1647
-			gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1648
-							"rb", i, &np->fwnode,
1649
-							GPIOD_IN, "nand-rb");
1685
+			gpio = devm_fwnode_gpiod_get_index(nc->dev,
1686
+							   of_fwnode_handle(np),
1687
+							   "rb", i, GPIOD_IN,
1688
+							   "nand-rb");
16501689 			if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
16511690 				dev_err(nc->dev,
16521691 					"Failed to get R/B gpio (err = %ld)\n",
....@@ -1660,10 +1699,10 @@
16601699 			}
16611700 		}
16621701 
1663
-		gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1664
-							      i, &np->fwnode,
1665
-							      GPIOD_OUT_HIGH,
1666
-							      "nand-cs");
1702
+		gpio = devm_fwnode_gpiod_get_index(nc->dev,
1703
+						   of_fwnode_handle(np),
1704
+						   "cs", i, GPIOD_OUT_HIGH,
1705
+						   "nand-cs");
16671706 		if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
16681707 			dev_err(nc->dev,
16691708 				"Failed to get CS gpio (err = %ld)\n",
....@@ -1864,34 +1903,71 @@
18641903 	clk_put(nc->mck);
18651904 }
18661905 
1867
-static const struct of_device_id atmel_matrix_of_ids[] = {
1906
+static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1907
+	.offs = AT91SAM9260_MATRIX_EBICSA,
1908
+};
1909
+
1910
+static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1911
+	.offs = AT91SAM9261_MATRIX_EBICSA,
1912
+};
1913
+
1914
+static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1915
+	.offs = AT91SAM9263_MATRIX_EBI0CSA,
1916
+};
1917
+
1918
+static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1919
+	.offs = AT91SAM9RL_MATRIX_EBICSA,
1920
+};
1921
+
1922
+static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1923
+	.offs = AT91SAM9G45_MATRIX_EBICSA,
1924
+};
1925
+
1926
+static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1927
+	.offs = AT91SAM9N12_MATRIX_EBICSA,
1928
+};
1929
+
1930
+static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1931
+	.offs = AT91SAM9X5_MATRIX_EBICSA,
1932
+};
1933
+
1934
+static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1935
+	.offs = AT91_SFR_CCFG_EBICSA,
1936
+	.nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1937
+};
1938
+
1939
+static const struct of_device_id atmel_ebi_csa_regmap_of_ids[] = {
18681940 	{
18691941 		.compatible = "atmel,at91sam9260-matrix",
1870
-		.data = (void *)AT91SAM9260_MATRIX_EBICSA,
1942
+		.data = &at91sam9260_ebi_csa,
18711943 	},
18721944 	{
18731945 		.compatible = "atmel,at91sam9261-matrix",
1874
-		.data = (void *)AT91SAM9261_MATRIX_EBICSA,
1946
+		.data = &at91sam9261_ebi_csa,
18751947 	},
18761948 	{
18771949 		.compatible = "atmel,at91sam9263-matrix",
1878
-		.data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1950
+		.data = &at91sam9263_ebi_csa,
18791951 	},
18801952 	{
18811953 		.compatible = "atmel,at91sam9rl-matrix",
1882
-		.data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1954
+		.data = &at91sam9rl_ebi_csa,
18831955 	},
18841956 	{
18851957 		.compatible = "atmel,at91sam9g45-matrix",
1886
-		.data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1958
+		.data = &at91sam9g45_ebi_csa,
18871959 	},
18881960 	{
18891961 		.compatible = "atmel,at91sam9n12-matrix",
1890
-		.data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1962
+		.data = &at91sam9n12_ebi_csa,
18911963 	},
18921964 	{
18931965 		.compatible = "atmel,at91sam9x5-matrix",
1894
-		.data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1966
+		.data = &at91sam9x5_ebi_csa,
1967
+	},
1968
+	{
1969
+		.compatible = "microchip,sam9x60-sfr",
1970
+		.data = &sam9x60_ebi_csa,
18951971 	},
18961972 	{ /* sentinel */ },
18971973 };
....@@ -1939,6 +2015,8 @@
19392015 
19402016 static const struct nand_controller_ops atmel_nand_controller_ops = {
19412017 	.attach_chip = atmel_nand_attach_chip,
2018
+	.setup_interface = atmel_nand_setup_interface,
2019
+	.exec_op = atmel_nand_exec_op,
19422020 };
19432021 
19442022 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
....@@ -1958,13 +2036,9 @@
19582036 	platform_set_drvdata(pdev, nc);
19592037 
19602038 	nc->pmecc = devm_atmel_pmecc_get(dev);
1961
-	if (IS_ERR(nc->pmecc)) {
1962
-		ret = PTR_ERR(nc->pmecc);
1963
-		if (ret != -EPROBE_DEFER)
1964
-			dev_err(dev, "Could not get PMECC object (err = %d)\n",
1965
-				ret);
1966
-		return ret;
1967
-	}
2039
+	if (IS_ERR(nc->pmecc))
2040
+		return dev_err_probe(dev, PTR_ERR(nc->pmecc),
2041
+				     "Could not get PMECC object\n");
19682042 
19692043 	if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
19702044 		dma_cap_mask_t mask;
....@@ -1984,13 +2058,15 @@
19842058 	nc->mck = of_clk_get(dev->parent->of_node, 0);
19852059 	if (IS_ERR(nc->mck)) {
19862060 		dev_err(dev, "Failed to retrieve MCK clk\n");
1987
-		return PTR_ERR(nc->mck);
2061
+		ret = PTR_ERR(nc->mck);
2062
+		goto out_release_dma;
19882063 	}
19892064 
19902065 	np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
19912066 	if (!np) {
19922067 		dev_err(dev, "Missing or invalid atmel,smc property\n");
1993
-		return -EINVAL;
2068
+		ret = -EINVAL;
2069
+		goto out_release_dma;
19942070 	}
19952071 
19962072 	nc->smc = syscon_node_to_regmap(np);
....@@ -1998,10 +2074,16 @@
19982074 	if (IS_ERR(nc->smc)) {
19992075 		ret = PTR_ERR(nc->smc);
20002076 		dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2001
-		return ret;
2077
+		goto out_release_dma;
20022078 	}
20032079 
20042080 	return 0;
2081
+
2082
+out_release_dma:
2083
+	if (nc->dmac)
2084
+		dma_release_channel(nc->dmac);
2085
+
2086
+	return ret;
20052087 }
20062088 
20072089 static int
....@@ -2012,37 +2094,38 @@
20122094 	struct device_node *np;
20132095 	int ret;
20142096 
2015
-	/* We do not retrieve the matrix syscon when parsing old DTs. */
2097
+	/* We do not retrieve the EBICSA regmap when parsing old DTs. */
20162098 	if (nc->base.caps->legacy_of_bindings)
20172099 		return 0;
20182100 
2019
-	np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
2101
+	np = of_parse_phandle(dev->parent->of_node,
2102
+			      nc->base.caps->ebi_csa_regmap_name, 0);
20202103 	if (!np)
20212104 		return 0;
20222105 
2023
-	match = of_match_node(atmel_matrix_of_ids, np);
2106
+	match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);
20242107 	if (!match) {
20252108 		of_node_put(np);
20262109 		return 0;
20272110 	}
20282111 
2029
-	nc->matrix = syscon_node_to_regmap(np);
2112
+	nc->ebi_csa_regmap = syscon_node_to_regmap(np);
20302113 	of_node_put(np);
2031
-	if (IS_ERR(nc->matrix)) {
2032
-		ret = PTR_ERR(nc->matrix);
2033
-		dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2114
+	if (IS_ERR(nc->ebi_csa_regmap)) {
2115
+		ret = PTR_ERR(nc->ebi_csa_regmap);
2116
+		dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
20342117 		return ret;
20352118 	}
20362119 
2037
-	nc->ebi_csa_offs = (uintptr_t)match->data;
2120
+	nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
20382121 
20392122 	/*
20402123 	 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2041
-	 * add 4 to ->ebi_csa_offs.
2124
+	 * add 4 to ->ebi_csa->offs.
20422125 	 */
20432126 	if (of_device_is_compatible(dev->parent->of_node,
20442127 				    "atmel,at91sam9263-ebi1"))
2045
-		nc->ebi_csa_offs += 4;
2128
+		nc->ebi_csa->offs += 4;
20462129 
20472130 	return 0;
20482131 }
....@@ -2229,6 +2312,9 @@
22292312 		return ret;
22302313 
22312314 	hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2315
+	regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2316
+		     ATMEL_HSMC_NFC_CTRL_DIS);
2317
+
22322318 	if (hsmc_nc->sram.pool)
22332319 		gen_pool_free(hsmc_nc->sram.pool,
22342320 			      (unsigned long)hsmc_nc->sram.virt,
....@@ -2281,6 +2367,8 @@
22812367 	/* Initial NFC configuration. */
22822368 	regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
22832369 		     ATMEL_HSMC_NFC_CFG_DTO_MAX);
2370
+	regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2371
+		     ATMEL_HSMC_NFC_CTRL_EN);
22842372 
22852373 	ret = atmel_nand_controller_add_nands(&nc->base);
22862374 	if (ret)
....@@ -2298,8 +2386,9 @@
22982386 	.probe = atmel_hsmc_nand_controller_probe,
22992387 	.remove = atmel_hsmc_nand_controller_remove,
23002388 	.ecc_init = atmel_hsmc_nand_ecc_init,
2301
-	.nand_init = atmel_hsmc_nand_init,
2302
-	.setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2389
+	.nand_init = atmel_nand_init,
2390
+	.setup_interface = atmel_hsmc_nand_setup_interface,
2391
+	.exec_op = atmel_hsmc_nand_exec_op,
23032392 };
23042393 
23052394 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
....@@ -2356,21 +2445,23 @@
23562445 
23572446 /*
23582447  * The SMC reg layout of at91rm9200 is completely different which prevents us
2359
- * from re-using atmel_smc_nand_setup_data_interface() for the
2360
- * ->setup_data_interface() hook.
2448
+ * from re-using atmel_smc_nand_setup_interface() for the
2449
+ * ->setup_interface() hook.
23612450  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2362
- * ->setup_data_interface() unassigned.
2451
+ * ->setup_interface() unassigned.
23632452  */
23642453 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
23652454 	.probe = atmel_smc_nand_controller_probe,
23662455 	.remove = atmel_smc_nand_controller_remove,
23672456 	.ecc_init = atmel_nand_ecc_init,
23682457 	.nand_init = atmel_smc_nand_init,
2458
+	.exec_op = atmel_smc_nand_exec_op,
23692459 };
23702460 
23712461 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
23722462 	.ale_offs = BIT(21),
23732463 	.cle_offs = BIT(22),
2464
+	.ebi_csa_regmap_name = "atmel,matrix",
23742465 	.ops = &at91rm9200_nc_ops,
23752466 };
23762467 
....@@ -2379,18 +2470,21 @@
23792470 	.remove = atmel_smc_nand_controller_remove,
23802471 	.ecc_init = atmel_nand_ecc_init,
23812472 	.nand_init = atmel_smc_nand_init,
2382
-	.setup_data_interface = atmel_smc_nand_setup_data_interface,
2473
+	.setup_interface = atmel_smc_nand_setup_interface,
2474
+	.exec_op = atmel_smc_nand_exec_op,
23832475 };
23842476 
23852477 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
23862478 	.ale_offs = BIT(21),
23872479 	.cle_offs = BIT(22),
2480
+	.ebi_csa_regmap_name = "atmel,matrix",
23882481 	.ops = &atmel_smc_nc_ops,
23892482 };
23902483 
23912484 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
23922485 	.ale_offs = BIT(22),
23932486 	.cle_offs = BIT(21),
2487
+	.ebi_csa_regmap_name = "atmel,matrix",
23942488 	.ops = &atmel_smc_nc_ops,
23952489 };
23962490 
....@@ -2398,6 +2492,15 @@
23982492 	.has_dma = true,
23992493 	.ale_offs = BIT(21),
24002494 	.cle_offs = BIT(22),
2495
+	.ebi_csa_regmap_name = "atmel,matrix",
2496
+	.ops = &atmel_smc_nc_ops,
2497
+};
2498
+
2499
+static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2500
+	.has_dma = true,
2501
+	.ale_offs = BIT(21),
2502
+	.cle_offs = BIT(22),
2503
+	.ebi_csa_regmap_name = "microchip,sfr",
24012504 	.ops = &atmel_smc_nc_ops,
24022505 };
24032506 
....@@ -2445,6 +2548,10 @@
24452548 		.compatible = "atmel,sama5d3-nand-controller",
24462549 		.data = &atmel_sama5_nc_caps,
24472550 	},
2551
+	{
2552
+		.compatible = "microchip,sam9x60-nand-controller",
2553
+		.data = &microchip_sam9x60_nc_caps,
2554
+	},
24482555 	/* Support for old/deprecated bindings: */
24492556 	{
24502557 		.compatible = "atmel,at91rm9200-nand",