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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/media/platform/ti-vpe/vpe_regs.h
....@@ -1,13 +1,10 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (c) 2013 Texas Instruments Inc.
34  *
45  * David Griego, <dagriego@biglakesoftware.com>
56  * Dale Farnsworth, <dale@farnsworth.org>
67  * Archit Taneja, <archit@ti.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify it
9
- * under the terms of the GNU General Public License version 2 as published by
10
- * the Free Software Foundation.
118  */
129 
1310 #ifndef __TI_VPE_REGS_H
....@@ -51,24 +48,24 @@
5148 #define VPE_INT0_ENABLE0_SET		0x0030
5249 #define VPE_INT0_ENABLE0		VPE_INT0_ENABLE0_SET
5350 #define VPE_INT0_ENABLE0_CLR		0x0038
54
-#define VPE_INT0_LIST0_COMPLETE		(1 << 0)
55
-#define VPE_INT0_LIST0_NOTIFY		(1 << 1)
56
-#define VPE_INT0_LIST1_COMPLETE		(1 << 2)
57
-#define VPE_INT0_LIST1_NOTIFY		(1 << 3)
58
-#define VPE_INT0_LIST2_COMPLETE		(1 << 4)
59
-#define VPE_INT0_LIST2_NOTIFY		(1 << 5)
60
-#define VPE_INT0_LIST3_COMPLETE		(1 << 6)
61
-#define VPE_INT0_LIST3_NOTIFY		(1 << 7)
62
-#define VPE_INT0_LIST4_COMPLETE		(1 << 8)
63
-#define VPE_INT0_LIST4_NOTIFY		(1 << 9)
64
-#define VPE_INT0_LIST5_COMPLETE		(1 << 10)
65
-#define VPE_INT0_LIST5_NOTIFY		(1 << 11)
66
-#define VPE_INT0_LIST6_COMPLETE		(1 << 12)
67
-#define VPE_INT0_LIST6_NOTIFY		(1 << 13)
68
-#define VPE_INT0_LIST7_COMPLETE		(1 << 14)
69
-#define VPE_INT0_LIST7_NOTIFY		(1 << 15)
70
-#define VPE_INT0_DESCRIPTOR		(1 << 16)
71
-#define VPE_DEI_FMD_INT			(1 << 18)
51
+#define VPE_INT0_LIST0_COMPLETE		BIT(0)
52
+#define VPE_INT0_LIST0_NOTIFY		BIT(1)
53
+#define VPE_INT0_LIST1_COMPLETE		BIT(2)
54
+#define VPE_INT0_LIST1_NOTIFY		BIT(3)
55
+#define VPE_INT0_LIST2_COMPLETE		BIT(4)
56
+#define VPE_INT0_LIST2_NOTIFY		BIT(5)
57
+#define VPE_INT0_LIST3_COMPLETE		BIT(6)
58
+#define VPE_INT0_LIST3_NOTIFY		BIT(7)
59
+#define VPE_INT0_LIST4_COMPLETE		BIT(8)
60
+#define VPE_INT0_LIST4_NOTIFY		BIT(9)
61
+#define VPE_INT0_LIST5_COMPLETE		BIT(10)
62
+#define VPE_INT0_LIST5_NOTIFY		BIT(11)
63
+#define VPE_INT0_LIST6_COMPLETE		BIT(12)
64
+#define VPE_INT0_LIST6_NOTIFY		BIT(13)
65
+#define VPE_INT0_LIST7_COMPLETE		BIT(14)
66
+#define VPE_INT0_LIST7_NOTIFY		BIT(15)
67
+#define VPE_INT0_DESCRIPTOR		BIT(16)
68
+#define VPE_DEI_FMD_INT			BIT(18)
7269 
7370 #define VPE_INT0_STATUS1_RAW_SET	0x0024
7471 #define VPE_INT0_STATUS1_RAW		VPE_INT0_STATUS1_RAW_SET
....@@ -77,21 +74,21 @@
7774 #define VPE_INT0_ENABLE1_SET		0x0034
7875 #define VPE_INT0_ENABLE1		VPE_INT0_ENABLE1_SET
7976 #define VPE_INT0_ENABLE1_CLR		0x003c
80
-#define VPE_INT0_CHANNEL_GROUP0		(1 << 0)
81
-#define VPE_INT0_CHANNEL_GROUP1		(1 << 1)
82
-#define VPE_INT0_CHANNEL_GROUP2		(1 << 2)
83
-#define VPE_INT0_CHANNEL_GROUP3		(1 << 3)
84
-#define VPE_INT0_CHANNEL_GROUP4		(1 << 4)
85
-#define VPE_INT0_CHANNEL_GROUP5		(1 << 5)
86
-#define VPE_INT0_CLIENT			(1 << 7)
87
-#define VPE_DEI_ERROR_INT		(1 << 16)
88
-#define VPE_DS1_UV_ERROR_INT		(1 << 22)
77
+#define VPE_INT0_CHANNEL_GROUP0		BIT(0)
78
+#define VPE_INT0_CHANNEL_GROUP1		BIT(1)
79
+#define VPE_INT0_CHANNEL_GROUP2		BIT(2)
80
+#define VPE_INT0_CHANNEL_GROUP3		BIT(3)
81
+#define VPE_INT0_CHANNEL_GROUP4		BIT(4)
82
+#define VPE_INT0_CHANNEL_GROUP5		BIT(5)
83
+#define VPE_INT0_CLIENT			BIT(7)
84
+#define VPE_DEI_ERROR_INT		BIT(16)
85
+#define VPE_DS1_UV_ERROR_INT		BIT(22)
8986 
9087 #define VPE_INTC_EOI			0x00a0
9188 
9289 #define VPE_CLK_ENABLE			0x0100
93
-#define VPE_VPEDMA_CLK_ENABLE		(1 << 0)
94
-#define VPE_DATA_PATH_CLK_ENABLE	(1 << 1)
90
+#define VPE_VPEDMA_CLK_ENABLE		BIT(0)
91
+#define VPE_DATA_PATH_CLK_ENABLE	BIT(1)
9592 
9693 #define VPE_CLK_RESET			0x0104
9794 #define VPE_VPDMA_CLK_RESET_MASK	0x1
....@@ -104,11 +101,11 @@
104101 #define VPE_CLK_FORMAT_SELECT		0x010c
105102 #define VPE_CSC_SRC_SELECT_MASK		0x03
106103 #define VPE_CSC_SRC_SELECT_SHIFT	0
107
-#define VPE_RGB_OUT_SELECT		(1 << 8)
104
+#define VPE_RGB_OUT_SELECT		BIT(8)
108105 #define VPE_DS_SRC_SELECT_MASK		0x07
109106 #define VPE_DS_SRC_SELECT_SHIFT		9
110
-#define VPE_DS_BYPASS			(1 << 16)
111
-#define VPE_COLOR_SEPARATE_422		(1 << 18)
107
+#define VPE_DS_BYPASS			BIT(16)
108
+#define VPE_COLOR_SEPARATE_422		BIT(18)
112109 
113110 #define VPE_DS_SRC_DEI_SCALER		(5 << VPE_DS_SRC_SELECT_SHIFT)
114111 #define VPE_CSC_SRC_DEI_SCALER		(3 << VPE_CSC_SRC_SELECT_SHIFT)
....@@ -118,8 +115,8 @@
118115 #define VPE_RANGE_RANGE_MAP_Y_SHIFT	0
119116 #define VPE_RANGE_RANGE_MAP_UV_MASK	0x07
120117 #define VPE_RANGE_RANGE_MAP_UV_SHIFT	3
121
-#define VPE_RANGE_MAP_ON		(1 << 6)
122
-#define VPE_RANGE_REDUCTION_ON		(1 << 28)
118
+#define VPE_RANGE_MAP_ON		BIT(6)
119
+#define VPE_RANGE_REDUCTION_ON		BIT(28)
123120 
124121 /* VPE chrominance upsampler regs */
125122 #define VPE_US1_R0			0x0304
....@@ -198,13 +195,13 @@
198195 #define VPE_DEI_WIDTH_SHIFT		0
199196 #define VPE_DEI_HEIGHT_MASK		0x07ff
200197 #define VPE_DEI_HEIGHT_SHIFT		16
201
-#define VPE_DEI_INTERLACE_BYPASS	(1 << 29)
202
-#define VPE_DEI_FIELD_FLUSH		(1 << 30)
203
-#define VPE_DEI_PROGRESSIVE		(1 << 31)
198
+#define VPE_DEI_INTERLACE_BYPASS	BIT(29)
199
+#define VPE_DEI_FIELD_FLUSH		BIT(30)
200
+#define VPE_DEI_PROGRESSIVE		BIT(31)
204201 
205202 #define VPE_MDT_BYPASS			0x0604
206
-#define VPE_MDT_TEMPMAX_BYPASS		(1 << 0)
207
-#define VPE_MDT_SPATMAX_BYPASS		(1 << 1)
203
+#define VPE_MDT_TEMPMAX_BYPASS		BIT(0)
204
+#define VPE_MDT_SPATMAX_BYPASS		BIT(1)
208205 
209206 #define VPE_MDT_SF_THRESHOLD		0x0608
210207 #define VPE_MDT_SF_SC_THR1_MASK		0xff
....@@ -217,8 +214,8 @@
217214 #define VPE_EDI_CONFIG			0x060c
218215 #define VPE_EDI_INP_MODE_MASK		0x03
219216 #define VPE_EDI_INP_MODE_SHIFT		0
220
-#define VPE_EDI_ENABLE_3D		(1 << 2)
221
-#define VPE_EDI_ENABLE_CHROMA_3D	(1 << 3)
217
+#define VPE_EDI_ENABLE_3D		BIT(2)
218
+#define VPE_EDI_ENABLE_CHROMA_3D	BIT(3)
222219 #define VPE_EDI_CHROMA3D_COR_THR_MASK	0xff
223220 #define VPE_EDI_CHROMA3D_COR_THR_SHIFT	8
224221 #define VPE_EDI_DIR_COR_LOWER_THR_MASK	0xff
....@@ -271,7 +268,7 @@
271268 #define VPE_FMD_WINDOW_MINX_SHIFT	0
272269 #define VPE_FMD_WINDOW_MAXX_MASK	0x07ff
273270 #define VPE_FMD_WINDOW_MAXX_SHIFT	16
274
-#define VPE_FMD_WINDOW_ENABLE		(1 << 31)
271
+#define VPE_FMD_WINDOW_ENABLE		BIT(31)
275272 
276273 #define VPE_DEI_FMD_WINDOW_R1		0x0624
277274 #define VPE_FMD_WINDOW_MINY_MASK	0x07ff
....@@ -280,10 +277,10 @@
280277 #define VPE_FMD_WINDOW_MAXY_SHIFT	16
281278 
282279 #define VPE_DEI_FMD_CONTROL_R0		0x0628
283
-#define VPE_FMD_ENABLE			(1 << 0)
284
-#define VPE_FMD_LOCK			(1 << 1)
285
-#define VPE_FMD_JAM_DIR			(1 << 2)
286
-#define VPE_FMD_BED_ENABLE		(1 << 3)
280
+#define VPE_FMD_ENABLE			BIT(0)
281
+#define VPE_FMD_LOCK			BIT(1)
282
+#define VPE_FMD_JAM_DIR			BIT(2)
283
+#define VPE_FMD_BED_ENABLE		BIT(3)
287284 #define VPE_FMD_CAF_FIELD_THR_MASK	0xff
288285 #define VPE_FMD_CAF_FIELD_THR_SHIFT	16
289286 #define VPE_FMD_CAF_LINE_THR_MASK	0xff
....@@ -296,7 +293,7 @@
296293 #define VPE_DEI_FMD_STATUS_R0		0x0630
297294 #define VPE_FMD_CAF_MASK		0x000fffff
298295 #define VPE_FMD_CAF_SHIFT		0
299
-#define VPE_FMD_RESET			(1 << 24)
296
+#define VPE_FMD_RESET			BIT(24)
300297 
301298 #define VPE_DEI_FMD_STATUS_R1		0x0634
302299 #define VPE_FMD_FIELD_DIFF_MASK		0x0fffffff