~hc/RK356X_SDK_RELEASE.git

..	..	@@ -25,8 +25,9 @@
25	25	* Alex Deucher
26	26	* Jerome Glisse
27	27	*/
28		-#include <drm/drmP.h>
	28	+
29	29	#include "amdgpu.h"
	30	+#include <drm/drm_debugfs.h>
30	31	#include <drm/amdgpu_drm.h>
31	32	#include "amdgpu_sched.h"
32	33	#include "amdgpu_uvd.h"
..	..	@@ -35,8 +36,37 @@
35	36
36	37	#include <linux/vga_switcheroo.h>
37	38	#include <linux/slab.h>
	39	+#include <linux/uaccess.h>
	40	+#include <linux/pci.h>
38	41	#include <linux/pm_runtime.h>
39	42	#include "amdgpu_amdkfd.h"
	43	+#include "amdgpu_gem.h"
	44	+#include "amdgpu_display.h"
	45	+#include "amdgpu_ras.h"
	46	+
	47	+void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
	48	+{
	49	+ struct amdgpu_gpu_instance *gpu_instance;
	50	+ int i;
	51	+
	52	+ mutex_lock(&mgpu_info.mutex);
	53	+
	54	+ for (i = 0; i < mgpu_info.num_gpu; i++) {
	55	+ gpu_instance = &(mgpu_info.gpu_ins[i]);
	56	+ if (gpu_instance->adev == adev) {
	57	+ mgpu_info.gpu_ins[i] =
	58	+ mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
	59	+ mgpu_info.num_gpu--;
	60	+ if (adev->flags & AMD_IS_APU)
	61	+ mgpu_info.num_apu--;
	62	+ else
	63	+ mgpu_info.num_dgpu--;
	64	+ break;
	65	+ }
	66	+ }
	67	+
	68	+ mutex_unlock(&mgpu_info.mutex);
	69	+}
40	70
41	71	/**
42	72	* amdgpu_driver_unload_kms - Main unload function for KMS.
..	..	@@ -48,53 +78,67 @@
48	78	*/
49	79	void amdgpu_driver_unload_kms(struct drm_device *dev)
50	80	{
51		- struct amdgpu_device *adev = dev->dev_private;
	81	+ struct amdgpu_device *adev = drm_to_adev(dev);
52	82
53	83	if (adev == NULL)
54	84	return;
55	85
	86	+ amdgpu_unregister_gpu_instance(adev);
	87	+
56	88	if (adev->rmmio == NULL)
57		- goto done_free;
	89	+ return;
58	90
59		- if (amdgpu_sriov_vf(adev))
60		- amdgpu_virt_request_full_gpu(adev, false);
61		-
62		- if (amdgpu_device_is_px(dev)) {
	91	+ if (adev->runpm) {
63	92	pm_runtime_get_sync(dev->dev);
64	93	pm_runtime_forbid(dev->dev);
65	94	}
66	95
67	96	amdgpu_acpi_fini(adev);
68		-
69	97	amdgpu_device_fini(adev);
	98	+}
70	99
71		-done_free:
72		- kfree(adev);
73		- dev->dev_private = NULL;
	100	+void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
	101	+{
	102	+ struct amdgpu_gpu_instance *gpu_instance;
	103	+
	104	+ mutex_lock(&mgpu_info.mutex);
	105	+
	106	+ if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
	107	+ DRM_ERROR("Cannot register more gpu instance\n");
	108	+ mutex_unlock(&mgpu_info.mutex);
	109	+ return;
	110	+ }
	111	+
	112	+ gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
	113	+ gpu_instance->adev = adev;
	114	+ gpu_instance->mgpu_fan_enabled = 0;
	115	+
	116	+ mgpu_info.num_gpu++;
	117	+ if (adev->flags & AMD_IS_APU)
	118	+ mgpu_info.num_apu++;
	119	+ else
	120	+ mgpu_info.num_dgpu++;
	121	+
	122	+ mutex_unlock(&mgpu_info.mutex);
74	123	}
75	124
76	125	/**
77	126	* amdgpu_driver_load_kms - Main load function for KMS.
78	127	*
79		- * @dev: drm dev pointer
	128	+ * @adev: pointer to struct amdgpu_device
80	129	* @flags: device flags
81	130	*
82	131	* This is the main load function for KMS (all asics).
83	132	* Returns 0 on success, error on failure.
84	133	*/
85		-int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
	134	+int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
86	135	{
87		- struct amdgpu_device *adev;
	136	+ struct drm_device *dev;
88	137	int r, acpi_status;
89	138
90		- adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
91		- if (adev == NULL) {
92		- return -ENOMEM;
93		- }
94		- dev->dev_private = (void *)adev;
	139	+ dev = adev_to_drm(adev);
95	140
96		- if ((amdgpu_runtime_pm != 0) &&
97		- amdgpu_has_atpx() &&
	141	+ if (amdgpu_has_atpx() &&
98	142	(amdgpu_is_atpx_hybrid() \|\|
99	143	amdgpu_has_atpx_dgpu_power_cntl()) &&
100	144	((flags & AMD_IS_APU) == 0) &&
..	..	@@ -107,27 +151,57 @@
107	151	* properly initialize the GPU MC controller and permit
108	152	* VRAM allocation
109	153	*/
110		- r = amdgpu_device_init(adev, dev, dev->pdev, flags);
	154	+ r = amdgpu_device_init(adev, flags);
111	155	if (r) {
112	156	dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
113	157	goto out;
114	158	}
115	159
	160	+ if (amdgpu_device_supports_boco(dev) &&
	161	+ (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
	162	+ adev->runpm = true;
	163	+ } else if (amdgpu_device_supports_baco(dev) &&
	164	+ (amdgpu_runtime_pm != 0)) {
	165	+ switch (adev->asic_type) {
	166	+#ifdef CONFIG_DRM_AMDGPU_CIK
	167	+ case CHIP_BONAIRE:
	168	+ case CHIP_HAWAII:
	169	+#endif
	170	+ case CHIP_VEGA20:
	171	+ case CHIP_ARCTURUS:
	172	+ case CHIP_SIENNA_CICHLID:
	173	+ case CHIP_NAVY_FLOUNDER:
	174	+ /* enable runpm if runpm=1 */
	175	+ if (amdgpu_runtime_pm > 0)
	176	+ adev->runpm = true;
	177	+ break;
	178	+ case CHIP_VEGA10:
	179	+ /* turn runpm on if noretry=0 */
	180	+ if (!adev->gmc.noretry)
	181	+ adev->runpm = true;
	182	+ break;
	183	+ default:
	184	+ /* enable runpm on VI+ */
	185	+ adev->runpm = true;
	186	+ break;
	187	+ }
	188	+ }
	189	+
116	190	/* Call ACPI methods: require modeset init
117	191	* but failure is not fatal
118	192	*/
119		- if (!r) {
120		- acpi_status = amdgpu_acpi_init(adev);
121		- if (acpi_status)
122		- dev_dbg(&dev->pdev->dev,
123		- "Error during ACPI methods call\n");
124		- }
125	193
126		- if (amdgpu_device_is_px(dev)) {
127		- dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
	194	+ acpi_status = amdgpu_acpi_init(adev);
	195	+ if (acpi_status)
	196	+ dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
	197	+
	198	+ if (adev->runpm) {
	199	+ /* only need to skip on ATPX */
	200	+ if (amdgpu_device_supports_boco(dev) &&
	201	+ !amdgpu_is_atpx_hybrid())
	202	+ dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
128	203	pm_runtime_use_autosuspend(dev->dev);
129	204	pm_runtime_set_autosuspend_delay(dev->dev, 5000);
130		- pm_runtime_set_active(dev->dev);
131	205	pm_runtime_allow(dev->dev);
132	206	pm_runtime_mark_last_busy(dev->dev);
133	207	pm_runtime_put_autosuspend(dev->dev);
..	..	@@ -136,7 +210,7 @@
136	210	out:
137	211	if (r) {
138	212	/* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
139		- if (adev->rmmio && amdgpu_device_is_px(dev))
	213	+ if (adev->rmmio && adev->runpm)
140	214	pm_runtime_put_noidle(dev->dev);
141	215	amdgpu_driver_unload_kms(dev);
142	216	}
..	..	@@ -207,6 +281,28 @@
207	281	fw_info->ver = adev->pm.fw_version;
208	282	fw_info->feature = 0;
209	283	break;
	284	+ case AMDGPU_INFO_FW_TA:
	285	+ switch (query_fw->index) {
	286	+ case 0:
	287	+ fw_info->ver = adev->psp.ta_fw_version;
	288	+ fw_info->feature = adev->psp.ta_xgmi_ucode_version;
	289	+ break;
	290	+ case 1:
	291	+ fw_info->ver = adev->psp.ta_fw_version;
	292	+ fw_info->feature = adev->psp.ta_ras_ucode_version;
	293	+ break;
	294	+ case 2:
	295	+ fw_info->ver = adev->psp.ta_fw_version;
	296	+ fw_info->feature = adev->psp.ta_hdcp_ucode_version;
	297	+ break;
	298	+ case 3:
	299	+ fw_info->ver = adev->psp.ta_fw_version;
	300	+ fw_info->feature = adev->psp.ta_dtm_ucode_version;
	301	+ break;
	302	+ default:
	303	+ return -EINVAL;
	304	+ }
	305	+ break;
210	306	case AMDGPU_INFO_FW_SDMA:
211	307	if (query_fw->index >= adev->sdma.num_instances)
212	308	return -EINVAL;
..	..	@@ -221,9 +317,151 @@
221	317	fw_info->ver = adev->psp.asd_fw_version;
222	318	fw_info->feature = adev->psp.asd_feature_version;
223	319	break;
	320	+ case AMDGPU_INFO_FW_DMCU:
	321	+ fw_info->ver = adev->dm.dmcu_fw_version;
	322	+ fw_info->feature = 0;
	323	+ break;
	324	+ case AMDGPU_INFO_FW_DMCUB:
	325	+ fw_info->ver = adev->dm.dmcub_fw_version;
	326	+ fw_info->feature = 0;
	327	+ break;
224	328	default:
225	329	return -EINVAL;
226	330	}
	331	+ return 0;
	332	+}
	333	+
	334	+static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
	335	+ struct drm_amdgpu_info *info,
	336	+ struct drm_amdgpu_info_hw_ip *result)
	337	+{
	338	+ uint32_t ib_start_alignment = 0;
	339	+ uint32_t ib_size_alignment = 0;
	340	+ enum amd_ip_block_type type;
	341	+ unsigned int num_rings = 0;
	342	+ unsigned int i, j;
	343	+
	344	+ if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
	345	+ return -EINVAL;
	346	+
	347	+ switch (info->query_hw_ip.type) {
	348	+ case AMDGPU_HW_IP_GFX:
	349	+ type = AMD_IP_BLOCK_TYPE_GFX;
	350	+ for (i = 0; i < adev->gfx.num_gfx_rings; i++)
	351	+ if (adev->gfx.gfx_ring[i].sched.ready)
	352	+ ++num_rings;
	353	+ ib_start_alignment = 32;
	354	+ ib_size_alignment = 32;
	355	+ break;
	356	+ case AMDGPU_HW_IP_COMPUTE:
	357	+ type = AMD_IP_BLOCK_TYPE_GFX;
	358	+ for (i = 0; i < adev->gfx.num_compute_rings; i++)
	359	+ if (adev->gfx.compute_ring[i].sched.ready)
	360	+ ++num_rings;
	361	+ ib_start_alignment = 32;
	362	+ ib_size_alignment = 32;
	363	+ break;
	364	+ case AMDGPU_HW_IP_DMA:
	365	+ type = AMD_IP_BLOCK_TYPE_SDMA;
	366	+ for (i = 0; i < adev->sdma.num_instances; i++)
	367	+ if (adev->sdma.instance[i].ring.sched.ready)
	368	+ ++num_rings;
	369	+ ib_start_alignment = 256;
	370	+ ib_size_alignment = 4;
	371	+ break;
	372	+ case AMDGPU_HW_IP_UVD:
	373	+ type = AMD_IP_BLOCK_TYPE_UVD;
	374	+ for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
	375	+ if (adev->uvd.harvest_config & (1 << i))
	376	+ continue;
	377	+
	378	+ if (adev->uvd.inst[i].ring.sched.ready)
	379	+ ++num_rings;
	380	+ }
	381	+ ib_start_alignment = 64;
	382	+ ib_size_alignment = 64;
	383	+ break;
	384	+ case AMDGPU_HW_IP_VCE:
	385	+ type = AMD_IP_BLOCK_TYPE_VCE;
	386	+ for (i = 0; i < adev->vce.num_rings; i++)
	387	+ if (adev->vce.ring[i].sched.ready)
	388	+ ++num_rings;
	389	+ ib_start_alignment = 4;
	390	+ ib_size_alignment = 1;
	391	+ break;
	392	+ case AMDGPU_HW_IP_UVD_ENC:
	393	+ type = AMD_IP_BLOCK_TYPE_UVD;
	394	+ for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
	395	+ if (adev->uvd.harvest_config & (1 << i))
	396	+ continue;
	397	+
	398	+ for (j = 0; j < adev->uvd.num_enc_rings; j++)
	399	+ if (adev->uvd.inst[i].ring_enc[j].sched.ready)
	400	+ ++num_rings;
	401	+ }
	402	+ ib_start_alignment = 64;
	403	+ ib_size_alignment = 64;
	404	+ break;
	405	+ case AMDGPU_HW_IP_VCN_DEC:
	406	+ type = AMD_IP_BLOCK_TYPE_VCN;
	407	+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
	408	+ if (adev->uvd.harvest_config & (1 << i))
	409	+ continue;
	410	+
	411	+ if (adev->vcn.inst[i].ring_dec.sched.ready)
	412	+ ++num_rings;
	413	+ }
	414	+ ib_start_alignment = 16;
	415	+ ib_size_alignment = 16;
	416	+ break;
	417	+ case AMDGPU_HW_IP_VCN_ENC:
	418	+ type = AMD_IP_BLOCK_TYPE_VCN;
	419	+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
	420	+ if (adev->uvd.harvest_config & (1 << i))
	421	+ continue;
	422	+
	423	+ for (j = 0; j < adev->vcn.num_enc_rings; j++)
	424	+ if (adev->vcn.inst[i].ring_enc[j].sched.ready)
	425	+ ++num_rings;
	426	+ }
	427	+ ib_start_alignment = 64;
	428	+ ib_size_alignment = 1;
	429	+ break;
	430	+ case AMDGPU_HW_IP_VCN_JPEG:
	431	+ type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
	432	+ AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
	433	+
	434	+ for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
	435	+ if (adev->jpeg.harvest_config & (1 << i))
	436	+ continue;
	437	+
	438	+ if (adev->jpeg.inst[i].ring_dec.sched.ready)
	439	+ ++num_rings;
	440	+ }
	441	+ ib_start_alignment = 16;
	442	+ ib_size_alignment = 16;
	443	+ break;
	444	+ default:
	445	+ return -EINVAL;
	446	+ }
	447	+
	448	+ for (i = 0; i < adev->num_ip_blocks; i++)
	449	+ if (adev->ip_blocks[i].version->type == type &&
	450	+ adev->ip_blocks[i].status.valid)
	451	+ break;
	452	+
	453	+ if (i == adev->num_ip_blocks)
	454	+ return 0;
	455	+
	456	+ num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
	457	+ num_rings);
	458	+
	459	+ result->hw_ip_version_major = adev->ip_blocks[i].version->major;
	460	+ result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
	461	+ result->capabilities_flags = 0;
	462	+ result->available_rings = (1 << num_rings) - 1;
	463	+ result->ib_start_alignment = ib_start_alignment;
	464	+ result->ib_size_alignment = ib_size_alignment;
227	465	return 0;
228	466	}
229	467
..	..	@@ -244,7 +482,7 @@
244	482	*/
245	483	static int amdgpu_info_ioctl(struct drm_device dev, void data, struct drm_file *filp)
246	484	{
247		- struct amdgpu_device *adev = dev->dev_private;
	485	+ struct amdgpu_device *adev = drm_to_adev(dev);
248	486	struct drm_amdgpu_info *info = data;
249	487	struct amdgpu_mode_info *minfo = &adev->mode_info;
250	488	void __user out = (void __user )(uintptr_t)info->return_pointer;
..	..	@@ -252,7 +490,7 @@
252	490	struct drm_crtc *crtc;
253	491	uint32_t ui32 = 0;
254	492	uint64_t ui64 = 0;
255		- int i, j, found;
	493	+ int i, found;
256	494	int ui32_size = sizeof(ui32);
257	495
258	496	if (!info->return_size \|\| !info->return_pointer)
..	..	@@ -267,6 +505,7 @@
267	505	crtc = (struct drm_crtc *)minfo->crtcs[i];
268	506	if (crtc && crtc->base.id == info->mode_crtc.id) {
269	507	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
	508	+
270	509	ui32 = amdgpu_crtc->crtc_id;
271	510	found = 1;
272	511	break;
..	..	@@ -279,101 +518,14 @@
279	518	return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
280	519	case AMDGPU_INFO_HW_IP_INFO: {
281	520	struct drm_amdgpu_info_hw_ip ip = {};
282		- enum amd_ip_block_type type;
283		- uint32_t ring_mask = 0;
284		- uint32_t ib_start_alignment = 0;
285		- uint32_t ib_size_alignment = 0;
	521	+ int ret;
286	522
287		- if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
288		- return -EINVAL;
	523	+ ret = amdgpu_hw_ip_info(adev, info, &ip);
	524	+ if (ret)
	525	+ return ret;
289	526
290		- switch (info->query_hw_ip.type) {
291		- case AMDGPU_HW_IP_GFX:
292		- type = AMD_IP_BLOCK_TYPE_GFX;
293		- for (i = 0; i < adev->gfx.num_gfx_rings; i++)
294		- ring_mask \|= adev->gfx.gfx_ring[i].ready << i;
295		- ib_start_alignment = 32;
296		- ib_size_alignment = 32;
297		- break;
298		- case AMDGPU_HW_IP_COMPUTE:
299		- type = AMD_IP_BLOCK_TYPE_GFX;
300		- for (i = 0; i < adev->gfx.num_compute_rings; i++)
301		- ring_mask \|= adev->gfx.compute_ring[i].ready << i;
302		- ib_start_alignment = 32;
303		- ib_size_alignment = 32;
304		- break;
305		- case AMDGPU_HW_IP_DMA:
306		- type = AMD_IP_BLOCK_TYPE_SDMA;
307		- for (i = 0; i < adev->sdma.num_instances; i++)
308		- ring_mask \|= adev->sdma.instance[i].ring.ready << i;
309		- ib_start_alignment = 256;
310		- ib_size_alignment = 4;
311		- break;
312		- case AMDGPU_HW_IP_UVD:
313		- type = AMD_IP_BLOCK_TYPE_UVD;
314		- for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
315		- if (adev->uvd.harvest_config & (1 << i))
316		- continue;
317		- ring_mask \|= adev->uvd.inst[i].ring.ready;
318		- }
319		- ib_start_alignment = 64;
320		- ib_size_alignment = 64;
321		- break;
322		- case AMDGPU_HW_IP_VCE:
323		- type = AMD_IP_BLOCK_TYPE_VCE;
324		- for (i = 0; i < adev->vce.num_rings; i++)
325		- ring_mask \|= adev->vce.ring[i].ready << i;
326		- ib_start_alignment = 4;
327		- ib_size_alignment = 1;
328		- break;
329		- case AMDGPU_HW_IP_UVD_ENC:
330		- type = AMD_IP_BLOCK_TYPE_UVD;
331		- for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
332		- if (adev->uvd.harvest_config & (1 << i))
333		- continue;
334		- for (j = 0; j < adev->uvd.num_enc_rings; j++)
335		- ring_mask \|= adev->uvd.inst[i].ring_enc[j].ready << j;
336		- }
337		- ib_start_alignment = 64;
338		- ib_size_alignment = 64;
339		- break;
340		- case AMDGPU_HW_IP_VCN_DEC:
341		- type = AMD_IP_BLOCK_TYPE_VCN;
342		- ring_mask = adev->vcn.ring_dec.ready;
343		- ib_start_alignment = 16;
344		- ib_size_alignment = 16;
345		- break;
346		- case AMDGPU_HW_IP_VCN_ENC:
347		- type = AMD_IP_BLOCK_TYPE_VCN;
348		- for (i = 0; i < adev->vcn.num_enc_rings; i++)
349		- ring_mask \|= adev->vcn.ring_enc[i].ready << i;
350		- ib_start_alignment = 64;
351		- ib_size_alignment = 1;
352		- break;
353		- case AMDGPU_HW_IP_VCN_JPEG:
354		- type = AMD_IP_BLOCK_TYPE_VCN;
355		- ring_mask = adev->vcn.ring_jpeg.ready;
356		- ib_start_alignment = 16;
357		- ib_size_alignment = 16;
358		- break;
359		- default:
360		- return -EINVAL;
361		- }
362		-
363		- for (i = 0; i < adev->num_ip_blocks; i++) {
364		- if (adev->ip_blocks[i].version->type == type &&
365		- adev->ip_blocks[i].status.valid) {
366		- ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
367		- ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
368		- ip.capabilities_flags = 0;
369		- ip.available_rings = ring_mask;
370		- ip.ib_start_alignment = ib_start_alignment;
371		- ip.ib_size_alignment = ib_size_alignment;
372		- break;
373		- }
374		- }
375		- return copy_to_user(out, &ip,
376		- min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
	527	+ ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
	528	+ return ret ? -EFAULT : 0;
377	529	}
378	530	case AMDGPU_INFO_HW_IP_COUNT: {
379	531	enum amd_ip_block_type type;
..	..	@@ -400,8 +552,11 @@
400	552	break;
401	553	case AMDGPU_HW_IP_VCN_DEC:
402	554	case AMDGPU_HW_IP_VCN_ENC:
403		- case AMDGPU_HW_IP_VCN_JPEG:
404	555	type = AMD_IP_BLOCK_TYPE_VCN;
	556	+ break;
	557	+ case AMDGPU_HW_IP_VCN_JPEG:
	558	+ type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
	559	+ AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
405	560	break;
406	561	default:
407	562	return -EINVAL;
..	..	@@ -443,25 +598,22 @@
443	598	ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
444	599	return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
445	600	case AMDGPU_INFO_VRAM_USAGE:
446		- ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
	601	+ ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
447	602	return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
448	603	case AMDGPU_INFO_VIS_VRAM_USAGE:
449		- ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
	604	+ ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
450	605	return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
451	606	case AMDGPU_INFO_GTT_USAGE:
452		- ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
	607	+ ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
453	608	return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
454	609	case AMDGPU_INFO_GDS_CONFIG: {
455	610	struct drm_amdgpu_info_gds gds_info;
456	611
457	612	memset(&gds_info, 0, sizeof(gds_info));
458		- gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
459		- gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
460		- gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
461		- gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
462		- gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
463		- gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
464		- gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
	613	+ gds_info.compute_partition_size = adev->gds.gds_size;
	614	+ gds_info.gds_total_size = adev->gds.gds_size;
	615	+ gds_info.gws_per_compute_partition = adev->gds.gws_size;
	616	+ gds_info.oa_per_compute_partition = adev->gds.oa_size;
465	617	return copy_to_user(out, &gds_info,
466	618	min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
467	619	}
..	..	@@ -469,10 +621,13 @@
469	621	struct drm_amdgpu_info_vram_gtt vram_gtt;
470	622
471	623	vram_gtt.vram_size = adev->gmc.real_vram_size -
472		- atomic64_read(&adev->vram_pin_size);
473		- vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
474		- atomic64_read(&adev->visible_pin_size);
475		- vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
	624	+ atomic64_read(&adev->vram_pin_size) -
	625	+ AMDGPU_VM_RESERVED_VRAM;
	626	+ vram_gtt.vram_cpu_accessible_size =
	627	+ min(adev->gmc.visible_vram_size -
	628	+ atomic64_read(&adev->visible_pin_size),
	629	+ vram_gtt.vram_size);
	630	+ vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
476	631	vram_gtt.gtt_size *= PAGE_SIZE;
477	632	vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
478	633	return copy_to_user(out, &vram_gtt,
..	..	@@ -480,30 +635,36 @@
480	635	}
481	636	case AMDGPU_INFO_MEMORY: {
482	637	struct drm_amdgpu_memory_info mem;
483		-
	638	+ struct ttm_resource_manager *vram_man =
	639	+ ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
	640	+ struct ttm_resource_manager *gtt_man =
	641	+ ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
484	642	memset(&mem, 0, sizeof(mem));
485	643	mem.vram.total_heap_size = adev->gmc.real_vram_size;
486	644	mem.vram.usable_heap_size = adev->gmc.real_vram_size -
487		- atomic64_read(&adev->vram_pin_size);
	645	+ atomic64_read(&adev->vram_pin_size) -
	646	+ AMDGPU_VM_RESERVED_VRAM;
488	647	mem.vram.heap_usage =
489		- amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
	648	+ amdgpu_vram_mgr_usage(vram_man);
490	649	mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
491	650
492	651	mem.cpu_accessible_vram.total_heap_size =
493	652	adev->gmc.visible_vram_size;
494		- mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
495		- atomic64_read(&adev->visible_pin_size);
	653	+ mem.cpu_accessible_vram.usable_heap_size =
	654	+ min(adev->gmc.visible_vram_size -
	655	+ atomic64_read(&adev->visible_pin_size),
	656	+ mem.vram.usable_heap_size);
496	657	mem.cpu_accessible_vram.heap_usage =
497		- amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
	658	+ amdgpu_vram_mgr_vis_usage(vram_man);
498	659	mem.cpu_accessible_vram.max_allocation =
499	660	mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
500	661
501		- mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
	662	+ mem.gtt.total_heap_size = gtt_man->size;
502	663	mem.gtt.total_heap_size *= PAGE_SIZE;
503	664	mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
504	665	atomic64_read(&adev->gart_pin_size);
505	666	mem.gtt.heap_usage =
506		- amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
	667	+ amdgpu_gtt_mgr_usage(gtt_man);
507	668	mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
508	669
509	670	return copy_to_user(out, &mem,
..	..	@@ -511,17 +672,18 @@
511	672	? -EFAULT : 0;
512	673	}
513	674	case AMDGPU_INFO_READ_MMR_REG: {
514		- unsigned n, alloc_size;
	675	+ unsigned int n, alloc_size;
515	676	uint32_t *regs;
516		- unsigned se_num = (info->read_mmr_reg.instance >>
	677	+ unsigned int se_num = (info->read_mmr_reg.instance >>
517	678	AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
518	679	AMDGPU_INFO_MMR_SE_INDEX_MASK;
519		- unsigned sh_num = (info->read_mmr_reg.instance >>
	680	+ unsigned int sh_num = (info->read_mmr_reg.instance >>
520	681	AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
521	682	AMDGPU_INFO_MMR_SH_INDEX_MASK;
522	683
523	684	/* set full masks if the userspace set all bits
524		- * in the bitfields */
	685	+ * in the bitfields
	686	+ */
525	687	if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
526	688	se_num = 0xffffffff;
527	689	else if (se_num >= AMDGPU_GFX_MAX_SE)
..	..	@@ -539,15 +701,19 @@
539	701	return -ENOMEM;
540	702	alloc_size = info->read_mmr_reg.count * sizeof(*regs);
541	703
542		- for (i = 0; i < info->read_mmr_reg.count; i++)
	704	+ amdgpu_gfx_off_ctrl(adev, false);
	705	+ for (i = 0; i < info->read_mmr_reg.count; i++) {
543	706	if (amdgpu_asic_read_register(adev, se_num, sh_num,
544	707	info->read_mmr_reg.dword_offset + i,
545	708	&regs[i])) {
546	709	DRM_DEBUG_KMS("unallowed offset %#x\n",
547	710	info->read_mmr_reg.dword_offset + i);
548	711	kfree(regs);
	712	+ amdgpu_gfx_off_ctrl(adev, true);
549	713	return -EFAULT;
550	714	}
	715	+ }
	716	+ amdgpu_gfx_off_ctrl(adev, true);
551	717	n = copy_to_user(out, regs, min(size, alloc_size));
552	718	kfree(regs);
553	719	return n ? -EFAULT : 0;
..	..	@@ -581,27 +747,30 @@
581	747	dev_info.ids_flags = 0;
582	748	if (adev->flags & AMD_IS_APU)
583	749	dev_info.ids_flags \|= AMDGPU_IDS_FLAGS_FUSION;
584		- if (amdgpu_sriov_vf(adev))
	750	+ if (amdgpu_mcbp \|\| amdgpu_sriov_vf(adev))
585	751	dev_info.ids_flags \|= AMDGPU_IDS_FLAGS_PREEMPTION;
	752	+ if (amdgpu_is_tmz(adev))
	753	+ dev_info.ids_flags \|= AMDGPU_IDS_FLAGS_TMZ;
586	754
587	755	vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
588	756	vm_size -= AMDGPU_VA_RESERVED_SIZE;
589	757
590	758	/* Older VCE FW versions are buggy and can handle only 40bits */
591		- if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
	759	+ if (adev->vce.fw_version &&
	760	+ adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
592	761	vm_size = min(vm_size, 1ULL << 40);
593	762
594	763	dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
595	764	dev_info.virtual_address_max =
596		- min(vm_size, AMDGPU_VA_HOLE_START);
	765	+ min(vm_size, AMDGPU_GMC_HOLE_START);
597	766
598		- if (vm_size > AMDGPU_VA_HOLE_START) {
599		- dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
600		- dev_info.high_va_max = AMDGPU_VA_HOLE_END \| vm_size;
	767	+ if (vm_size > AMDGPU_GMC_HOLE_START) {
	768	+ dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
	769	+ dev_info.high_va_max = AMDGPU_GMC_HOLE_END \| vm_size;
601	770	}
602		- dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
	771	+ dev_info.virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
603	772	dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
604		- dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
	773	+ dev_info.gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
605	774	dev_info.cu_active_number = adev->gfx.cu_info.number;
606	775	dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
607	776	dev_info.ce_ram_size = adev->gfx.ce_ram_size;
..	..	@@ -614,17 +783,6 @@
614	783	dev_info.vce_harvest_config = adev->vce.harvest_config;
615	784	dev_info.gc_double_offchip_lds_buf =
616	785	adev->gfx.config.double_offchip_lds_buf;
617		-
618		- if (amdgpu_ngg) {
619		- dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
620		- dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
621		- dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
622		- dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
623		- dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
624		- dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
625		- dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
626		- dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
627		- }
628	786	dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
629	787	dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
630	788	dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
..	..	@@ -633,11 +791,17 @@
633	791	dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
634	792	dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
635	793
	794	+ if (adev->family >= AMDGPU_FAMILY_NV)
	795	+ dev_info.pa_sc_tile_steering_override =
	796	+ adev->gfx.config.pa_sc_tile_steering_override;
	797	+
	798	+ dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
	799	+
636	800	return copy_to_user(out, &dev_info,
637	801	min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
638	802	}
639	803	case AMDGPU_INFO_VCE_CLOCK_TABLE: {
640		- unsigned i;
	804	+ unsigned int i;
641	805	struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
642	806	struct amd_vce_state *vce_state;
643	807
..	..	@@ -793,6 +957,18 @@
793	957	case AMDGPU_INFO_VRAM_LOST_COUNTER:
794	958	ui32 = atomic_read(&adev->vram_lost_counter);
795	959	return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
	960	+ case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
	961	+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
	962	+ uint64_t ras_mask;
	963	+
	964	+ if (!ras)
	965	+ return -EINVAL;
	966	+ ras_mask = (uint64_t)ras->supported << 32 \| ras->features;
	967	+
	968	+ return copy_to_user(out, &ras_mask,
	969	+ min_t(u64, size, sizeof(ras_mask))) ?
	970	+ -EFAULT : 0;
	971	+ }
796	972	default:
797	973	DRM_DEBUG_KMS("Invalid request %d\n", info->query);
798	974	return -EINVAL;
..	..	@@ -828,12 +1004,18 @@
828	1004	*/
829	1005	int amdgpu_driver_open_kms(struct drm_device dev, struct drm_file file_priv)
830	1006	{
831		- struct amdgpu_device *adev = dev->dev_private;
	1007	+ struct amdgpu_device *adev = drm_to_adev(dev);
832	1008	struct amdgpu_fpriv *fpriv;
833	1009	int r, pasid;
834	1010
835	1011	/* Ensure IB tests are run on ring */
836		- flush_delayed_work(&adev->late_init_work);
	1012	+ flush_delayed_work(&adev->delayed_init_work);
	1013	+
	1014	+
	1015	+ if (amdgpu_ras_intr_triggered()) {
	1016	+ DRM_ERROR("RAS Intr triggered, device disabled!!");
	1017	+ return -EHWPOISON;
	1018	+ }
837	1019
838	1020	file_priv->driver_priv = NULL;
839	1021
..	..	@@ -862,8 +1044,11 @@
862	1044	goto error_vm;
863	1045	}
864	1046
865		- if (amdgpu_sriov_vf(adev)) {
866		- r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
	1047	+ if (amdgpu_mcbp \|\| amdgpu_sriov_vf(adev)) {
	1048	+ uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
	1049	+
	1050	+ r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
	1051	+ &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
867	1052	if (r)
868	1053	goto error_vm;
869	1054	}
..	..	@@ -904,11 +1089,11 @@
904	1089	void amdgpu_driver_postclose_kms(struct drm_device *dev,
905	1090	struct drm_file *file_priv)
906	1091	{
907		- struct amdgpu_device *adev = dev->dev_private;
	1092	+ struct amdgpu_device *adev = drm_to_adev(dev);
908	1093	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
909	1094	struct amdgpu_bo_list *list;
910	1095	struct amdgpu_bo *pd;
911		- unsigned int pasid;
	1096	+ u32 pasid;
912	1097	int handle;
913	1098
914	1099	if (!fpriv)
..	..	@@ -916,14 +1101,14 @@
916	1101
917	1102	pm_runtime_get_sync(dev->dev);
918	1103
919		- if (adev->asic_type != CHIP_RAVEN) {
	1104	+ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
920	1105	amdgpu_uvd_free_handles(adev, file_priv);
	1106	+ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
921	1107	amdgpu_vce_free_handles(adev, file_priv);
922		- }
923	1108
924	1109	amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
925	1110
926		- if (amdgpu_sriov_vf(adev)) {
	1111	+ if (amdgpu_mcbp \|\| amdgpu_sriov_vf(adev)) {
927	1112	/* TODO: how to handle reserve failure */
928	1113	BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
929	1114	amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
..	..	@@ -934,11 +1119,11 @@
934	1119	pasid = fpriv->vm.pasid;
935	1120	pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
936	1121
937		- amdgpu_vm_fini(adev, &fpriv->vm);
938	1122	amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
	1123	+ amdgpu_vm_fini(adev, &fpriv->vm);
939	1124
940	1125	if (pasid)
941		- amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
	1126	+ amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
942	1127	amdgpu_bo_unref(&pd);
943	1128
944	1129	idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
..	..	@@ -960,15 +1145,16 @@
960	1145	/**
961	1146	* amdgpu_get_vblank_counter_kms - get frame count
962	1147	*
963		- * @dev: drm dev pointer
964		- * @pipe: crtc to get the frame count from
	1148	+ * @crtc: crtc to get the frame count from
965	1149	*
966	1150	* Gets the frame count on the requested crtc (all asics).
967	1151	* Returns frame count on success, -EINVAL on failure.
968	1152	*/
969		-u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
	1153	+u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
970	1154	{
971		- struct amdgpu_device *adev = dev->dev_private;
	1155	+ struct drm_device *dev = crtc->dev;
	1156	+ unsigned int pipe = crtc->index;
	1157	+ struct amdgpu_device *adev = drm_to_adev(dev);
972	1158	int vpos, hpos, stat;
973	1159	u32 count;
974	1160
..	..	@@ -1027,15 +1213,16 @@
1027	1213	/**
1028	1214	* amdgpu_enable_vblank_kms - enable vblank interrupt
1029	1215	*
1030		- * @dev: drm dev pointer
1031		- * @pipe: crtc to enable vblank interrupt for
	1216	+ * @crtc: crtc to enable vblank interrupt for
1032	1217	*
1033	1218	* Enable the interrupt on the requested crtc (all asics).
1034	1219	* Returns 0 on success, -EINVAL on failure.
1035	1220	*/
1036		-int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
	1221	+int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1037	1222	{
1038		- struct amdgpu_device *adev = dev->dev_private;
	1223	+ struct drm_device *dev = crtc->dev;
	1224	+ unsigned int pipe = crtc->index;
	1225	+ struct amdgpu_device *adev = drm_to_adev(dev);
1039	1226	int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1040	1227
1041	1228	return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
..	..	@@ -1044,14 +1231,15 @@
1044	1231	/**
1045	1232	* amdgpu_disable_vblank_kms - disable vblank interrupt
1046	1233	*
1047		- * @dev: drm dev pointer
1048		- * @pipe: crtc to disable vblank interrupt for
	1234	+ * @crtc: crtc to disable vblank interrupt for
1049	1235	*
1050	1236	* Disable the interrupt on the requested crtc (all asics).
1051	1237	*/
1052		-void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
	1238	+void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1053	1239	{
1054		- struct amdgpu_device *adev = dev->dev_private;
	1240	+ struct drm_device *dev = crtc->dev;
	1241	+ unsigned int pipe = crtc->index;
	1242	+ struct amdgpu_device *adev = drm_to_adev(dev);
1055	1243	int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1056	1244
1057	1245	amdgpu_irq_put(adev, &adev->crtc_irq, idx);
..	..	@@ -1087,7 +1275,7 @@
1087	1275	{
1088	1276	struct drm_info_node node = (struct drm_info_node ) m->private;
1089	1277	struct drm_device *dev = node->minor->dev;
1090		- struct amdgpu_device *adev = dev->dev_private;
	1278	+ struct amdgpu_device *adev = drm_to_adev(dev);
1091	1279	struct drm_amdgpu_info_firmware fw_info;
1092	1280	struct drm_amdgpu_query_fw query_fw;
1093	1281	struct atom_context *ctx = adev->mode_info.atom_context;
..	..	@@ -1183,8 +1371,7 @@
1183	1371	fw_info.feature, fw_info.ver);
1184	1372
1185	1373	/* MEC2 */
1186		- if (adev->asic_type == CHIP_KAVERI \|\|
1187		- (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
	1374	+ if (adev->gfx.mec2_fw) {
1188	1375	query_fw.index = 1;
1189	1376	ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1190	1377	if (ret)
..	..	@@ -1209,6 +1396,34 @@
1209	1396	return ret;
1210	1397	seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1211	1398	fw_info.feature, fw_info.ver);
	1399	+
	1400	+ query_fw.fw_type = AMDGPU_INFO_FW_TA;
	1401	+ for (i = 0; i < 4; i++) {
	1402	+ query_fw.index = i;
	1403	+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
	1404	+ if (ret)
	1405	+ continue;
	1406	+ switch (query_fw.index) {
	1407	+ case 0:
	1408	+ seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
	1409	+ "RAS", fw_info.feature, fw_info.ver);
	1410	+ break;
	1411	+ case 1:
	1412	+ seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
	1413	+ "XGMI", fw_info.feature, fw_info.ver);
	1414	+ break;
	1415	+ case 2:
	1416	+ seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
	1417	+ "HDCP", fw_info.feature, fw_info.ver);
	1418	+ break;
	1419	+ case 3:
	1420	+ seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
	1421	+ "DTM", fw_info.feature, fw_info.ver);
	1422	+ break;
	1423	+ default:
	1424	+ return -EINVAL;
	1425	+ }
	1426	+ }
1212	1427
1213	1428	/* SMC */
1214	1429	query_fw.fw_type = AMDGPU_INFO_FW_SMC;
..	..	@@ -1237,6 +1452,22 @@
1237	1452	seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1238	1453	fw_info.feature, fw_info.ver);
1239	1454
	1455	+ /* DMCU */
	1456	+ query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
	1457	+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
	1458	+ if (ret)
	1459	+ return ret;
	1460	+ seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
	1461	+ fw_info.feature, fw_info.ver);
	1462	+
	1463	+ /* DMCUB */
	1464	+ query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
	1465	+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
	1466	+ if (ret)
	1467	+ return ret;
	1468	+ seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
	1469	+ fw_info.feature, fw_info.ver);
	1470	+
1240	1471
1241	1472	seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1242	1473