.. | .. |
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1 | | -/* |
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2 | | - This file is provided under a dual BSD/GPLv2 license. When using or |
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3 | | - redistributing this file, you may do so under either license. |
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4 | | - |
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5 | | - GPL LICENSE SUMMARY |
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6 | | - Copyright(c) 2014 Intel Corporation. |
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7 | | - This program is free software; you can redistribute it and/or modify |
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8 | | - it under the terms of version 2 of the GNU General Public License as |
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9 | | - published by the Free Software Foundation. |
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10 | | - |
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11 | | - This program is distributed in the hope that it will be useful, but |
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12 | | - WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | | - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | | - General Public License for more details. |
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15 | | - |
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16 | | - Contact Information: |
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17 | | - qat-linux@intel.com |
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18 | | - |
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19 | | - BSD LICENSE |
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20 | | - Copyright(c) 2014 Intel Corporation. |
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21 | | - Redistribution and use in source and binary forms, with or without |
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22 | | - modification, are permitted provided that the following conditions |
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23 | | - are met: |
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24 | | - |
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25 | | - * Redistributions of source code must retain the above copyright |
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26 | | - notice, this list of conditions and the following disclaimer. |
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27 | | - * Redistributions in binary form must reproduce the above copyright |
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28 | | - notice, this list of conditions and the following disclaimer in |
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29 | | - the documentation and/or other materials provided with the |
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30 | | - distribution. |
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31 | | - * Neither the name of Intel Corporation nor the names of its |
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32 | | - contributors may be used to endorse or promote products derived |
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33 | | - from this software without specific prior written permission. |
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34 | | - |
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35 | | - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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36 | | - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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37 | | - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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38 | | - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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39 | | - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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40 | | - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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41 | | - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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42 | | - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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43 | | - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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44 | | - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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45 | | - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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46 | | -*/ |
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| 1 | +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) |
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| 2 | +/* Copyright(c) 2014 - 2020 Intel Corporation */ |
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47 | 3 | #include <linux/types.h> |
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48 | 4 | #include <linux/mutex.h> |
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49 | 5 | #include <linux/slab.h> |
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50 | | -#include <linux/delay.h> |
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| 6 | +#include <linux/iopoll.h> |
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51 | 7 | #include <linux/pci.h> |
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52 | 8 | #include <linux/dma-mapping.h> |
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53 | 9 | #include "adf_accel_devices.h" |
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.. | .. |
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60 | 16 | #define ADF_DH895XCC_MAILBOX_BASE_OFFSET 0x20970 |
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61 | 17 | #define ADF_DH895XCC_MAILBOX_STRIDE 0x1000 |
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62 | 18 | #define ADF_ADMINMSG_LEN 32 |
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| 19 | +#define ADF_CONST_TABLE_SIZE 1024 |
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| 20 | +#define ADF_ADMIN_POLL_DELAY_US 20 |
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| 21 | +#define ADF_ADMIN_POLL_TIMEOUT_US (5 * USEC_PER_SEC) |
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63 | 22 | |
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64 | 23 | static const u8 const_tab[1024] __aligned(1024) = { |
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65 | 24 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
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.. | .. |
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154 | 113 | static int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev, u32 ae, |
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155 | 114 | void *in, void *out) |
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156 | 115 | { |
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| 116 | + int ret; |
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| 117 | + u32 status; |
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157 | 118 | struct adf_admin_comms *admin = accel_dev->admin; |
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158 | 119 | int offset = ae * ADF_ADMINMSG_LEN * 2; |
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159 | 120 | void __iomem *mailbox = admin->mailbox_addr; |
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160 | 121 | int mb_offset = ae * ADF_DH895XCC_MAILBOX_STRIDE; |
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161 | | - int times, received; |
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| 122 | + struct icp_qat_fw_init_admin_req *request = in; |
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162 | 123 | |
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163 | 124 | mutex_lock(&admin->lock); |
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164 | 125 | |
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.. | .. |
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169 | 130 | |
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170 | 131 | memcpy(admin->virt_addr + offset, in, ADF_ADMINMSG_LEN); |
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171 | 132 | ADF_CSR_WR(mailbox, mb_offset, 1); |
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172 | | - received = 0; |
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173 | | - for (times = 0; times < 50; times++) { |
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174 | | - msleep(20); |
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175 | | - if (ADF_CSR_RD(mailbox, mb_offset) == 0) { |
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176 | | - received = 1; |
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177 | | - break; |
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178 | | - } |
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179 | | - } |
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180 | | - if (received) |
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| 133 | + |
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| 134 | + ret = read_poll_timeout(ADF_CSR_RD, status, status == 0, |
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| 135 | + ADF_ADMIN_POLL_DELAY_US, |
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| 136 | + ADF_ADMIN_POLL_TIMEOUT_US, true, |
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| 137 | + mailbox, mb_offset); |
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| 138 | + if (ret < 0) { |
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| 139 | + /* Response timeout */ |
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| 140 | + dev_err(&GET_DEV(accel_dev), |
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| 141 | + "Failed to send admin msg %d to accelerator %d\n", |
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| 142 | + request->cmd_id, ae); |
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| 143 | + } else { |
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| 144 | + /* Response received from admin message, we can now |
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| 145 | + * make response data available in "out" parameter. |
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| 146 | + */ |
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181 | 147 | memcpy(out, admin->virt_addr + offset + |
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182 | 148 | ADF_ADMINMSG_LEN, ADF_ADMINMSG_LEN); |
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183 | | - else |
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184 | | - dev_err(&GET_DEV(accel_dev), |
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185 | | - "Failed to send admin msg to accelerator\n"); |
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| 149 | + } |
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186 | 150 | |
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187 | 151 | mutex_unlock(&admin->lock); |
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188 | | - return received ? 0 : -EFAULT; |
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| 152 | + return ret; |
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189 | 153 | } |
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190 | 154 | |
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191 | | -static int adf_send_admin_cmd(struct adf_accel_dev *accel_dev, int cmd) |
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| 155 | +static int adf_send_admin(struct adf_accel_dev *accel_dev, |
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| 156 | + struct icp_qat_fw_init_admin_req *req, |
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| 157 | + struct icp_qat_fw_init_admin_resp *resp, |
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| 158 | + const unsigned long ae_mask) |
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192 | 159 | { |
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193 | | - struct adf_hw_device_data *hw_device = accel_dev->hw_device; |
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| 160 | + u32 ae; |
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| 161 | + |
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| 162 | + for_each_set_bit(ae, &ae_mask, ICP_QAT_HW_AE_DELIMITER) |
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| 163 | + if (adf_put_admin_msg_sync(accel_dev, ae, req, resp) || |
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| 164 | + resp->status) |
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| 165 | + return -EFAULT; |
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| 166 | + |
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| 167 | + return 0; |
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| 168 | +} |
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| 169 | + |
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| 170 | +static int adf_init_me(struct adf_accel_dev *accel_dev) |
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| 171 | +{ |
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194 | 172 | struct icp_qat_fw_init_admin_req req; |
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195 | 173 | struct icp_qat_fw_init_admin_resp resp; |
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196 | | - int i; |
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| 174 | + struct adf_hw_device_data *hw_device = accel_dev->hw_device; |
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| 175 | + u32 ae_mask = hw_device->ae_mask; |
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197 | 176 | |
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198 | | - memset(&req, 0, sizeof(struct icp_qat_fw_init_admin_req)); |
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199 | | - req.init_admin_cmd_id = cmd; |
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| 177 | + memset(&req, 0, sizeof(req)); |
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| 178 | + memset(&resp, 0, sizeof(resp)); |
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| 179 | + req.cmd_id = ICP_QAT_FW_INIT_ME; |
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200 | 180 | |
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201 | | - if (cmd == ICP_QAT_FW_CONSTANTS_CFG) { |
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202 | | - req.init_cfg_sz = 1024; |
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203 | | - req.init_cfg_ptr = accel_dev->admin->const_tbl_addr; |
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204 | | - } |
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205 | | - for (i = 0; i < hw_device->get_num_aes(hw_device); i++) { |
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206 | | - memset(&resp, 0, sizeof(struct icp_qat_fw_init_admin_resp)); |
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207 | | - if (adf_put_admin_msg_sync(accel_dev, i, &req, &resp) || |
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208 | | - resp.init_resp_hdr.status) |
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209 | | - return -EFAULT; |
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210 | | - } |
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211 | | - return 0; |
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| 181 | + return adf_send_admin(accel_dev, &req, &resp, ae_mask); |
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| 182 | +} |
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| 183 | + |
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| 184 | +static int adf_set_fw_constants(struct adf_accel_dev *accel_dev) |
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| 185 | +{ |
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| 186 | + struct icp_qat_fw_init_admin_req req; |
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| 187 | + struct icp_qat_fw_init_admin_resp resp; |
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| 188 | + struct adf_hw_device_data *hw_device = accel_dev->hw_device; |
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| 189 | + u32 ae_mask = hw_device->ae_mask; |
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| 190 | + |
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| 191 | + memset(&req, 0, sizeof(req)); |
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| 192 | + memset(&resp, 0, sizeof(resp)); |
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| 193 | + req.cmd_id = ICP_QAT_FW_CONSTANTS_CFG; |
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| 194 | + |
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| 195 | + req.init_cfg_sz = ADF_CONST_TABLE_SIZE; |
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| 196 | + req.init_cfg_ptr = accel_dev->admin->const_tbl_addr; |
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| 197 | + |
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| 198 | + return adf_send_admin(accel_dev, &req, &resp, ae_mask); |
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212 | 199 | } |
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213 | 200 | |
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214 | 201 | /** |
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.. | .. |
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221 | 208 | */ |
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222 | 209 | int adf_send_admin_init(struct adf_accel_dev *accel_dev) |
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223 | 210 | { |
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224 | | - int ret = adf_send_admin_cmd(accel_dev, ICP_QAT_FW_INIT_ME); |
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| 211 | + int ret; |
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225 | 212 | |
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| 213 | + ret = adf_init_me(accel_dev); |
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226 | 214 | if (ret) |
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227 | 215 | return ret; |
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228 | | - return adf_send_admin_cmd(accel_dev, ICP_QAT_FW_CONSTANTS_CFG); |
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| 216 | + |
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| 217 | + return adf_set_fw_constants(accel_dev); |
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229 | 218 | } |
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230 | 219 | EXPORT_SYMBOL_GPL(adf_send_admin_init); |
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231 | 220 | |
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.. | .. |
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244 | 233 | dev_to_node(&GET_DEV(accel_dev))); |
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245 | 234 | if (!admin) |
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246 | 235 | return -ENOMEM; |
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247 | | - admin->virt_addr = dma_zalloc_coherent(&GET_DEV(accel_dev), PAGE_SIZE, |
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248 | | - &admin->phy_addr, GFP_KERNEL); |
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| 236 | + admin->virt_addr = dma_alloc_coherent(&GET_DEV(accel_dev), PAGE_SIZE, |
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| 237 | + &admin->phy_addr, GFP_KERNEL); |
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249 | 238 | if (!admin->virt_addr) { |
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250 | 239 | dev_err(&GET_DEV(accel_dev), "Failed to allocate dma buff\n"); |
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251 | 240 | kfree(admin); |
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252 | 241 | return -ENOMEM; |
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253 | 242 | } |
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254 | 243 | |
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255 | | - admin->virt_tbl_addr = dma_zalloc_coherent(&GET_DEV(accel_dev), |
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256 | | - PAGE_SIZE, |
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257 | | - &admin->const_tbl_addr, |
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258 | | - GFP_KERNEL); |
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| 244 | + admin->virt_tbl_addr = dma_alloc_coherent(&GET_DEV(accel_dev), |
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| 245 | + PAGE_SIZE, |
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| 246 | + &admin->const_tbl_addr, |
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| 247 | + GFP_KERNEL); |
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259 | 248 | if (!admin->virt_tbl_addr) { |
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260 | 249 | dev_err(&GET_DEV(accel_dev), "Failed to allocate const_tbl\n"); |
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261 | 250 | dma_free_coherent(&GET_DEV(accel_dev), PAGE_SIZE, |
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