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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/crypto/ccree/cc_hw_queue_defs.h
....@@ -1,5 +1,5 @@
11 /* SPDX-License-Identifier: GPL-2.0 */
2
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
2
+/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
33 
44 #ifndef __CC_HW_QUEUE_DEFS_H__
55 #define __CC_HW_QUEUE_DEFS_H__
....@@ -17,43 +17,43 @@
1717 /* Define max. available slots in HW queue */
1818 #define HW_QUEUE_SLOTS_MAX              15
1919 
20
-#define CC_REG_LOW(word, name)  \
21
-	(CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT)
20
+#define CC_REG_LOW(name)  (name ## _BIT_SHIFT)
21
+#define CC_REG_HIGH(name) (CC_REG_LOW(name) + name ## _BIT_SIZE - 1)
22
+#define CC_GENMASK(name)  GENMASK(CC_REG_HIGH(name), CC_REG_LOW(name))
2223 
23
-#define CC_REG_HIGH(word, name) \
24
-	(CC_REG_LOW(word, name) + \
25
-	 CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1)
24
+#define CC_HWQ_GENMASK(word, field) \
25
+	CC_GENMASK(CC_DSCRPTR_QUEUE_WORD ## word ## _ ## field)
2626 
27
-#define CC_GENMASK(word, name) \
28
-	GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name))
29
-
30
-#define WORD0_VALUE		CC_GENMASK(0, VALUE)
31
-#define WORD1_DIN_CONST_VALUE	CC_GENMASK(1, DIN_CONST_VALUE)
32
-#define WORD1_DIN_DMA_MODE	CC_GENMASK(1, DIN_DMA_MODE)
33
-#define WORD1_DIN_SIZE		CC_GENMASK(1, DIN_SIZE)
34
-#define WORD1_NOT_LAST		CC_GENMASK(1, NOT_LAST)
35
-#define WORD1_NS_BIT		CC_GENMASK(1, NS_BIT)
36
-#define WORD2_VALUE		CC_GENMASK(2, VALUE)
37
-#define WORD3_DOUT_DMA_MODE	CC_GENMASK(3, DOUT_DMA_MODE)
38
-#define WORD3_DOUT_LAST_IND	CC_GENMASK(3, DOUT_LAST_IND)
39
-#define WORD3_DOUT_SIZE		CC_GENMASK(3, DOUT_SIZE)
40
-#define WORD3_HASH_XOR_BIT	CC_GENMASK(3, HASH_XOR_BIT)
41
-#define WORD3_NS_BIT		CC_GENMASK(3, NS_BIT)
42
-#define WORD3_QUEUE_LAST_IND	CC_GENMASK(3, QUEUE_LAST_IND)
43
-#define WORD4_ACK_NEEDED	CC_GENMASK(4, ACK_NEEDED)
44
-#define WORD4_AES_SEL_N_HASH	CC_GENMASK(4, AES_SEL_N_HASH)
45
-#define WORD4_BYTES_SWAP	CC_GENMASK(4, BYTES_SWAP)
46
-#define WORD4_CIPHER_CONF0	CC_GENMASK(4, CIPHER_CONF0)
47
-#define WORD4_CIPHER_CONF1	CC_GENMASK(4, CIPHER_CONF1)
48
-#define WORD4_CIPHER_CONF2	CC_GENMASK(4, CIPHER_CONF2)
49
-#define WORD4_CIPHER_DO		CC_GENMASK(4, CIPHER_DO)
50
-#define WORD4_CIPHER_MODE	CC_GENMASK(4, CIPHER_MODE)
51
-#define WORD4_CMAC_SIZE0	CC_GENMASK(4, CMAC_SIZE0)
52
-#define WORD4_DATA_FLOW_MODE	CC_GENMASK(4, DATA_FLOW_MODE)
53
-#define WORD4_KEY_SIZE		CC_GENMASK(4, KEY_SIZE)
54
-#define WORD4_SETUP_OPERATION	CC_GENMASK(4, SETUP_OPERATION)
55
-#define WORD5_DIN_ADDR_HIGH	CC_GENMASK(5, DIN_ADDR_HIGH)
56
-#define WORD5_DOUT_ADDR_HIGH	CC_GENMASK(5, DOUT_ADDR_HIGH)
27
+#define WORD0_VALUE		CC_HWQ_GENMASK(0, VALUE)
28
+#define	WORD0_CPP_CIPHER_MODE	CC_HWQ_GENMASK(0, CPP_CIPHER_MODE)
29
+#define WORD1_DIN_CONST_VALUE	CC_HWQ_GENMASK(1, DIN_CONST_VALUE)
30
+#define WORD1_DIN_DMA_MODE	CC_HWQ_GENMASK(1, DIN_DMA_MODE)
31
+#define WORD1_DIN_SIZE		CC_HWQ_GENMASK(1, DIN_SIZE)
32
+#define WORD1_NOT_LAST		CC_HWQ_GENMASK(1, NOT_LAST)
33
+#define WORD1_NS_BIT		CC_HWQ_GENMASK(1, NS_BIT)
34
+#define WORD1_LOCK_QUEUE	CC_HWQ_GENMASK(1, LOCK_QUEUE)
35
+#define WORD2_VALUE		CC_HWQ_GENMASK(2, VALUE)
36
+#define WORD3_DOUT_DMA_MODE	CC_HWQ_GENMASK(3, DOUT_DMA_MODE)
37
+#define WORD3_DOUT_LAST_IND	CC_HWQ_GENMASK(3, DOUT_LAST_IND)
38
+#define WORD3_DOUT_SIZE		CC_HWQ_GENMASK(3, DOUT_SIZE)
39
+#define WORD3_HASH_XOR_BIT	CC_HWQ_GENMASK(3, HASH_XOR_BIT)
40
+#define WORD3_NS_BIT		CC_HWQ_GENMASK(3, NS_BIT)
41
+#define WORD3_QUEUE_LAST_IND	CC_HWQ_GENMASK(3, QUEUE_LAST_IND)
42
+#define WORD4_ACK_NEEDED	CC_HWQ_GENMASK(4, ACK_NEEDED)
43
+#define WORD4_AES_SEL_N_HASH	CC_HWQ_GENMASK(4, AES_SEL_N_HASH)
44
+#define WORD4_AES_XOR_CRYPTO_KEY CC_HWQ_GENMASK(4, AES_XOR_CRYPTO_KEY)
45
+#define WORD4_BYTES_SWAP	CC_HWQ_GENMASK(4, BYTES_SWAP)
46
+#define WORD4_CIPHER_CONF0	CC_HWQ_GENMASK(4, CIPHER_CONF0)
47
+#define WORD4_CIPHER_CONF1	CC_HWQ_GENMASK(4, CIPHER_CONF1)
48
+#define WORD4_CIPHER_CONF2	CC_HWQ_GENMASK(4, CIPHER_CONF2)
49
+#define WORD4_CIPHER_DO		CC_HWQ_GENMASK(4, CIPHER_DO)
50
+#define WORD4_CIPHER_MODE	CC_HWQ_GENMASK(4, CIPHER_MODE)
51
+#define WORD4_CMAC_SIZE0	CC_HWQ_GENMASK(4, CMAC_SIZE0)
52
+#define WORD4_DATA_FLOW_MODE	CC_HWQ_GENMASK(4, DATA_FLOW_MODE)
53
+#define WORD4_KEY_SIZE		CC_HWQ_GENMASK(4, KEY_SIZE)
54
+#define WORD4_SETUP_OPERATION	CC_HWQ_GENMASK(4, SETUP_OPERATION)
55
+#define WORD5_DIN_ADDR_HIGH	CC_HWQ_GENMASK(5, DIN_ADDR_HIGH)
56
+#define WORD5_DOUT_ADDR_HIGH	CC_HWQ_GENMASK(5, DOUT_ADDR_HIGH)
5757 
5858 /******************************************************************************
5959  *				TYPE DEFINITIONS
....@@ -107,6 +107,7 @@
107107 	AES_to_AES_to_HASH_and_DOUT	= 13,
108108 	AES_to_AES_to_HASH	= 14,
109109 	AES_to_HASH_and_AES	= 15,
110
+	DIN_SM4_DOUT		= 16,
110111 	DIN_AES_AESMAC		= 17,
111112 	HASH_to_DOUT		= 18,
112113 	/* setup flows */
....@@ -114,9 +115,11 @@
114115 	S_DIN_to_AES2		= 33,
115116 	S_DIN_to_DES		= 34,
116117 	S_DIN_to_RC4		= 35,
118
+	S_DIN_to_SM4		= 36,
117119 	S_DIN_to_HASH		= 37,
118120 	S_AES_to_DOUT		= 38,
119121 	S_AES2_to_DOUT		= 39,
122
+	S_SM4_to_DOUT		= 40,
120123 	S_RC4_to_DOUT		= 41,
121124 	S_DES_to_DOUT		= 42,
122125 	S_HASH_to_DOUT		= 43,
....@@ -172,6 +175,15 @@
172175 	END_OF_KEYS = S32_MAX,
173176 };
174177 
178
+#define CC_NUM_HW_KEY_SLOTS	4
179
+#define CC_FIRST_HW_KEY_SLOT	0
180
+#define CC_LAST_HW_KEY_SLOT	(CC_FIRST_HW_KEY_SLOT + CC_NUM_HW_KEY_SLOTS - 1)
181
+
182
+#define CC_NUM_CPP_KEY_SLOTS	8
183
+#define CC_FIRST_CPP_KEY_SLOT	16
184
+#define CC_LAST_CPP_KEY_SLOT	(CC_FIRST_CPP_KEY_SLOT + \
185
+					CC_NUM_CPP_KEY_SLOTS - 1)
186
+
175187 enum cc_hw_aes_key_size {
176188 	AES_128_KEY = 0,
177189 	AES_192_KEY = 1,
....@@ -185,35 +197,39 @@
185197 	HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
186198 };
187199 
200
+#define CC_CPP_DIN_ADDR	0xFF00FF00UL
201
+#define CC_CPP_DIN_SIZE 0xFF00FFUL
202
+
188203 /*****************************/
189204 /* Descriptor packing macros */
190205 /*****************************/
191206 
192
-/*
193
- * Init a HW descriptor struct
194
- * @pdesc: pointer HW descriptor struct
207
+/**
208
+ * hw_desc_init() - Init a HW descriptor struct
209
+ * @pdesc: pointer to HW descriptor struct
195210  */
196211 static inline void hw_desc_init(struct cc_hw_desc *pdesc)
197212 {
198213 	memset(pdesc, 0, sizeof(struct cc_hw_desc));
199214 }
200215 
201
-/*
202
- * Indicates the end of current HW descriptors flow and release the HW engines.
216
+/**
217
+ * set_queue_last_ind_bit() - Indicate the end of current HW descriptors flow
218
+ * and release the HW engines.
203219  *
204
- * @pdesc: pointer HW descriptor struct
220
+ * @pdesc: Pointer to HW descriptor struct
205221  */
206222 static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc)
207223 {
208224 	pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
209225 }
210226 
211
-/*
212
- * Set the DIN field of a HW descriptors
227
+/**
228
+ * set_din_type() - Set the DIN field of a HW descriptor
213229  *
214
- * @pdesc: pointer HW descriptor struct
215
- * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
216
- * @addr: dinAdr DIN address
230
+ * @pdesc: Pointer to HW descriptor struct
231
+ * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
232
+ * @addr: DIN address
217233  * @size: Data size in bytes
218234  * @axi_sec: AXI secure bit
219235  */
....@@ -221,20 +237,20 @@
221237 				enum cc_dma_mode dma_mode, dma_addr_t addr,
222238 				u32 size, enum cc_axi_sec axi_sec)
223239 {
224
-	pdesc->word[0] = (u32)addr;
240
+	pdesc->word[0] = lower_32_bits(addr);
225241 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
226
-	pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32)));
242
+	pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr));
227243 #endif
228244 	pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) |
229245 				FIELD_PREP(WORD1_DIN_SIZE, size) |
230246 				FIELD_PREP(WORD1_NS_BIT, axi_sec);
231247 }
232248 
233
-/*
234
- * Set the DIN field of a HW descriptors to NO DMA mode.
249
+/**
250
+ * set_din_no_dma() - Set the DIN field of a HW descriptor to NO DMA mode.
235251  * Used for NOP descriptor, register patches and other special modes.
236252  *
237
- * @pdesc: pointer HW descriptor struct
253
+ * @pdesc: Pointer to HW descriptor struct
238254  * @addr: DIN address
239255  * @size: Data size in bytes
240256  */
....@@ -244,27 +260,42 @@
244260 	pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size);
245261 }
246262 
247
-/*
248
- * Set the DIN field of a HW descriptors to SRAM mode.
249
- * Note: No need to check SRAM alignment since host requests do not use SRAM and
250
- * adaptor will enforce alignment check.
263
+/**
264
+ * set_cpp_crypto_key() - Setup the special CPP descriptor
251265  *
252
- * @pdesc: pointer HW descriptor struct
253
- * @addr: DIN address
254
- * @size Data size in bytes
266
+ * @pdesc: Pointer to HW descriptor struct
267
+ * @slot: Slot number
255268  */
256
-static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr,
257
-				u32 size)
269
+static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, u8 slot)
258270 {
259
-	pdesc->word[0] = (u32)addr;
271
+	pdesc->word[0] |= CC_CPP_DIN_ADDR;
272
+
273
+	pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE);
274
+	pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1);
275
+
276
+	pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot);
277
+}
278
+
279
+/**
280
+ * set_din_sram() - Set the DIN field of a HW descriptor to SRAM mode.
281
+ * Note: No need to check SRAM alignment since host requests do not use SRAM and
282
+ * the adaptor will enforce alignment checks.
283
+ *
284
+ * @pdesc: Pointer to HW descriptor struct
285
+ * @addr: DIN address
286
+ * @size: Data size in bytes
287
+ */
288
+static inline void set_din_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
289
+{
290
+	pdesc->word[0] = addr;
260291 	pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) |
261292 				FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM);
262293 }
263294 
264
-/*
265
- * Set the DIN field of a HW descriptors to CONST mode
295
+/**
296
+ * set_din_const() - Set the DIN field of a HW descriptor to CONST mode
266297  *
267
- * @pdesc: pointer HW descriptor struct
298
+ * @pdesc: Pointer to HW descriptor struct
268299  * @val: DIN const value
269300  * @size: Data size in bytes
270301  */
....@@ -276,20 +307,20 @@
276307 			FIELD_PREP(WORD1_DIN_SIZE, size);
277308 }
278309 
279
-/*
280
- * Set the DIN not last input data indicator
310
+/**
311
+ * set_din_not_last_indication() - Set the DIN not last input data indicator
281312  *
282
- * @pdesc: pointer HW descriptor struct
313
+ * @pdesc: Pointer to HW descriptor struct
283314  */
284315 static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc)
285316 {
286317 	pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1);
287318 }
288319 
289
-/*
290
- * Set the DOUT field of a HW descriptors
320
+/**
321
+ * set_dout_type() - Set the DOUT field of a HW descriptor
291322  *
292
- * @pdesc: pointer HW descriptor struct
323
+ * @pdesc: Pointer to HW descriptor struct
293324  * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
294325  * @addr: DOUT address
295326  * @size: Data size in bytes
....@@ -299,24 +330,24 @@
299330 				 enum cc_dma_mode dma_mode, dma_addr_t addr,
300331 				 u32 size, enum cc_axi_sec axi_sec)
301332 {
302
-	pdesc->word[2] = (u32)addr;
333
+	pdesc->word[2] = lower_32_bits(addr);
303334 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
304
-	pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32)));
335
+	pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, upper_32_bits(addr));
305336 #endif
306337 	pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) |
307338 				FIELD_PREP(WORD3_DOUT_SIZE, size) |
308339 				FIELD_PREP(WORD3_NS_BIT, axi_sec);
309340 }
310341 
311
-/*
312
- * Set the DOUT field of a HW descriptors to DLLI type
342
+/**
343
+ * set_dout_dlli() - Set the DOUT field of a HW descriptor to DLLI type
313344  * The LAST INDICATION is provided by the user
314345  *
315
- * @pdesc pointer HW descriptor struct
346
+ * @pdesc: Pointer to HW descriptor struct
316347  * @addr: DOUT address
317348  * @size: Data size in bytes
318
- * @last_ind: The last indication bit
319349  * @axi_sec: AXI secure bit
350
+ * @last_ind: The last indication bit
320351  */
321352 static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
322353 				 u32 size, enum cc_axi_sec axi_sec,
....@@ -326,29 +357,28 @@
326357 	pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
327358 }
328359 
329
-/*
330
- * Set the DOUT field of a HW descriptors to DLLI type
360
+/**
361
+ * set_dout_mlli() - Set the DOUT field of a HW descriptor to MLLI type
331362  * The LAST INDICATION is provided by the user
332363  *
333
- * @pdesc: pointer HW descriptor struct
364
+ * @pdesc: Pointer to HW descriptor struct
334365  * @addr: DOUT address
335366  * @size: Data size in bytes
336
- * @last_ind: The last indication bit
337367  * @axi_sec: AXI secure bit
368
+ * @last_ind: The last indication bit
338369  */
339
-static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
340
-				 u32 size, enum cc_axi_sec axi_sec,
341
-				 bool last_ind)
370
+static inline void set_dout_mlli(struct cc_hw_desc *pdesc, u32 addr, u32 size,
371
+				 enum cc_axi_sec axi_sec, bool last_ind)
342372 {
343373 	set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec);
344374 	pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
345375 }
346376 
347
-/*
348
- * Set the DOUT field of a HW descriptors to NO DMA mode.
377
+/**
378
+ * set_dout_no_dma() - Set the DOUT field of a HW descriptor to NO DMA mode.
349379  * Used for NOP descriptor, register patches and other special modes.
350380  *
351
- * @pdesc: pointer HW descriptor struct
381
+ * @pdesc: pointer to HW descriptor struct
352382  * @addr: DOUT address
353383  * @size: Data size in bytes
354384  * @write_enable: Enables a write operation to a register
....@@ -361,44 +391,55 @@
361391 			FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable);
362392 }
363393 
364
-/*
365
- * Set the word for the XOR operation.
394
+/**
395
+ * set_xor_val() - Set the word for the XOR operation.
366396  *
367
- * @pdesc: pointer HW descriptor struct
368
- * @val: xor data value
397
+ * @pdesc: Pointer to HW descriptor struct
398
+ * @val: XOR data value
369399  */
370400 static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val)
371401 {
372402 	pdesc->word[2] = val;
373403 }
374404 
375
-/*
376
- * Sets the XOR indicator bit in the descriptor
405
+/**
406
+ * set_xor_active() - Set the XOR indicator bit in the descriptor
377407  *
378
- * @pdesc: pointer HW descriptor struct
408
+ * @pdesc: Pointer to HW descriptor struct
379409  */
380410 static inline void set_xor_active(struct cc_hw_desc *pdesc)
381411 {
382412 	pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1);
383413 }
384414 
385
-/*
386
- * Select the AES engine instead of HASH engine when setting up combined mode
387
- * with AES XCBC MAC
415
+/**
416
+ * set_aes_not_hash_mode() - Select the AES engine instead of HASH engine when
417
+ * setting up combined mode with AES XCBC MAC
388418  *
389
- * @pdesc: pointer HW descriptor struct
419
+ * @pdesc: Pointer to HW descriptor struct
390420  */
391421 static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc)
392422 {
393423 	pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1);
394424 }
395425 
396
-/*
397
- * Set the DOUT field of a HW descriptors to SRAM mode
398
- * Note: No need to check SRAM alignment since host requests do not use SRAM and
399
- * adaptor will enforce alignment check.
426
+/**
427
+ * set_aes_xor_crypto_key() - Set aes xor crypto key, which in some scenarios
428
+ * selects the SM3 engine
400429  *
401
- * @pdesc: pointer HW descriptor struct
430
+ * @pdesc: Pointer to HW descriptor struct
431
+ */
432
+static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc)
433
+{
434
+	pdesc->word[4] |= FIELD_PREP(WORD4_AES_XOR_CRYPTO_KEY, 1);
435
+}
436
+
437
+/**
438
+ * set_dout_sram() - Set the DOUT field of a HW descriptor to SRAM mode
439
+ * Note: No need to check SRAM alignment since host requests do not use SRAM and
440
+ * the adaptor will enforce alignment checks.
441
+ *
442
+ * @pdesc: Pointer to HW descriptor struct
402443  * @addr: DOUT address
403444  * @size: Data size in bytes
404445  */
....@@ -409,32 +450,34 @@
409450 			FIELD_PREP(WORD3_DOUT_SIZE, size);
410451 }
411452 
412
-/*
413
- * Sets the data unit size for XEX mode in data_out_addr[15:0]
453
+/**
454
+ * set_xex_data_unit_size() - Set the data unit size for XEX mode in
455
+ * data_out_addr[15:0]
414456  *
415
- * @pdesc: pDesc pointer HW descriptor struct
416
- * @size: data unit size for XEX mode
457
+ * @pdesc: Pointer to HW descriptor struct
458
+ * @size: Data unit size for XEX mode
417459  */
418460 static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size)
419461 {
420462 	pdesc->word[2] = size;
421463 }
422464 
423
-/*
424
- * Set the number of rounds for Multi2 in data_out_addr[15:0]
465
+/**
466
+ * set_multi2_num_rounds() - Set the number of rounds for Multi2 in
467
+ * data_out_addr[15:0]
425468  *
426
- * @pdesc: pointer HW descriptor struct
427
- * @num: number of rounds for Multi2
469
+ * @pdesc: Pointer to HW descriptor struct
470
+ * @num: Number of rounds for Multi2
428471  */
429472 static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num)
430473 {
431474 	pdesc->word[2] = num;
432475 }
433476 
434
-/*
435
- * Set the flow mode.
477
+/**
478
+ * set_flow_mode() - Set the flow mode.
436479  *
437
- * @pdesc: pointer HW descriptor struct
480
+ * @pdesc: Pointer to HW descriptor struct
438481  * @mode: Any one of the modes defined in [CC7x-DESC]
439482  */
440483 static inline void set_flow_mode(struct cc_hw_desc *pdesc,
....@@ -443,21 +486,37 @@
443486 	pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode);
444487 }
445488 
446
-/*
447
- * Set the cipher mode.
489
+/**
490
+ * set_cipher_mode() - Set the cipher mode.
448491  *
449
- * @pdesc: pointer HW descriptor struct
450
- * @mode:  Any one of the modes defined in [CC7x-DESC]
492
+ * @pdesc: Pointer to HW descriptor struct
493
+ * @mode: Any one of the modes defined in [CC7x-DESC]
451494  */
452495 static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode)
453496 {
454497 	pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode);
455498 }
456499 
457
-/*
458
- * Set the cipher configuration fields.
500
+/**
501
+ * set_hash_cipher_mode() - Set the cipher mode for hash algorithms.
459502  *
460
- * @pdesc: pointer HW descriptor struct
503
+ * @pdesc: Pointer to HW descriptor struct
504
+ * @cipher_mode: Any one of the modes defined in [CC7x-DESC]
505
+ * @hash_mode: specifies which hash is being handled
506
+ */
507
+static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc,
508
+					enum drv_cipher_mode cipher_mode,
509
+					enum drv_hash_mode hash_mode)
510
+{
511
+	set_cipher_mode(pdesc, cipher_mode);
512
+	if (hash_mode == DRV_HASH_SM3)
513
+		set_aes_xor_crypto_key(pdesc);
514
+}
515
+
516
+/**
517
+ * set_cipher_config0() - Set the cipher configuration fields.
518
+ *
519
+ * @pdesc: Pointer to HW descriptor struct
461520  * @mode: Any one of the modes defined in [CC7x-DESC]
462521  */
463522 static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode)
....@@ -465,11 +524,11 @@
465524 	pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode);
466525 }
467526 
468
-/*
469
- * Set the cipher configuration fields.
527
+/**
528
+ * set_cipher_config1() - Set the cipher configuration fields.
470529  *
471
- * @pdesc: pointer HW descriptor struct
472
- * @config: Any one of the modes defined in [CC7x-DESC]
530
+ * @pdesc: Pointer to HW descriptor struct
531
+ * @config: Padding mode
473532  */
474533 static inline void set_cipher_config1(struct cc_hw_desc *pdesc,
475534 				      enum cc_hash_conf_pad config)
....@@ -477,10 +536,10 @@
477536 	pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config);
478537 }
479538 
480
-/*
481
- * Set HW key configuration fields.
539
+/**
540
+ * set_hw_crypto_key() - Set HW key configuration fields.
482541  *
483
- * @pdesc: pointer HW descriptor struct
542
+ * @pdesc: Pointer to HW descriptor struct
484543  * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key
485544  */
486545 static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc,
....@@ -492,64 +551,64 @@
492551 				   (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2));
493552 }
494553 
495
-/*
496
- * Set byte order of all setup-finalize descriptors.
554
+/**
555
+ * set_bytes_swap() - Set byte order of all setup-finalize descriptors.
497556  *
498
- * @pdesc: pointer HW descriptor struct
499
- * @config: Any one of the modes defined in [CC7x-DESC]
557
+ * @pdesc: Pointer to HW descriptor struct
558
+ * @config: True to enable byte swapping
500559  */
501560 static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config)
502561 {
503562 	pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config);
504563 }
505564 
506
-/*
507
- * Set CMAC_SIZE0 mode.
565
+/**
566
+ * set_cmac_size0_mode() - Set CMAC_SIZE0 mode.
508567  *
509
- * @pdesc: pointer HW descriptor struct
568
+ * @pdesc: Pointer to HW descriptor struct
510569  */
511570 static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc)
512571 {
513572 	pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1);
514573 }
515574 
516
-/*
517
- * Set key size descriptor field.
575
+/**
576
+ * set_key_size() - Set key size descriptor field.
518577  *
519
- * @pdesc: pointer HW descriptor struct
520
- * @size: key size in bytes (NOT size code)
578
+ * @pdesc: Pointer to HW descriptor struct
579
+ * @size: Key size in bytes (NOT size code)
521580  */
522581 static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size)
523582 {
524583 	pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size);
525584 }
526585 
527
-/*
528
- * Set AES key size.
586
+/**
587
+ * set_key_size_aes() - Set AES key size.
529588  *
530
- * @pdesc: pointer HW descriptor struct
531
- * @size: key size in bytes (NOT size code)
589
+ * @pdesc: Pointer to HW descriptor struct
590
+ * @size: Key size in bytes (NOT size code)
532591  */
533592 static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size)
534593 {
535594 	set_key_size(pdesc, ((size >> 3) - 2));
536595 }
537596 
538
-/*
539
- * Set DES key size.
597
+/**
598
+ * set_key_size_des() - Set DES key size.
540599  *
541
- * @pdesc: pointer HW descriptor struct
542
- * @size: key size in bytes (NOT size code)
600
+ * @pdesc: Pointer to HW descriptor struct
601
+ * @size: Key size in bytes (NOT size code)
543602  */
544603 static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size)
545604 {
546605 	set_key_size(pdesc, ((size >> 3) - 1));
547606 }
548607 
549
-/*
550
- * Set the descriptor setup mode
608
+/**
609
+ * set_setup_mode() - Set the descriptor setup mode
551610  *
552
- * @pdesc: pointer HW descriptor struct
611
+ * @pdesc: Pointer to HW descriptor struct
553612  * @mode: Any one of the setup modes defined in [CC7x-DESC]
554613  */
555614 static inline void set_setup_mode(struct cc_hw_desc *pdesc,
....@@ -558,10 +617,10 @@
558617 	pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode);
559618 }
560619 
561
-/*
562
- * Set the descriptor cipher DO
620
+/**
621
+ * set_cipher_do() - Set the descriptor cipher DO
563622  *
564
- * @pdesc: pointer HW descriptor struct
623
+ * @pdesc: Pointer to HW descriptor struct
565624  * @config: Any one of the cipher do defined in [CC7x-DESC]
566625  */
567626 static inline void set_cipher_do(struct cc_hw_desc *pdesc,