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hc
2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/crypto/ccree/cc_host_regs.h
....@@ -1,5 +1,5 @@
11 /* SPDX-License-Identifier: GPL-2.0 */
2
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
2
+/* Copyright (C) 2012-2019 ARM Limited or its affiliates. */
33 
44 #ifndef __CC_HOST_H__
55 #define __CC_HOST_H__
....@@ -7,33 +7,102 @@
77 // --------------------------------------
88 // BLOCK: HOST_P
99 // --------------------------------------
10
+
11
+
12
+/* IRR */
1013 #define CC_HOST_IRR_REG_OFFSET	0xA00UL
14
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SHIFT	0x1UL
15
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_0_INT_BIT_SIZE	0x1UL
1116 #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT	0x2UL
1217 #define CC_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE	0x1UL
18
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SHIFT	0x3UL
19
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_1_INT_BIT_SIZE	0x1UL
20
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SHIFT	0x4UL
21
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_2_INT_BIT_SIZE	0x1UL
22
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SHIFT	0x5UL
23
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_3_INT_BIT_SIZE	0x1UL
24
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SHIFT	0x6UL
25
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_4_INT_BIT_SIZE	0x1UL
26
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SHIFT	0x7UL
27
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_5_INT_BIT_SIZE	0x1UL
1328 #define CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT	0x8UL
1429 #define CC_HOST_IRR_AXI_ERR_INT_BIT_SIZE	0x1UL
30
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SHIFT	0x9UL
31
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_6_INT_BIT_SIZE	0x1UL
32
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SHIFT	0xAUL
33
+#define CC_HOST_IRR_REE_OP_ABORTED_AES_7_INT_BIT_SIZE	0x1UL
1534 #define CC_HOST_IRR_GPR0_BIT_SHIFT	0xBUL
1635 #define CC_HOST_IRR_GPR0_BIT_SIZE	0x1UL
36
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SHIFT	0xCUL
37
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_0_INT_BIT_SIZE	0x1UL
38
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SHIFT	0xDUL
39
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_1_INT_BIT_SIZE	0x1UL
40
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SHIFT	0xEUL
41
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_2_INT_BIT_SIZE	0x1UL
42
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SHIFT	0xFUL
43
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_3_INT_BIT_SIZE	0x1UL
44
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SHIFT	0x10UL
45
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_4_INT_BIT_SIZE	0x1UL
46
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SHIFT	0x11UL
47
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_5_INT_BIT_SIZE	0x1UL
48
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SHIFT	0x12UL
49
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_6_INT_BIT_SIZE	0x1UL
1750 #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT	0x13UL
1851 #define CC_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE	0x1UL
52
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SHIFT	0x14UL
53
+#define CC_HOST_IRR_REE_OP_ABORTED_SM_7_INT_BIT_SIZE	0x1UL
1954 #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT	0x17UL
2055 #define CC_HOST_IRR_AXIM_COMP_INT_BIT_SIZE	0x1UL
2156 #define CC_HOST_SEP_SRAM_THRESHOLD_REG_OFFSET	0xA10UL
2257 #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SHIFT	0x0UL
2358 #define CC_HOST_SEP_SRAM_THRESHOLD_VALUE_BIT_SIZE	0xCUL
24
-#define CC_HOST_IMR_REG_OFFSET	0xA04UL
25
-#define CC_HOST_IMR_NOT_USED_MASK_BIT_SHIFT	0x1UL
26
-#define CC_HOST_IMR_NOT_USED_MASK_BIT_SIZE	0x1UL
59
+
60
+/* IMR */
61
+#define CC_HOST_IMR_REG_OFFSET	0x0A04UL
62
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT	0x1UL
63
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SIZE	0x1UL
2764 #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT	0x2UL
2865 #define CC_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE	0x1UL
66
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT	0x3UL
67
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SIZE	0x1UL
68
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT	0x4UL
69
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SIZE	0x1UL
70
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT	0x5UL
71
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SIZE	0x1UL
72
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT	0x6UL
73
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SIZE	0x1UL
74
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT	0x7UL
75
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SIZE	0x1UL
2976 #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT	0x8UL
3077 #define CC_HOST_IMR_AXI_ERR_MASK_BIT_SIZE	0x1UL
78
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT	0x9UL
79
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SIZE	0x1UL
80
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT	0xAUL
81
+#define CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SIZE	0x1UL
3182 #define CC_HOST_IMR_GPR0_BIT_SHIFT	0xBUL
3283 #define CC_HOST_IMR_GPR0_BIT_SIZE	0x1UL
84
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT	0xCUL
85
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SIZE	0x1UL
86
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT	0xDUL
87
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SIZE	0x1UL
88
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT	0xEUL
89
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SIZE	0x1UL
90
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT	0xFUL
91
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SIZE	0x1UL
92
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT	0x10UL
93
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SIZE	0x1UL
94
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT	0x11UL
95
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SIZE	0x1UL
96
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT	0x12UL
97
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SIZE	0x1UL
3398 #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT	0x13UL
3499 #define CC_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE	0x1UL
100
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT	0x14UL
101
+#define CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SIZE	0x1UL
35102 #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT	0x17UL
36103 #define CC_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE	0x1UL
104
+
105
+/* ICR */
37106 #define CC_HOST_ICR_REG_OFFSET	0xA08UL
38107 #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT	0x2UL
39108 #define CC_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE	0x1UL
....@@ -45,6 +114,12 @@
45114 #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE	0x1UL
46115 #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT	0x17UL
47116 #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE	0x1UL
117
+#define CC_NVM_IS_IDLE_REG_OFFSET       0x0A10UL
118
+#define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT  0x0UL
119
+#define CC_NVM_IS_IDLE_VALUE_BIT_SIZE   0x1UL
120
+#define CC_SECURITY_DISABLED_REG_OFFSET		0x0A1CUL
121
+#define CC_SECURITY_DISABLED_VALUE_BIT_SHIFT	0x0UL
122
+#define CC_SECURITY_DISABLED_VALUE_BIT_SIZE	0x1UL
48123 #define CC_HOST_SIGNATURE_712_REG_OFFSET	0xA24UL
49124 #define CC_HOST_SIGNATURE_630_REG_OFFSET	0xAC8UL
50125 #define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT	0x0UL
....@@ -131,6 +206,66 @@
131206 #define CC_HOST_POWER_DOWN_EN_REG_OFFSET	0xA78UL
132207 #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT	0x0UL
133208 #define CC_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE	0x1UL
209
+#define CC_HOST_REMOVE_INPUT_PINS_REG_OFFSET	0x0A7CUL
210
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SHIFT	0x0UL
211
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_ENGINE_BIT_SIZE	0x1UL
212
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SHIFT	0x1UL
213
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_AES_MAC_ENGINE_BIT_SIZE	0x1UL
214
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SHIFT	0x2UL
215
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_GHASH_ENGINE_BIT_SIZE	0x1UL
216
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SHIFT	0x3UL
217
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_DES_ENGINE_BIT_SIZE	0x1UL
218
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SHIFT	0x4UL
219
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_HASH_ENGINE_BIT_SIZE	0x1UL
220
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SHIFT	0x5UL
221
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM3_ENGINE_BIT_SIZE	0x1UL
222
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SHIFT	0x6UL
223
+#define CC_HOST_REMOVE_INPUT_PINS_REMOVE_SM4_ENGINE_BIT_SIZE	0x1UL
224
+#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SHIFT	0x7UL
225
+#define CC_HOST_REMOVE_INPUT_PINS_OTP_DISCONNECTED_BIT_SIZE	0x1UL
226
+// --------------------------------------
227
+// BLOCK: ID_REGISTERS
228
+// --------------------------------------
229
+#define CC_PERIPHERAL_ID_4_REG_OFFSET	0x0FD0UL
230
+#define CC_PERIPHERAL_ID_4_VALUE_BIT_SHIFT	0x0UL
231
+#define CC_PERIPHERAL_ID_4_VALUE_BIT_SIZE	0x4UL
232
+#define CC_PIDRESERVED0_REG_OFFSET	0x0FD4UL
233
+#define CC_PIDRESERVED1_REG_OFFSET	0x0FD8UL
234
+#define CC_PIDRESERVED2_REG_OFFSET	0x0FDCUL
235
+#define CC_PERIPHERAL_ID_0_REG_OFFSET	0x0FE0UL
236
+#define CC_PERIPHERAL_ID_0_VALUE_BIT_SHIFT	0x0UL
237
+#define CC_PERIPHERAL_ID_0_VALUE_BIT_SIZE	0x8UL
238
+#define CC_PERIPHERAL_ID_1_REG_OFFSET	0x0FE4UL
239
+#define CC_PERIPHERAL_ID_1_PART_1_BIT_SHIFT	0x0UL
240
+#define CC_PERIPHERAL_ID_1_PART_1_BIT_SIZE	0x4UL
241
+#define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SHIFT	0x4UL
242
+#define CC_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SIZE	0x4UL
243
+#define CC_PERIPHERAL_ID_2_REG_OFFSET	0x0FE8UL
244
+#define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SHIFT	0x0UL
245
+#define CC_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SIZE	0x3UL
246
+#define CC_PERIPHERAL_ID_2_JEDEC_BIT_SHIFT	0x3UL
247
+#define CC_PERIPHERAL_ID_2_JEDEC_BIT_SIZE	0x1UL
248
+#define CC_PERIPHERAL_ID_2_REVISION_BIT_SHIFT	0x4UL
249
+#define CC_PERIPHERAL_ID_2_REVISION_BIT_SIZE	0x4UL
250
+#define CC_PERIPHERAL_ID_3_REG_OFFSET	0x0FECUL
251
+#define CC_PERIPHERAL_ID_3_CMOD_BIT_SHIFT	0x0UL
252
+#define CC_PERIPHERAL_ID_3_CMOD_BIT_SIZE	0x4UL
253
+#define CC_PERIPHERAL_ID_3_REVAND_BIT_SHIFT	0x4UL
254
+#define CC_PERIPHERAL_ID_3_REVAND_BIT_SIZE	0x4UL
255
+#define CC_COMPONENT_ID_0_REG_OFFSET	0x0FF0UL
256
+#define CC_COMPONENT_ID_0_VALUE_BIT_SHIFT	0x0UL
257
+#define CC_COMPONENT_ID_0_VALUE_BIT_SIZE	0x8UL
258
+#define CC_COMPONENT_ID_1_REG_OFFSET	0x0FF4UL
259
+#define CC_COMPONENT_ID_1_PRMBL_1_BIT_SHIFT	0x0UL
260
+#define CC_COMPONENT_ID_1_PRMBL_1_BIT_SIZE	0x4UL
261
+#define CC_COMPONENT_ID_1_CLASS_BIT_SHIFT	0x4UL
262
+#define CC_COMPONENT_ID_1_CLASS_BIT_SIZE	0x4UL
263
+#define CC_COMPONENT_ID_2_REG_OFFSET	0x0FF8UL
264
+#define CC_COMPONENT_ID_2_VALUE_BIT_SHIFT	0x0UL
265
+#define CC_COMPONENT_ID_2_VALUE_BIT_SIZE	0x8UL
266
+#define CC_COMPONENT_ID_3_REG_OFFSET	0x0FFCUL
267
+#define CC_COMPONENT_ID_3_VALUE_BIT_SHIFT	0x0UL
268
+#define CC_COMPONENT_ID_3_VALUE_BIT_SIZE	0x8UL
134269 // --------------------------------------
135270 // BLOCK: HOST_SRAM
136271 // --------------------------------------