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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/crypto/ccree/cc_driver.h
....@@ -1,5 +1,5 @@
11 /* SPDX-License-Identifier: GPL-2.0 */
2
-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
2
+/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
33 
44 /* \file cc_driver.h
55  * ARM CryptoCell Linux Crypto Driver
....@@ -26,9 +26,7 @@
2626 #include <linux/clk.h>
2727 #include <linux/platform_device.h>
2828 
29
-/* Registers definitions from shared/hw/ree_include */
3029 #include "cc_host_regs.h"
31
-#define CC_DEV_SHA_MAX 512
3230 #include "cc_crypto_ctx.h"
3331 #include "cc_hw_queue_defs.h"
3432 #include "cc_sram_mgr.h"
....@@ -36,15 +34,25 @@
3634 extern bool cc_dump_desc;
3735 extern bool cc_dump_bytes;
3836 
39
-#define DRV_MODULE_VERSION "4.0"
37
+#define DRV_MODULE_VERSION "5.0"
4038 
4139 enum cc_hw_rev {
4240 	CC_HW_REV_630 = 630,
4341 	CC_HW_REV_710 = 710,
44
-	CC_HW_REV_712 = 712
42
+	CC_HW_REV_712 = 712,
43
+	CC_HW_REV_713 = 713
44
+};
45
+
46
+enum cc_std_body {
47
+	CC_STD_NIST = 0x1,
48
+	CC_STD_OSCCA = 0x2,
49
+	CC_STD_ALL = 0x3
4550 };
4651 
4752 #define CC_COHERENT_CACHE_PARAMS 0xEEE
53
+
54
+#define CC_PINS_FULL	0x0
55
+#define CC_PINS_SLIM	0x9F
4856 
4957 /* Maximum DMA mask supported by IP */
5058 #define DMA_BIT_MASK_LEN 48
....@@ -58,9 +66,31 @@
5866 
5967 #define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
6068 
61
-#define AXIM_MON_COMP_VALUE GENMASK(CC_AXIM_MON_COMP_VALUE_BIT_SIZE + \
62
-				    CC_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
63
-				    CC_AXIM_MON_COMP_VALUE_BIT_SHIFT)
69
+#define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT)
70
+
71
+#define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)
72
+
73
+#define AXIM_MON_COMP_VALUE CC_GENMASK(CC_AXIM_MON_COMP_VALUE)
74
+
75
+#define CC_CPP_AES_ABORT_MASK ( \
76
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \
77
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \
78
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \
79
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \
80
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \
81
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \
82
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \
83
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT))
84
+
85
+#define CC_CPP_SM4_ABORT_MASK ( \
86
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \
87
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \
88
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \
89
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \
90
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \
91
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \
92
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \
93
+	BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT))
6494 
6595 /* Register name mangling macro */
6696 #define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
....@@ -74,7 +104,6 @@
74104 
75105 #define MAX_REQUEST_QUEUE_SIZE 4096
76106 #define MAX_MLLI_BUFF_SIZE 2080
77
-#define MAX_ICV_NENTS_SUPPORTED 2
78107 
79108 /* Definitions for HW descriptors DIN/DOUT fields */
80109 #define NS_BIT 1
....@@ -83,55 +112,49 @@
83112  * field in the HW descriptor. The DMA engine +8 that value.
84113  */
85114 
115
+struct cc_cpp_req {
116
+	bool is_cpp;
117
+	enum cc_cpp_alg alg;
118
+	u8 slot;
119
+};
120
+
86121 #define CC_MAX_IVGEN_DMA_ADDRESSES	3
87122 struct cc_crypto_req {
88123 	void (*user_cb)(struct device *dev, void *req, int err);
89124 	void *user_arg;
90
-	dma_addr_t ivgen_dma_addr[CC_MAX_IVGEN_DMA_ADDRESSES];
91
-	/* For the first 'ivgen_dma_addr_len' addresses of this array,
92
-	 * generated IV would be placed in it by send_request().
93
-	 * Same generated IV for all addresses!
94
-	 */
95
-	/* Amount of 'ivgen_dma_addr' elements to be filled. */
96
-	unsigned int ivgen_dma_addr_len;
97
-	/* The generated IV size required, 8/16 B allowed. */
98
-	unsigned int ivgen_size;
99125 	struct completion seq_compl; /* request completion */
126
+	struct cc_cpp_req cpp;
100127 };
101128 
102129 /**
103130  * struct cc_drvdata - driver private data context
104131  * @cc_base:	virt address of the CC registers
105
- * @irq:	device IRQ number
106
- * @irq_mask:	Interrupt mask shadow (1 for masked interrupts)
107
- * @fw_ver:	SeP loaded firmware version
132
+ * @irq:	bitmap indicating source of last interrupt
108133  */
109134 struct cc_drvdata {
110135 	void __iomem *cc_base;
111136 	int irq;
112
-	u32 irq_mask;
113
-	u32 fw_ver;
114137 	struct completion hw_queue_avail; /* wait for HW queue availability */
115138 	struct platform_device *plat_dev;
116
-	cc_sram_addr_t mlli_sram_addr;
117
-	void *buff_mgr_handle;
118
-	void *cipher_handle;
139
+	u32 mlli_sram_addr;
140
+	struct dma_pool *mlli_buffs_pool;
141
+	struct list_head alg_list;
119142 	void *hash_handle;
120143 	void *aead_handle;
121144 	void *request_mgr_handle;
122145 	void *fips_handle;
123
-	void *ivgen_handle;
124
-	void *sram_mgr_handle;
125
-	void *debugfs;
146
+	u32 sram_free_offset;	/* offset to non-allocated area in SRAM */
147
+	struct dentry *dir;	/* for debugfs */
126148 	struct clk *clk;
127149 	bool coherent;
128150 	char *hw_rev_name;
129151 	enum cc_hw_rev hw_rev;
130
-	u32 hash_len_sz;
131152 	u32 axim_mon_offset;
132153 	u32 sig_offset;
133154 	u32 ver_offset;
134
-	bool pm_on;
155
+	int std_bodies;
156
+	bool sec_disabled;
157
+	u32 comp_mask;
135158 };
136159 
137160 struct cc_crypto_alg {
....@@ -139,7 +162,6 @@
139162 	int cipher_mode;
140163 	int flow_mode; /* Note: currently, refers to the cipher mode only. */
141164 	int auth_mode;
142
-	unsigned int data_unit;
143165 	struct cc_drvdata *drvdata;
144166 	struct skcipher_alg skcipher_alg;
145167 	struct aead_alg aead_alg;
....@@ -157,6 +179,8 @@
157179 	int flow_mode; /* Note: currently, refers to the cipher mode only. */
158180 	int auth_mode;
159181 	u32 min_hw_rev;
182
+	enum cc_std_body std_body;
183
+	bool sec_func;
160184 	unsigned int data_unit;
161185 	struct cc_drvdata *drvdata;
162186 };
....@@ -180,10 +204,10 @@
180204 		__dump_byte_array(name, the_array, size);
181205 }
182206 
207
+bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
183208 int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
184209 void fini_cc_regs(struct cc_drvdata *drvdata);
185
-int cc_clk_on(struct cc_drvdata *drvdata);
186
-void cc_clk_off(struct cc_drvdata *drvdata);
210
+unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
187211 
188212 static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
189213 {