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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/crypto/ccree/cc_crypto_ctx.h
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@@ -1,5 +1,5 @@
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 /* SPDX-License-Identifier: GPL-2.0 */
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-/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
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+/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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 #ifndef _CC_CRYPTO_CTX_H_
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 #define _CC_CRYPTO_CTX_H_
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@@ -55,6 +55,14 @@
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 #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX
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+#define CC_CPP_NUM_SLOTS	8
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+#define CC_CPP_NUM_ALGS		2
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+
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+enum cc_cpp_alg {
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+	CC_CPP_SM4 = 1,
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+	CC_CPP_AES = 0
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+};
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+
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 enum drv_engine_type {
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 	DRV_ENGINE_NULL = 0,
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 	DRV_ENGINE_AES = 1,
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@@ -100,7 +108,6 @@
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 	DRV_CIPHER_CBC_CTS = 11,
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 	DRV_CIPHER_GCTR = 12,
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 	DRV_CIPHER_ESSIV = 13,
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-	DRV_CIPHER_BITLOCKER = 14,
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 	DRV_CIPHER_RESERVE32B = S32_MAX
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 };
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@@ -115,7 +122,8 @@
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 	DRV_HASH_CBC_MAC = 6,
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 	DRV_HASH_XCBC_MAC = 7,
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 	DRV_HASH_CMAC = 8,
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-	DRV_HASH_MODE_NUM = 9,
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+	DRV_HASH_SM3 = 9,
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+	DRV_HASH_MODE_NUM = 10,
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 	DRV_HASH_RESERVE32B = S32_MAX
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 };
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@@ -127,6 +135,7 @@
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 	DRV_HASH_HW_SHA512 = 4,
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 	DRV_HASH_HW_SHA384 = 12,
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 	DRV_HASH_HW_GHASH = 6,
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+	DRV_HASH_HW_SM3 = 14,
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 	DRV_HASH_HW_RESERVE32B = S32_MAX
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 };
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