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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/crypto/atmel-sha.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Cryptographic API.
34  *
....@@ -5,10 +6,6 @@
56  *
67  * Copyright (c) 2012 Eukréa Electromatique - ATMEL
78  * Author: Nicolas Royer <nicolas@eukrea.com>
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License version 2 as published
11
- * by the Free Software Foundation.
129  *
1310  * Some ideas are from omap-sham.c drivers.
1411  */
....@@ -24,6 +21,7 @@
2421 #include <linux/platform_device.h>
2522 
2623 #include <linux/device.h>
24
+#include <linux/dmaengine.h>
2725 #include <linux/init.h>
2826 #include <linux/errno.h>
2927 #include <linux/interrupt.h>
....@@ -33,15 +31,15 @@
3331 #include <linux/of_device.h>
3432 #include <linux/delay.h>
3533 #include <linux/crypto.h>
36
-#include <linux/cryptohash.h>
3734 #include <crypto/scatterwalk.h>
3835 #include <crypto/algapi.h>
3936 #include <crypto/sha.h>
4037 #include <crypto/hash.h>
4138 #include <crypto/internal/hash.h>
42
-#include <linux/platform_data/crypto-atmel.h>
4339 #include "atmel-sha-regs.h"
4440 #include "atmel-authenc.h"
41
+
42
+#define ATMEL_SHA_PRIORITY	300
4543 
4644 /* SHA flags */
4745 #define SHA_FLAGS_BUSY			BIT(0)
....@@ -137,7 +135,6 @@
137135 	void __iomem		*io_base;
138136 
139137 	spinlock_t		lock;
140
-	int			err;
141138 	struct tasklet_struct	done_task;
142139 	struct tasklet_struct	queue_task;
143140 
....@@ -363,7 +360,7 @@
363360 static void atmel_sha_fill_padding(struct atmel_sha_reqctx *ctx, int length)
364361 {
365362 	unsigned int index, padlen;
366
-	u64 bits[2];
363
+	__be64 bits[2];
367364 	u64 size[2];
368365 
369366 	size[0] = ctx->digcnt[0];
....@@ -854,7 +851,7 @@
854851 								0, final);
855852 }
856853 
857
-static int atmel_sha_update_dma_stop(struct atmel_sha_dev *dd)
854
+static void atmel_sha_update_dma_stop(struct atmel_sha_dev *dd)
858855 {
859856 	struct atmel_sha_reqctx *ctx = ahash_request_ctx(dd->req);
860857 
....@@ -873,8 +870,6 @@
873870 		dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen +
874871 						ctx->block_size, DMA_TO_DEVICE);
875872 	}
876
-
877
-	return 0;
878873 }
879874 
880875 static int atmel_sha_update_req(struct atmel_sha_dev *dd)
....@@ -1028,7 +1023,6 @@
10281023 	if (!(SHA_FLAGS_INIT & dd->flags)) {
10291024 		atmel_sha_write(dd, SHA_CR, SHA_CR_SWRST);
10301025 		dd->flags |= SHA_FLAGS_INIT;
1031
-		dd->err = 0;
10321026 	}
10331027 
10341028 	return 0;
....@@ -1039,9 +1033,13 @@
10391033 	return atmel_sha_read(dd, SHA_HW_VERSION) & 0x00000fff;
10401034 }
10411035 
1042
-static void atmel_sha_hw_version_init(struct atmel_sha_dev *dd)
1036
+static int atmel_sha_hw_version_init(struct atmel_sha_dev *dd)
10431037 {
1044
-	atmel_sha_hw_init(dd);
1038
+	int err;
1039
+
1040
+	err = atmel_sha_hw_init(dd);
1041
+	if (err)
1042
+		return err;
10451043 
10461044 	dd->hw_version = atmel_sha_get_version(dd);
10471045 
....@@ -1049,6 +1047,8 @@
10491047 			"version: 0x%x\n", dd->hw_version);
10501048 
10511049 	clk_disable(dd->iclk);
1050
+
1051
+	return 0;
10521052 }
10531053 
10541054 static int atmel_sha_handle_queue(struct atmel_sha_dev *dd,
....@@ -1251,130 +1251,66 @@
12511251 	return 0;
12521252 }
12531253 
1254
+static void atmel_sha_alg_init(struct ahash_alg *alg)
1255
+{
1256
+	alg->halg.base.cra_priority = ATMEL_SHA_PRIORITY;
1257
+	alg->halg.base.cra_flags = CRYPTO_ALG_ASYNC;
1258
+	alg->halg.base.cra_ctxsize = sizeof(struct atmel_sha_ctx);
1259
+	alg->halg.base.cra_module = THIS_MODULE;
1260
+	alg->halg.base.cra_init = atmel_sha_cra_init;
1261
+
1262
+	alg->halg.statesize = sizeof(struct atmel_sha_reqctx);
1263
+
1264
+	alg->init = atmel_sha_init;
1265
+	alg->update = atmel_sha_update;
1266
+	alg->final = atmel_sha_final;
1267
+	alg->finup = atmel_sha_finup;
1268
+	alg->digest = atmel_sha_digest;
1269
+	alg->export = atmel_sha_export;
1270
+	alg->import = atmel_sha_import;
1271
+}
1272
+
12541273 static struct ahash_alg sha_1_256_algs[] = {
12551274 {
1256
-	.init		= atmel_sha_init,
1257
-	.update		= atmel_sha_update,
1258
-	.final		= atmel_sha_final,
1259
-	.finup		= atmel_sha_finup,
1260
-	.digest		= atmel_sha_digest,
1261
-	.export		= atmel_sha_export,
1262
-	.import		= atmel_sha_import,
1263
-	.halg = {
1264
-		.digestsize	= SHA1_DIGEST_SIZE,
1265
-		.statesize	= sizeof(struct atmel_sha_reqctx),
1266
-		.base	= {
1267
-			.cra_name		= "sha1",
1268
-			.cra_driver_name	= "atmel-sha1",
1269
-			.cra_priority		= 100,
1270
-			.cra_flags		= CRYPTO_ALG_ASYNC,
1271
-			.cra_blocksize		= SHA1_BLOCK_SIZE,
1272
-			.cra_ctxsize		= sizeof(struct atmel_sha_ctx),
1273
-			.cra_alignmask		= 0,
1274
-			.cra_module		= THIS_MODULE,
1275
-			.cra_init		= atmel_sha_cra_init,
1276
-		}
1277
-	}
1275
+	.halg.base.cra_name		= "sha1",
1276
+	.halg.base.cra_driver_name	= "atmel-sha1",
1277
+	.halg.base.cra_blocksize	= SHA1_BLOCK_SIZE,
1278
+
1279
+	.halg.digestsize = SHA1_DIGEST_SIZE,
12781280 },
12791281 {
1280
-	.init		= atmel_sha_init,
1281
-	.update		= atmel_sha_update,
1282
-	.final		= atmel_sha_final,
1283
-	.finup		= atmel_sha_finup,
1284
-	.digest		= atmel_sha_digest,
1285
-	.export		= atmel_sha_export,
1286
-	.import		= atmel_sha_import,
1287
-	.halg = {
1288
-		.digestsize	= SHA256_DIGEST_SIZE,
1289
-		.statesize	= sizeof(struct atmel_sha_reqctx),
1290
-		.base	= {
1291
-			.cra_name		= "sha256",
1292
-			.cra_driver_name	= "atmel-sha256",
1293
-			.cra_priority		= 100,
1294
-			.cra_flags		= CRYPTO_ALG_ASYNC,
1295
-			.cra_blocksize		= SHA256_BLOCK_SIZE,
1296
-			.cra_ctxsize		= sizeof(struct atmel_sha_ctx),
1297
-			.cra_alignmask		= 0,
1298
-			.cra_module		= THIS_MODULE,
1299
-			.cra_init		= atmel_sha_cra_init,
1300
-		}
1301
-	}
1282
+	.halg.base.cra_name		= "sha256",
1283
+	.halg.base.cra_driver_name	= "atmel-sha256",
1284
+	.halg.base.cra_blocksize	= SHA256_BLOCK_SIZE,
1285
+
1286
+	.halg.digestsize = SHA256_DIGEST_SIZE,
13021287 },
13031288 };
13041289 
13051290 static struct ahash_alg sha_224_alg = {
1306
-	.init		= atmel_sha_init,
1307
-	.update		= atmel_sha_update,
1308
-	.final		= atmel_sha_final,
1309
-	.finup		= atmel_sha_finup,
1310
-	.digest		= atmel_sha_digest,
1311
-	.export		= atmel_sha_export,
1312
-	.import		= atmel_sha_import,
1313
-	.halg = {
1314
-		.digestsize	= SHA224_DIGEST_SIZE,
1315
-		.statesize	= sizeof(struct atmel_sha_reqctx),
1316
-		.base	= {
1317
-			.cra_name		= "sha224",
1318
-			.cra_driver_name	= "atmel-sha224",
1319
-			.cra_priority		= 100,
1320
-			.cra_flags		= CRYPTO_ALG_ASYNC,
1321
-			.cra_blocksize		= SHA224_BLOCK_SIZE,
1322
-			.cra_ctxsize		= sizeof(struct atmel_sha_ctx),
1323
-			.cra_alignmask		= 0,
1324
-			.cra_module		= THIS_MODULE,
1325
-			.cra_init		= atmel_sha_cra_init,
1326
-		}
1327
-	}
1291
+	.halg.base.cra_name		= "sha224",
1292
+	.halg.base.cra_driver_name	= "atmel-sha224",
1293
+	.halg.base.cra_blocksize	= SHA224_BLOCK_SIZE,
1294
+
1295
+	.halg.digestsize = SHA224_DIGEST_SIZE,
13281296 };
13291297 
13301298 static struct ahash_alg sha_384_512_algs[] = {
13311299 {
1332
-	.init		= atmel_sha_init,
1333
-	.update		= atmel_sha_update,
1334
-	.final		= atmel_sha_final,
1335
-	.finup		= atmel_sha_finup,
1336
-	.digest		= atmel_sha_digest,
1337
-	.export		= atmel_sha_export,
1338
-	.import		= atmel_sha_import,
1339
-	.halg = {
1340
-		.digestsize	= SHA384_DIGEST_SIZE,
1341
-		.statesize	= sizeof(struct atmel_sha_reqctx),
1342
-		.base	= {
1343
-			.cra_name		= "sha384",
1344
-			.cra_driver_name	= "atmel-sha384",
1345
-			.cra_priority		= 100,
1346
-			.cra_flags		= CRYPTO_ALG_ASYNC,
1347
-			.cra_blocksize		= SHA384_BLOCK_SIZE,
1348
-			.cra_ctxsize		= sizeof(struct atmel_sha_ctx),
1349
-			.cra_alignmask		= 0x3,
1350
-			.cra_module		= THIS_MODULE,
1351
-			.cra_init		= atmel_sha_cra_init,
1352
-		}
1353
-	}
1300
+	.halg.base.cra_name		= "sha384",
1301
+	.halg.base.cra_driver_name	= "atmel-sha384",
1302
+	.halg.base.cra_blocksize	= SHA384_BLOCK_SIZE,
1303
+	.halg.base.cra_alignmask	= 0x3,
1304
+
1305
+	.halg.digestsize = SHA384_DIGEST_SIZE,
13541306 },
13551307 {
1356
-	.init		= atmel_sha_init,
1357
-	.update		= atmel_sha_update,
1358
-	.final		= atmel_sha_final,
1359
-	.finup		= atmel_sha_finup,
1360
-	.digest		= atmel_sha_digest,
1361
-	.export		= atmel_sha_export,
1362
-	.import		= atmel_sha_import,
1363
-	.halg = {
1364
-		.digestsize	= SHA512_DIGEST_SIZE,
1365
-		.statesize	= sizeof(struct atmel_sha_reqctx),
1366
-		.base	= {
1367
-			.cra_name		= "sha512",
1368
-			.cra_driver_name	= "atmel-sha512",
1369
-			.cra_priority		= 100,
1370
-			.cra_flags		= CRYPTO_ALG_ASYNC,
1371
-			.cra_blocksize		= SHA512_BLOCK_SIZE,
1372
-			.cra_ctxsize		= sizeof(struct atmel_sha_ctx),
1373
-			.cra_alignmask		= 0x3,
1374
-			.cra_module		= THIS_MODULE,
1375
-			.cra_init		= atmel_sha_cra_init,
1376
-		}
1377
-	}
1308
+	.halg.base.cra_name		= "sha512",
1309
+	.halg.base.cra_driver_name	= "atmel-sha512",
1310
+	.halg.base.cra_blocksize	= SHA512_BLOCK_SIZE,
1311
+	.halg.base.cra_alignmask	= 0x3,
1312
+
1313
+	.halg.digestsize = SHA512_DIGEST_SIZE,
13781314 },
13791315 };
13801316 
....@@ -1398,10 +1334,6 @@
13981334 		if (SHA_FLAGS_DMA_ACTIVE & dd->flags) {
13991335 			dd->flags &= ~SHA_FLAGS_DMA_ACTIVE;
14001336 			atmel_sha_update_dma_stop(dd);
1401
-			if (dd->err) {
1402
-				err = dd->err;
1403
-				goto finish;
1404
-			}
14051337 		}
14061338 		if (SHA_FLAGS_OUTPUT_READY & dd->flags) {
14071339 			/* hash or semi-hash ready */
....@@ -1496,7 +1428,6 @@
14961428 	struct scatterlist *sg;
14971429 	int nents;
14981430 
1499
-	dmaengine_terminate_all(dma->chan);
15001431 	dma_unmap_sg(dd->dev, dma->sg, dma->nents, DMA_TO_DEVICE);
15011432 
15021433 	sg = dma->sg;
....@@ -2082,131 +2013,61 @@
20822013 	atmel_sha_hmac_key_release(&hmac->hkey);
20832014 }
20842015 
2016
+static void atmel_sha_hmac_alg_init(struct ahash_alg *alg)
2017
+{
2018
+	alg->halg.base.cra_priority = ATMEL_SHA_PRIORITY;
2019
+	alg->halg.base.cra_flags = CRYPTO_ALG_ASYNC;
2020
+	alg->halg.base.cra_ctxsize = sizeof(struct atmel_sha_hmac_ctx);
2021
+	alg->halg.base.cra_module = THIS_MODULE;
2022
+	alg->halg.base.cra_init	= atmel_sha_hmac_cra_init;
2023
+	alg->halg.base.cra_exit	= atmel_sha_hmac_cra_exit;
2024
+
2025
+	alg->halg.statesize = sizeof(struct atmel_sha_reqctx);
2026
+
2027
+	alg->init = atmel_sha_hmac_init;
2028
+	alg->update = atmel_sha_update;
2029
+	alg->final = atmel_sha_final;
2030
+	alg->digest = atmel_sha_hmac_digest;
2031
+	alg->setkey = atmel_sha_hmac_setkey;
2032
+	alg->export = atmel_sha_export;
2033
+	alg->import = atmel_sha_import;
2034
+}
2035
+
20852036 static struct ahash_alg sha_hmac_algs[] = {
20862037 {
2087
-	.init		= atmel_sha_hmac_init,
2088
-	.update		= atmel_sha_update,
2089
-	.final		= atmel_sha_final,
2090
-	.digest		= atmel_sha_hmac_digest,
2091
-	.setkey		= atmel_sha_hmac_setkey,
2092
-	.export		= atmel_sha_export,
2093
-	.import		= atmel_sha_import,
2094
-	.halg = {
2095
-		.digestsize	= SHA1_DIGEST_SIZE,
2096
-		.statesize	= sizeof(struct atmel_sha_reqctx),
2097
-		.base	= {
2098
-			.cra_name		= "hmac(sha1)",
2099
-			.cra_driver_name	= "atmel-hmac-sha1",
2100
-			.cra_priority		= 100,
2101
-			.cra_flags		= CRYPTO_ALG_ASYNC,
2102
-			.cra_blocksize		= SHA1_BLOCK_SIZE,
2103
-			.cra_ctxsize		= sizeof(struct atmel_sha_hmac_ctx),
2104
-			.cra_alignmask		= 0,
2105
-			.cra_module		= THIS_MODULE,
2106
-			.cra_init		= atmel_sha_hmac_cra_init,
2107
-			.cra_exit		= atmel_sha_hmac_cra_exit,
2108
-		}
2109
-	}
2038
+	.halg.base.cra_name		= "hmac(sha1)",
2039
+	.halg.base.cra_driver_name	= "atmel-hmac-sha1",
2040
+	.halg.base.cra_blocksize	= SHA1_BLOCK_SIZE,
2041
+
2042
+	.halg.digestsize = SHA1_DIGEST_SIZE,
21102043 },
21112044 {
2112
-	.init		= atmel_sha_hmac_init,
2113
-	.update		= atmel_sha_update,
2114
-	.final		= atmel_sha_final,
2115
-	.digest		= atmel_sha_hmac_digest,
2116
-	.setkey		= atmel_sha_hmac_setkey,
2117
-	.export		= atmel_sha_export,
2118
-	.import		= atmel_sha_import,
2119
-	.halg = {
2120
-		.digestsize	= SHA224_DIGEST_SIZE,
2121
-		.statesize	= sizeof(struct atmel_sha_reqctx),
2122
-		.base	= {
2123
-			.cra_name		= "hmac(sha224)",
2124
-			.cra_driver_name	= "atmel-hmac-sha224",
2125
-			.cra_priority		= 100,
2126
-			.cra_flags		= CRYPTO_ALG_ASYNC,
2127
-			.cra_blocksize		= SHA224_BLOCK_SIZE,
2128
-			.cra_ctxsize		= sizeof(struct atmel_sha_hmac_ctx),
2129
-			.cra_alignmask		= 0,
2130
-			.cra_module		= THIS_MODULE,
2131
-			.cra_init		= atmel_sha_hmac_cra_init,
2132
-			.cra_exit		= atmel_sha_hmac_cra_exit,
2133
-		}
2134
-	}
2045
+	.halg.base.cra_name		= "hmac(sha224)",
2046
+	.halg.base.cra_driver_name	= "atmel-hmac-sha224",
2047
+	.halg.base.cra_blocksize	= SHA224_BLOCK_SIZE,
2048
+
2049
+	.halg.digestsize = SHA224_DIGEST_SIZE,
21352050 },
21362051 {
2137
-	.init		= atmel_sha_hmac_init,
2138
-	.update		= atmel_sha_update,
2139
-	.final		= atmel_sha_final,
2140
-	.digest		= atmel_sha_hmac_digest,
2141
-	.setkey		= atmel_sha_hmac_setkey,
2142
-	.export		= atmel_sha_export,
2143
-	.import		= atmel_sha_import,
2144
-	.halg = {
2145
-		.digestsize	= SHA256_DIGEST_SIZE,
2146
-		.statesize	= sizeof(struct atmel_sha_reqctx),
2147
-		.base	= {
2148
-			.cra_name		= "hmac(sha256)",
2149
-			.cra_driver_name	= "atmel-hmac-sha256",
2150
-			.cra_priority		= 100,
2151
-			.cra_flags		= CRYPTO_ALG_ASYNC,
2152
-			.cra_blocksize		= SHA256_BLOCK_SIZE,
2153
-			.cra_ctxsize		= sizeof(struct atmel_sha_hmac_ctx),
2154
-			.cra_alignmask		= 0,
2155
-			.cra_module		= THIS_MODULE,
2156
-			.cra_init		= atmel_sha_hmac_cra_init,
2157
-			.cra_exit		= atmel_sha_hmac_cra_exit,
2158
-		}
2159
-	}
2052
+	.halg.base.cra_name		= "hmac(sha256)",
2053
+	.halg.base.cra_driver_name	= "atmel-hmac-sha256",
2054
+	.halg.base.cra_blocksize	= SHA256_BLOCK_SIZE,
2055
+
2056
+	.halg.digestsize = SHA256_DIGEST_SIZE,
21602057 },
21612058 {
2162
-	.init		= atmel_sha_hmac_init,
2163
-	.update		= atmel_sha_update,
2164
-	.final		= atmel_sha_final,
2165
-	.digest		= atmel_sha_hmac_digest,
2166
-	.setkey		= atmel_sha_hmac_setkey,
2167
-	.export		= atmel_sha_export,
2168
-	.import		= atmel_sha_import,
2169
-	.halg = {
2170
-		.digestsize	= SHA384_DIGEST_SIZE,
2171
-		.statesize	= sizeof(struct atmel_sha_reqctx),
2172
-		.base	= {
2173
-			.cra_name		= "hmac(sha384)",
2174
-			.cra_driver_name	= "atmel-hmac-sha384",
2175
-			.cra_priority		= 100,
2176
-			.cra_flags		= CRYPTO_ALG_ASYNC,
2177
-			.cra_blocksize		= SHA384_BLOCK_SIZE,
2178
-			.cra_ctxsize		= sizeof(struct atmel_sha_hmac_ctx),
2179
-			.cra_alignmask		= 0,
2180
-			.cra_module		= THIS_MODULE,
2181
-			.cra_init		= atmel_sha_hmac_cra_init,
2182
-			.cra_exit		= atmel_sha_hmac_cra_exit,
2183
-		}
2184
-	}
2059
+	.halg.base.cra_name		= "hmac(sha384)",
2060
+	.halg.base.cra_driver_name	= "atmel-hmac-sha384",
2061
+	.halg.base.cra_blocksize	= SHA384_BLOCK_SIZE,
2062
+
2063
+	.halg.digestsize = SHA384_DIGEST_SIZE,
21852064 },
21862065 {
2187
-	.init		= atmel_sha_hmac_init,
2188
-	.update		= atmel_sha_update,
2189
-	.final		= atmel_sha_final,
2190
-	.digest		= atmel_sha_hmac_digest,
2191
-	.setkey		= atmel_sha_hmac_setkey,
2192
-	.export		= atmel_sha_export,
2193
-	.import		= atmel_sha_import,
2194
-	.halg = {
2195
-		.digestsize	= SHA512_DIGEST_SIZE,
2196
-		.statesize	= sizeof(struct atmel_sha_reqctx),
2197
-		.base	= {
2198
-			.cra_name		= "hmac(sha512)",
2199
-			.cra_driver_name	= "atmel-hmac-sha512",
2200
-			.cra_priority		= 100,
2201
-			.cra_flags		= CRYPTO_ALG_ASYNC,
2202
-			.cra_blocksize		= SHA512_BLOCK_SIZE,
2203
-			.cra_ctxsize		= sizeof(struct atmel_sha_hmac_ctx),
2204
-			.cra_alignmask		= 0,
2205
-			.cra_module		= THIS_MODULE,
2206
-			.cra_init		= atmel_sha_hmac_cra_init,
2207
-			.cra_exit		= atmel_sha_hmac_cra_exit,
2208
-		}
2209
-	}
2066
+	.halg.base.cra_name		= "hmac(sha512)",
2067
+	.halg.base.cra_driver_name	= "atmel-hmac-sha512",
2068
+	.halg.base.cra_blocksize	= SHA512_BLOCK_SIZE,
2069
+
2070
+	.halg.digestsize = SHA512_DIGEST_SIZE,
22102071 },
22112072 };
22122073 
....@@ -2345,18 +2206,13 @@
23452206 EXPORT_SYMBOL_GPL(atmel_sha_authenc_free);
23462207 
23472208 int atmel_sha_authenc_setkey(struct atmel_sha_authenc_ctx *auth,
2348
-			     const u8 *key, unsigned int keylen,
2349
-			     u32 *flags)
2209
+			     const u8 *key, unsigned int keylen, u32 flags)
23502210 {
23512211 	struct crypto_ahash *tfm = auth->tfm;
2352
-	int err;
23532212 
23542213 	crypto_ahash_clear_flags(tfm, CRYPTO_TFM_REQ_MASK);
2355
-	crypto_ahash_set_flags(tfm, *flags & CRYPTO_TFM_REQ_MASK);
2356
-	err = crypto_ahash_setkey(tfm, key, keylen);
2357
-	*flags = crypto_ahash_get_flags(tfm);
2358
-
2359
-	return err;
2214
+	crypto_ahash_set_flags(tfm, flags & CRYPTO_TFM_REQ_MASK);
2215
+	return crypto_ahash_setkey(tfm, key, keylen);
23602216 }
23612217 EXPORT_SYMBOL_GPL(atmel_sha_authenc_setkey);
23622218 
....@@ -2559,12 +2415,16 @@
25592415 	int err, i, j;
25602416 
25612417 	for (i = 0; i < ARRAY_SIZE(sha_1_256_algs); i++) {
2418
+		atmel_sha_alg_init(&sha_1_256_algs[i]);
2419
+
25622420 		err = crypto_register_ahash(&sha_1_256_algs[i]);
25632421 		if (err)
25642422 			goto err_sha_1_256_algs;
25652423 	}
25662424 
25672425 	if (dd->caps.has_sha224) {
2426
+		atmel_sha_alg_init(&sha_224_alg);
2427
+
25682428 		err = crypto_register_ahash(&sha_224_alg);
25692429 		if (err)
25702430 			goto err_sha_224_algs;
....@@ -2572,6 +2432,8 @@
25722432 
25732433 	if (dd->caps.has_sha_384_512) {
25742434 		for (i = 0; i < ARRAY_SIZE(sha_384_512_algs); i++) {
2435
+			atmel_sha_alg_init(&sha_384_512_algs[i]);
2436
+
25752437 			err = crypto_register_ahash(&sha_384_512_algs[i]);
25762438 			if (err)
25772439 				goto err_sha_384_512_algs;
....@@ -2580,6 +2442,8 @@
25802442 
25812443 	if (dd->caps.has_hmac) {
25822444 		for (i = 0; i < ARRAY_SIZE(sha_hmac_algs); i++) {
2445
+			atmel_sha_hmac_alg_init(&sha_hmac_algs[i]);
2446
+
25832447 			err = crypto_register_ahash(&sha_hmac_algs[i]);
25842448 			if (err)
25852449 				goto err_sha_hmac_algs;
....@@ -2606,35 +2470,14 @@
26062470 	return err;
26072471 }
26082472 
2609
-static bool atmel_sha_filter(struct dma_chan *chan, void *slave)
2473
+static int atmel_sha_dma_init(struct atmel_sha_dev *dd)
26102474 {
2611
-	struct at_dma_slave	*sl = slave;
2612
-
2613
-	if (sl && sl->dma_dev == chan->device->dev) {
2614
-		chan->private = sl;
2615
-		return true;
2616
-	} else {
2617
-		return false;
2618
-	}
2619
-}
2620
-
2621
-static int atmel_sha_dma_init(struct atmel_sha_dev *dd,
2622
-				struct crypto_platform_data *pdata)
2623
-{
2624
-	dma_cap_mask_t mask_in;
2625
-
2626
-	/* Try to grab DMA channel */
2627
-	dma_cap_zero(mask_in);
2628
-	dma_cap_set(DMA_SLAVE, mask_in);
2629
-
2630
-	dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in,
2631
-			atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx");
2632
-	if (!dd->dma_lch_in.chan) {
2633
-		dev_warn(dd->dev, "no DMA channel available\n");
2634
-		return -ENODEV;
2475
+	dd->dma_lch_in.chan = dma_request_chan(dd->dev, "tx");
2476
+	if (IS_ERR(dd->dma_lch_in.chan)) {
2477
+		dev_err(dd->dev, "DMA channel is not available\n");
2478
+		return PTR_ERR(dd->dma_lch_in.chan);
26352479 	}
26362480 
2637
-	dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
26382481 	dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
26392482 		SHA_REG_DIN(0);
26402483 	dd->dma_lch_in.dma_conf.src_maxburst = 1;
....@@ -2707,49 +2550,18 @@
27072550 };
27082551 
27092552 MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids);
2710
-
2711
-static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev)
2712
-{
2713
-	struct device_node *np = pdev->dev.of_node;
2714
-	struct crypto_platform_data *pdata;
2715
-
2716
-	if (!np) {
2717
-		dev_err(&pdev->dev, "device node not found\n");
2718
-		return ERR_PTR(-EINVAL);
2719
-	}
2720
-
2721
-	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
2722
-	if (!pdata)
2723
-		return ERR_PTR(-ENOMEM);
2724
-
2725
-	pdata->dma_slave = devm_kzalloc(&pdev->dev,
2726
-					sizeof(*(pdata->dma_slave)),
2727
-					GFP_KERNEL);
2728
-	if (!pdata->dma_slave)
2729
-		return ERR_PTR(-ENOMEM);
2730
-
2731
-	return pdata;
2732
-}
2733
-#else /* CONFIG_OF */
2734
-static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev)
2735
-{
2736
-	return ERR_PTR(-EINVAL);
2737
-}
27382553 #endif
27392554 
27402555 static int atmel_sha_probe(struct platform_device *pdev)
27412556 {
27422557 	struct atmel_sha_dev *sha_dd;
2743
-	struct crypto_platform_data	*pdata;
27442558 	struct device *dev = &pdev->dev;
27452559 	struct resource *sha_res;
27462560 	int err;
27472561 
27482562 	sha_dd = devm_kzalloc(&pdev->dev, sizeof(*sha_dd), GFP_KERNEL);
2749
-	if (sha_dd == NULL) {
2750
-		err = -ENOMEM;
2751
-		goto sha_dd_err;
2752
-	}
2563
+	if (!sha_dd)
2564
+		return -ENOMEM;
27532565 
27542566 	sha_dd->dev = dev;
27552567 
....@@ -2770,23 +2582,22 @@
27702582 	if (!sha_res) {
27712583 		dev_err(dev, "no MEM resource info\n");
27722584 		err = -ENODEV;
2773
-		goto res_err;
2585
+		goto err_tasklet_kill;
27742586 	}
27752587 	sha_dd->phys_base = sha_res->start;
27762588 
27772589 	/* Get the IRQ */
27782590 	sha_dd->irq = platform_get_irq(pdev,  0);
27792591 	if (sha_dd->irq < 0) {
2780
-		dev_err(dev, "no IRQ resource info\n");
27812592 		err = sha_dd->irq;
2782
-		goto res_err;
2593
+		goto err_tasklet_kill;
27832594 	}
27842595 
27852596 	err = devm_request_irq(&pdev->dev, sha_dd->irq, atmel_sha_irq,
27862597 			       IRQF_SHARED, "atmel-sha", sha_dd);
27872598 	if (err) {
27882599 		dev_err(dev, "unable to request sha irq.\n");
2789
-		goto res_err;
2600
+		goto err_tasklet_kill;
27902601 	}
27912602 
27922603 	/* Initializing the clock */
....@@ -2794,41 +2605,30 @@
27942605 	if (IS_ERR(sha_dd->iclk)) {
27952606 		dev_err(dev, "clock initialization failed.\n");
27962607 		err = PTR_ERR(sha_dd->iclk);
2797
-		goto res_err;
2608
+		goto err_tasklet_kill;
27982609 	}
27992610 
28002611 	sha_dd->io_base = devm_ioremap_resource(&pdev->dev, sha_res);
28012612 	if (IS_ERR(sha_dd->io_base)) {
28022613 		dev_err(dev, "can't ioremap\n");
28032614 		err = PTR_ERR(sha_dd->io_base);
2804
-		goto res_err;
2615
+		goto err_tasklet_kill;
28052616 	}
28062617 
28072618 	err = clk_prepare(sha_dd->iclk);
28082619 	if (err)
2809
-		goto res_err;
2620
+		goto err_tasklet_kill;
28102621 
2811
-	atmel_sha_hw_version_init(sha_dd);
2622
+	err = atmel_sha_hw_version_init(sha_dd);
2623
+	if (err)
2624
+		goto err_iclk_unprepare;
28122625 
28132626 	atmel_sha_get_cap(sha_dd);
28142627 
28152628 	if (sha_dd->caps.has_dma) {
2816
-		pdata = pdev->dev.platform_data;
2817
-		if (!pdata) {
2818
-			pdata = atmel_sha_of_init(pdev);
2819
-			if (IS_ERR(pdata)) {
2820
-				dev_err(&pdev->dev, "platform data not available\n");
2821
-				err = PTR_ERR(pdata);
2822
-				goto iclk_unprepare;
2823
-			}
2824
-		}
2825
-		if (!pdata->dma_slave) {
2826
-			err = -ENXIO;
2827
-			goto iclk_unprepare;
2828
-		}
2829
-		err = atmel_sha_dma_init(sha_dd, pdata);
2629
+		err = atmel_sha_dma_init(sha_dd);
28302630 		if (err)
2831
-			goto err_sha_dma;
2631
+			goto err_iclk_unprepare;
28322632 
28332633 		dev_info(dev, "using %s for DMA transfers\n",
28342634 				dma_chan_name(sha_dd->dma_lch_in.chan));
....@@ -2854,14 +2654,11 @@
28542654 	spin_unlock(&atmel_sha.lock);
28552655 	if (sha_dd->caps.has_dma)
28562656 		atmel_sha_dma_cleanup(sha_dd);
2857
-err_sha_dma:
2858
-iclk_unprepare:
2657
+err_iclk_unprepare:
28592658 	clk_unprepare(sha_dd->iclk);
2860
-res_err:
2659
+err_tasklet_kill:
28612660 	tasklet_kill(&sha_dd->queue_task);
28622661 	tasklet_kill(&sha_dd->done_task);
2863
-sha_dd_err:
2864
-	dev_err(dev, "initialization failed.\n");
28652662 
28662663 	return err;
28672664 }