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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/clocksource/mips-gic-timer.c
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@@ -16,6 +16,7 @@
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 #include <linux/notifier.h>
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 #include <linux/of_irq.h>
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 #include <linux/percpu.h>
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+#include <linux/sched_clock.h>
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 #include <linux/smp.h>
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 #include <linux/time.h>
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 #include <asm/mips-cps.h>
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@@ -23,13 +24,13 @@
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 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
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 static int gic_timer_irq;
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 static unsigned int gic_frequency;
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+static bool __read_mostly gic_clock_unstable;
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28
 
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-static u64 notrace gic_read_count(void)
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+static void gic_clocksource_unstable(char *reason);
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+
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+static u64 notrace gic_read_count_2x32(void)
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 {
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 	unsigned int hi, hi2, lo;
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-
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-	if (mips_cm_is64)
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-		return read_gic_counter();
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34
 
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 	do {
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 		hi = read_gic_counter_32h();
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@@ -38,6 +39,19 @@
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 	} while (hi2 != hi);
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 	return (((u64) hi) << 32) + lo;
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+}
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+
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+static u64 notrace gic_read_count_64(void)
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+{
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+	return read_gic_counter();
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+}
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+
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+static u64 notrace gic_read_count(void)
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+{
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+	if (mips_cm_is64)
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+		return gic_read_count_64();
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+
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+	return gic_read_count_2x32();
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 }
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 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
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@@ -67,7 +81,7 @@
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 	return IRQ_HANDLED;
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 }
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-struct irqaction gic_compare_irqaction = {
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+static struct irqaction gic_compare_irqaction = {
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 	.handler = gic_compare_interrupt,
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 	.percpu_dev_id = &gic_clockevent_device,
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 	.flags = IRQF_PERCPU | IRQF_TIMER,
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@@ -114,8 +128,10 @@
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 {
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 	struct clk_notifier_data *cnd = data;
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130
 
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-	if (action == POST_RATE_CHANGE)
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+	if (action == POST_RATE_CHANGE) {
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+		gic_clocksource_unstable("ref clock rate change");
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 		on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
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+	}
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 	return NOTIFY_OK;
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 }
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@@ -155,11 +171,23 @@
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 }
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172
 
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 static struct clocksource gic_clocksource = {
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-	.name		= "GIC",
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-	.read		= gic_hpt_read,
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-	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
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-	.archdata	= { .vdso_clock_mode = VDSO_CLOCK_GIC },
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+	.name			= "GIC",
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+	.read			= gic_hpt_read,
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+	.flags			= CLOCK_SOURCE_IS_CONTINUOUS,
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+	.vdso_clock_mode	= VDSO_CLOCKMODE_GIC,
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 };
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+
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+static void gic_clocksource_unstable(char *reason)
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+{
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+	if (gic_clock_unstable)
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+		return;
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+
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+	gic_clock_unstable = true;
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+
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+	pr_info("GIC timer is unstable due to %s\n", reason);
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+
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+	clocksource_mark_unstable(&gic_clocksource);
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+}
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 static int __init __gic_clocksource_init(void)
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 {
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@@ -228,6 +256,18 @@
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 	/* And finally start the counter */
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 	clear_gic_config(GIC_CONFIG_COUNTSTOP);
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258
 
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+	/*
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+	 * It's safe to use the MIPS GIC timer as a sched clock source only if
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+	 * its ticks are stable, which is true on either the platforms with
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+	 * stable CPU frequency or on the platforms with CM3 and CPU frequency
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+	 * change performed by the CPC core clocks divider.
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+	 */
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+	if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
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+		sched_clock_register(mips_cm_is64 ?
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+				     gic_read_count_64 : gic_read_count_2x32,
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+				     64, gic_frequency);
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+	}
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+
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 	return 0;
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 }
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 TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",