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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/clk/ti/clock.h
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@@ -20,10 +20,13 @@
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 	struct clk_hw		hw;
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 	struct clk_omap_reg	reg;
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 	u8			shift;
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-	u8			width;
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 	u8			flags;
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 	s8			latch;
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+	u16			min;
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+	u16			max;
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+	u16			mask;
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 	const struct clk_div_table	*table;
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+	u32		context;
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 };
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 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
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@@ -36,6 +39,7 @@
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 	u8			shift;
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 	s8			latch;
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 	u8			flags;
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+	u8			saved_parent;
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 };
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 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
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@@ -80,6 +84,13 @@
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 #define CLKF_SW_SUP			BIT(5)
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 #define CLKF_HW_SUP			BIT(6)
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 #define CLKF_NO_IDLEST			BIT(7)
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+
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+#define CLKF_SOC_MASK			GENMASK(11, 8)
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+
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+#define CLKF_SOC_NONSEC			BIT(8)
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+#define CLKF_SOC_DRA72			BIT(9)
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+#define CLKF_SOC_DRA74			BIT(10)
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+#define CLKF_SOC_DRA76			BIT(11)
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 #define CLK(dev, con, ck)		\
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 	{				\
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@@ -184,9 +195,16 @@
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 extern const struct omap_clkctrl_data omap4_clkctrl_data[];
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 extern const struct omap_clkctrl_data omap5_clkctrl_data[];
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 extern const struct omap_clkctrl_data dra7_clkctrl_data[];
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+extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
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+extern struct ti_dt_clk dra7xx_compat_clks[];
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 extern const struct omap_clkctrl_data am3_clkctrl_data[];
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+extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
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+extern struct ti_dt_clk am33xx_compat_clks[];
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 extern const struct omap_clkctrl_data am4_clkctrl_data[];
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+extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
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+extern struct ti_dt_clk am43xx_compat_clks[];
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 extern const struct omap_clkctrl_data am438x_clkctrl_data[];
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+extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
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 extern const struct omap_clkctrl_data dm814_clkctrl_data[];
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 extern const struct omap_clkctrl_data dm816_clkctrl_data[];
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@@ -194,6 +212,8 @@
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 struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
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 			    const char *con);
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+struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
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+				    const char *con);
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 int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
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 void ti_clk_add_aliases(void);
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@@ -202,8 +222,7 @@
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 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
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 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
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-			      u8 flags, u8 *width,
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-			      const struct clk_div_table **table);
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+			      u8 flags, struct clk_omap_divider *div);
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 int ti_clk_get_reg_addr(struct device_node *node, int index,
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 			struct clk_omap_reg *reg);
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@@ -212,7 +231,6 @@
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 		      ti_of_clk_init_cb_t func);
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 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
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-void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
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 int of_ti_clk_autoidle_setup(struct device_node *node);
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 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
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@@ -233,7 +251,9 @@
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 extern const struct clk_ops ti_clk_mux_ops;
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 extern const struct clk_ops omap_gate_clk_ops;
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-void omap2_init_clk_clkdm(struct clk_hw *hw);
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+extern struct ti_clk_features ti_clk_features;
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+
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+int omap2_init_clk_clkdm(struct clk_hw *hw);
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 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
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 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
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@@ -290,6 +310,7 @@
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 				    unsigned long *parent_rate);
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 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
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 				       struct clk_rate_request *req);
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+int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
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 extern struct ti_clk_ll_ops *ti_clk_ll_ops;
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