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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/clk/ti/clk-54xx.c
....@@ -1,13 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * OMAP5 Clock init
34  *
45  * Copyright (C) 2013 Texas Instruments, Inc.
56  *
67  * Tero Kristo (t-kristo@ti.com)
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
118  */
129 
1310 #include <linux/kernel.h>
....@@ -34,7 +31,21 @@
3431 };
3532 
3633 static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
37
-	{ OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" },
34
+	{ OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
35
+	{ 0 },
36
+};
37
+
38
+static const char * const omap5_aess_fclk_parents[] __initconst = {
39
+	"abe_clk",
40
+	NULL,
41
+};
42
+
43
+static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
44
+	.max_div = 2,
45
+};
46
+
47
+static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
48
+	{ 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
3849 	{ 0 },
3950 };
4051 
....@@ -125,6 +136,7 @@
125136 
126137 static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
127138 	{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
139
+	{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
128140 	{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
129141 	{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
130142 	{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
....@@ -148,7 +160,7 @@
148160 };
149161 
150162 static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
151
-	{ OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
163
+	{ OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
152164 	{ 0 },
153165 };
154166 
....@@ -289,6 +301,24 @@
289301 	{ 0 },
290302 };
291303 
304
+static const struct
305
+omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
306
+	{ OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
307
+	{ OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
308
+	{ OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
309
+	{ OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
310
+	{ OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
311
+	{ OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
312
+	{ OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" },
313
+	{ 0 },
314
+};
315
+
316
+static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
317
+	{ OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
318
+	{ OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
319
+	{ 0 },
320
+};
321
+
292322 static const char * const omap5_dss_dss_clk_parents[] __initconst = {
293323 	"dpll_per_h12x2_ck",
294324 	NULL,
....@@ -314,6 +344,39 @@
314344 
315345 static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
316346 	{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
347
+	{ 0 },
348
+};
349
+
350
+static const char * const omap5_gpu_core_mux_parents[] __initconst = {
351
+	"dpll_core_h14x2_ck",
352
+	"dpll_per_h14x2_ck",
353
+	NULL,
354
+};
355
+
356
+static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
357
+	"dpll_core_h14x2_ck",
358
+	"dpll_per_h14x2_ck",
359
+	NULL,
360
+};
361
+
362
+static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
363
+	"sys_clkin",
364
+	NULL,
365
+};
366
+
367
+static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
368
+	.max_div = 2,
369
+};
370
+
371
+static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
372
+	{ 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
373
+	{ 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
374
+	{ 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
375
+	{ 0 },
376
+};
377
+
378
+static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
379
+	{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
317380 	{ 0 },
318381 };
319382 
....@@ -472,7 +535,10 @@
472535 	{ 0x4a008d20, omap5_l4cfg_clkctrl_regs },
473536 	{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
474537 	{ 0x4a009020, omap5_l4per_clkctrl_regs },
538
+	{ 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
539
+	{ 0x4a009220, omap5_iva_clkctrl_regs },
475540 	{ 0x4a009420, omap5_dss_clkctrl_regs },
541
+	{ 0x4a009520, omap5_gpu_clkctrl_regs },
476542 	{ 0x4a009620, omap5_l3init_clkctrl_regs },
477543 	{ 0x4ae07920, omap5_wkupaon_clkctrl_regs },
478544 	{ 0 },