.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * OMAP4 Clock init |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2013 Texas Instruments, Inc. |
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5 | 6 | * |
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6 | 7 | * Tero Kristo (t-kristo@ti.com) |
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7 | | - * |
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8 | | - * This program is free software; you can redistribute it and/or modify |
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9 | | - * it under the terms of the GNU General Public License version 2 as |
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10 | | - * published by the Free Software Foundation. |
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11 | 8 | */ |
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12 | 9 | |
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13 | 10 | #include <linux/kernel.h> |
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.. | .. |
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40 | 37 | }; |
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41 | 38 | |
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42 | 39 | static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = { |
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43 | | - { OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m4x2_ck" }, |
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| 40 | + { OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m4x2_ck" }, |
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44 | 41 | { 0 }, |
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45 | 42 | }; |
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46 | 43 | |
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.. | .. |
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222 | 219 | }; |
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223 | 220 | |
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224 | 221 | static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = { |
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225 | | - { OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "ducati_clk_mux_ck" }, |
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| 222 | + { OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "ducati_clk_mux_ck" }, |
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226 | 223 | { 0 }, |
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227 | 224 | }; |
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228 | 225 | |
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.. | .. |
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607 | 604 | { 0 }, |
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608 | 605 | }; |
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609 | 606 | |
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| 607 | +static const struct |
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| 608 | +omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = { |
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| 609 | + { OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" }, |
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| 610 | + { OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" }, |
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| 611 | + { OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" }, |
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| 612 | + { OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" }, |
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| 613 | + { OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_div_ck" }, |
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| 614 | + { OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" }, |
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| 615 | + { OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_div_ck" }, |
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| 616 | + { 0 }, |
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| 617 | +}; |
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| 618 | + |
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610 | 619 | static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = { |
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611 | 620 | { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, |
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612 | 621 | { 0 }, |
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.. | .. |
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694 | 703 | { 0x4a009220, omap4_l3_gfx_clkctrl_regs }, |
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695 | 704 | { 0x4a009320, omap4_l3_init_clkctrl_regs }, |
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696 | 705 | { 0x4a009420, omap4_l4_per_clkctrl_regs }, |
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| 706 | + { 0x4a0095a0, omap4_l4_secure_clkctrl_regs }, |
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697 | 707 | { 0x4a307820, omap4_l4_wkup_clkctrl_regs }, |
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698 | 708 | { 0x4a307a20, omap4_emu_sys_clkctrl_regs }, |
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699 | 709 | { 0 }, |
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