~hc/RK356X_SDK_RELEASE.git

..	..	@@ -4,179 +4,92 @@
4	4	* Michael Turquette <mturquette@baylibre.com>
5	5	*/
6	6
7		-#include <linux/clk.h>
8	7	#include <linux/clk-provider.h>
9	8	#include <linux/init.h>
10	9	#include <linux/of_device.h>
11		-#include <linux/mfd/syscon.h>
12	10	#include <linux/platform_device.h>
13		-#include <linux/regmap.h>
	11	+#include <linux/module.h>
14	12
15		-#include "clkc.h"
16	13	#include "gxbb.h"
17	14	#include "clk-regmap.h"
	15	+#include "clk-pll.h"
	16	+#include "clk-mpll.h"
	17	+#include "meson-eeclk.h"
	18	+#include "vid-pll-div.h"
18	19
19	20	static DEFINE_SPINLOCK(meson_clk_lock);
20	21
21		-static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
22		- PLL_RATE(96000000, 32, 1, 3),
23		- PLL_RATE(99000000, 33, 1, 3),
24		- PLL_RATE(102000000, 34, 1, 3),
25		- PLL_RATE(105000000, 35, 1, 3),
26		- PLL_RATE(108000000, 36, 1, 3),
27		- PLL_RATE(111000000, 37, 1, 3),
28		- PLL_RATE(114000000, 38, 1, 3),
29		- PLL_RATE(117000000, 39, 1, 3),
30		- PLL_RATE(120000000, 40, 1, 3),
31		- PLL_RATE(123000000, 41, 1, 3),
32		- PLL_RATE(126000000, 42, 1, 3),
33		- PLL_RATE(129000000, 43, 1, 3),
34		- PLL_RATE(132000000, 44, 1, 3),
35		- PLL_RATE(135000000, 45, 1, 3),
36		- PLL_RATE(138000000, 46, 1, 3),
37		- PLL_RATE(141000000, 47, 1, 3),
38		- PLL_RATE(144000000, 48, 1, 3),
39		- PLL_RATE(147000000, 49, 1, 3),
40		- PLL_RATE(150000000, 50, 1, 3),
41		- PLL_RATE(153000000, 51, 1, 3),
42		- PLL_RATE(156000000, 52, 1, 3),
43		- PLL_RATE(159000000, 53, 1, 3),
44		- PLL_RATE(162000000, 54, 1, 3),
45		- PLL_RATE(165000000, 55, 1, 3),
46		- PLL_RATE(168000000, 56, 1, 3),
47		- PLL_RATE(171000000, 57, 1, 3),
48		- PLL_RATE(174000000, 58, 1, 3),
49		- PLL_RATE(177000000, 59, 1, 3),
50		- PLL_RATE(180000000, 60, 1, 3),
51		- PLL_RATE(183000000, 61, 1, 3),
52		- PLL_RATE(186000000, 62, 1, 3),
53		- PLL_RATE(192000000, 32, 1, 2),
54		- PLL_RATE(198000000, 33, 1, 2),
55		- PLL_RATE(204000000, 34, 1, 2),
56		- PLL_RATE(210000000, 35, 1, 2),
57		- PLL_RATE(216000000, 36, 1, 2),
58		- PLL_RATE(222000000, 37, 1, 2),
59		- PLL_RATE(228000000, 38, 1, 2),
60		- PLL_RATE(234000000, 39, 1, 2),
61		- PLL_RATE(240000000, 40, 1, 2),
62		- PLL_RATE(246000000, 41, 1, 2),
63		- PLL_RATE(252000000, 42, 1, 2),
64		- PLL_RATE(258000000, 43, 1, 2),
65		- PLL_RATE(264000000, 44, 1, 2),
66		- PLL_RATE(270000000, 45, 1, 2),
67		- PLL_RATE(276000000, 46, 1, 2),
68		- PLL_RATE(282000000, 47, 1, 2),
69		- PLL_RATE(288000000, 48, 1, 2),
70		- PLL_RATE(294000000, 49, 1, 2),
71		- PLL_RATE(300000000, 50, 1, 2),
72		- PLL_RATE(306000000, 51, 1, 2),
73		- PLL_RATE(312000000, 52, 1, 2),
74		- PLL_RATE(318000000, 53, 1, 2),
75		- PLL_RATE(324000000, 54, 1, 2),
76		- PLL_RATE(330000000, 55, 1, 2),
77		- PLL_RATE(336000000, 56, 1, 2),
78		- PLL_RATE(342000000, 57, 1, 2),
79		- PLL_RATE(348000000, 58, 1, 2),
80		- PLL_RATE(354000000, 59, 1, 2),
81		- PLL_RATE(360000000, 60, 1, 2),
82		- PLL_RATE(366000000, 61, 1, 2),
83		- PLL_RATE(372000000, 62, 1, 2),
84		- PLL_RATE(384000000, 32, 1, 1),
85		- PLL_RATE(396000000, 33, 1, 1),
86		- PLL_RATE(408000000, 34, 1, 1),
87		- PLL_RATE(420000000, 35, 1, 1),
88		- PLL_RATE(432000000, 36, 1, 1),
89		- PLL_RATE(444000000, 37, 1, 1),
90		- PLL_RATE(456000000, 38, 1, 1),
91		- PLL_RATE(468000000, 39, 1, 1),
92		- PLL_RATE(480000000, 40, 1, 1),
93		- PLL_RATE(492000000, 41, 1, 1),
94		- PLL_RATE(504000000, 42, 1, 1),
95		- PLL_RATE(516000000, 43, 1, 1),
96		- PLL_RATE(528000000, 44, 1, 1),
97		- PLL_RATE(540000000, 45, 1, 1),
98		- PLL_RATE(552000000, 46, 1, 1),
99		- PLL_RATE(564000000, 47, 1, 1),
100		- PLL_RATE(576000000, 48, 1, 1),
101		- PLL_RATE(588000000, 49, 1, 1),
102		- PLL_RATE(600000000, 50, 1, 1),
103		- PLL_RATE(612000000, 51, 1, 1),
104		- PLL_RATE(624000000, 52, 1, 1),
105		- PLL_RATE(636000000, 53, 1, 1),
106		- PLL_RATE(648000000, 54, 1, 1),
107		- PLL_RATE(660000000, 55, 1, 1),
108		- PLL_RATE(672000000, 56, 1, 1),
109		- PLL_RATE(684000000, 57, 1, 1),
110		- PLL_RATE(696000000, 58, 1, 1),
111		- PLL_RATE(708000000, 59, 1, 1),
112		- PLL_RATE(720000000, 60, 1, 1),
113		- PLL_RATE(732000000, 61, 1, 1),
114		- PLL_RATE(744000000, 62, 1, 1),
115		- PLL_RATE(768000000, 32, 1, 0),
116		- PLL_RATE(792000000, 33, 1, 0),
117		- PLL_RATE(816000000, 34, 1, 0),
118		- PLL_RATE(840000000, 35, 1, 0),
119		- PLL_RATE(864000000, 36, 1, 0),
120		- PLL_RATE(888000000, 37, 1, 0),
121		- PLL_RATE(912000000, 38, 1, 0),
122		- PLL_RATE(936000000, 39, 1, 0),
123		- PLL_RATE(960000000, 40, 1, 0),
124		- PLL_RATE(984000000, 41, 1, 0),
125		- PLL_RATE(1008000000, 42, 1, 0),
126		- PLL_RATE(1032000000, 43, 1, 0),
127		- PLL_RATE(1056000000, 44, 1, 0),
128		- PLL_RATE(1080000000, 45, 1, 0),
129		- PLL_RATE(1104000000, 46, 1, 0),
130		- PLL_RATE(1128000000, 47, 1, 0),
131		- PLL_RATE(1152000000, 48, 1, 0),
132		- PLL_RATE(1176000000, 49, 1, 0),
133		- PLL_RATE(1200000000, 50, 1, 0),
134		- PLL_RATE(1224000000, 51, 1, 0),
135		- PLL_RATE(1248000000, 52, 1, 0),
136		- PLL_RATE(1272000000, 53, 1, 0),
137		- PLL_RATE(1296000000, 54, 1, 0),
138		- PLL_RATE(1320000000, 55, 1, 0),
139		- PLL_RATE(1344000000, 56, 1, 0),
140		- PLL_RATE(1368000000, 57, 1, 0),
141		- PLL_RATE(1392000000, 58, 1, 0),
142		- PLL_RATE(1416000000, 59, 1, 0),
143		- PLL_RATE(1440000000, 60, 1, 0),
144		- PLL_RATE(1464000000, 61, 1, 0),
145		- PLL_RATE(1488000000, 62, 1, 0),
	22	+static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
	23	+ PLL_PARAMS(32, 1),
	24	+ PLL_PARAMS(33, 1),
	25	+ PLL_PARAMS(34, 1),
	26	+ PLL_PARAMS(35, 1),
	27	+ PLL_PARAMS(36, 1),
	28	+ PLL_PARAMS(37, 1),
	29	+ PLL_PARAMS(38, 1),
	30	+ PLL_PARAMS(39, 1),
	31	+ PLL_PARAMS(40, 1),
	32	+ PLL_PARAMS(41, 1),
	33	+ PLL_PARAMS(42, 1),
	34	+ PLL_PARAMS(43, 1),
	35	+ PLL_PARAMS(44, 1),
	36	+ PLL_PARAMS(45, 1),
	37	+ PLL_PARAMS(46, 1),
	38	+ PLL_PARAMS(47, 1),
	39	+ PLL_PARAMS(48, 1),
	40	+ PLL_PARAMS(49, 1),
	41	+ PLL_PARAMS(50, 1),
	42	+ PLL_PARAMS(51, 1),
	43	+ PLL_PARAMS(52, 1),
	44	+ PLL_PARAMS(53, 1),
	45	+ PLL_PARAMS(54, 1),
	46	+ PLL_PARAMS(55, 1),
	47	+ PLL_PARAMS(56, 1),
	48	+ PLL_PARAMS(57, 1),
	49	+ PLL_PARAMS(58, 1),
	50	+ PLL_PARAMS(59, 1),
	51	+ PLL_PARAMS(60, 1),
	52	+ PLL_PARAMS(61, 1),
	53	+ PLL_PARAMS(62, 1),
146	54	{ /* sentinel */ },
147	55	};
148	56
149		-static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
150		- PLL_RATE(504000000, 42, 1, 1),
151		- PLL_RATE(516000000, 43, 1, 1),
152		- PLL_RATE(528000000, 44, 1, 1),
153		- PLL_RATE(540000000, 45, 1, 1),
154		- PLL_RATE(552000000, 46, 1, 1),
155		- PLL_RATE(564000000, 47, 1, 1),
156		- PLL_RATE(576000000, 48, 1, 1),
157		- PLL_RATE(588000000, 49, 1, 1),
158		- PLL_RATE(600000000, 50, 1, 1),
159		- PLL_RATE(612000000, 51, 1, 1),
160		- PLL_RATE(624000000, 52, 1, 1),
161		- PLL_RATE(636000000, 53, 1, 1),
162		- PLL_RATE(648000000, 54, 1, 1),
163		- PLL_RATE(660000000, 55, 1, 1),
164		- PLL_RATE(672000000, 56, 1, 1),
165		- PLL_RATE(684000000, 57, 1, 1),
166		- PLL_RATE(696000000, 58, 1, 1),
167		- PLL_RATE(708000000, 59, 1, 1),
168		- PLL_RATE(720000000, 60, 1, 1),
169		- PLL_RATE(732000000, 61, 1, 1),
170		- PLL_RATE(744000000, 62, 1, 1),
171		- PLL_RATE(756000000, 63, 1, 1),
172		- PLL_RATE(768000000, 64, 1, 1),
173		- PLL_RATE(780000000, 65, 1, 1),
174		- PLL_RATE(792000000, 66, 1, 1),
	57	+static const struct pll_params_table gxl_gp0_pll_params_table[] = {
	58	+ PLL_PARAMS(42, 1),
	59	+ PLL_PARAMS(43, 1),
	60	+ PLL_PARAMS(44, 1),
	61	+ PLL_PARAMS(45, 1),
	62	+ PLL_PARAMS(46, 1),
	63	+ PLL_PARAMS(47, 1),
	64	+ PLL_PARAMS(48, 1),
	65	+ PLL_PARAMS(49, 1),
	66	+ PLL_PARAMS(50, 1),
	67	+ PLL_PARAMS(51, 1),
	68	+ PLL_PARAMS(52, 1),
	69	+ PLL_PARAMS(53, 1),
	70	+ PLL_PARAMS(54, 1),
	71	+ PLL_PARAMS(55, 1),
	72	+ PLL_PARAMS(56, 1),
	73	+ PLL_PARAMS(57, 1),
	74	+ PLL_PARAMS(58, 1),
	75	+ PLL_PARAMS(59, 1),
	76	+ PLL_PARAMS(60, 1),
	77	+ PLL_PARAMS(61, 1),
	78	+ PLL_PARAMS(62, 1),
	79	+ PLL_PARAMS(63, 1),
	80	+ PLL_PARAMS(64, 1),
	81	+ PLL_PARAMS(65, 1),
	82	+ PLL_PARAMS(66, 1),
175	83	{ /* sentinel */ },
176	84	};
177	85
178		-static struct clk_regmap gxbb_fixed_pll = {
	86	+static struct clk_regmap gxbb_fixed_pll_dco = {
179	87	.data = &(struct meson_clk_pll_data){
	88	+ .en = {
	89	+ .reg_off = HHI_MPLL_CNTL,
	90	+ .shift = 30,
	91	+ .width = 1,
	92	+ },
180	93	.m = {
181	94	.reg_off = HHI_MPLL_CNTL,
182	95	.shift = 0,
..	..	@@ -186,11 +99,6 @@
186	99	.reg_off = HHI_MPLL_CNTL,
187	100	.shift = 9,
188	101	.width = 5,
189		- },
190		- .od = {
191		- .reg_off = HHI_MPLL_CNTL,
192		- .shift = 16,
193		- .width = 2,
194	102	},
195	103	.frac = {
196	104	.reg_off = HHI_MPLL_CNTL2,
..	..	@@ -209,10 +117,33 @@
209	117	},
210	118	},
211	119	.hw.init = &(struct clk_init_data){
212		- .name = "fixed_pll",
	120	+ .name = "fixed_pll_dco",
213	121	.ops = &meson_clk_pll_ro_ops,
214		- .parent_names = (const char *[]){ "xtal" },
	122	+ .parent_data = &(const struct clk_parent_data) {
	123	+ .fw_name = "xtal",
	124	+ },
215	125	.num_parents = 1,
	126	+ },
	127	+};
	128	+
	129	+static struct clk_regmap gxbb_fixed_pll = {
	130	+ .data = &(struct clk_regmap_div_data){
	131	+ .offset = HHI_MPLL_CNTL,
	132	+ .shift = 16,
	133	+ .width = 2,
	134	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	135	+ },
	136	+ .hw.init = &(struct clk_init_data){
	137	+ .name = "fixed_pll",
	138	+ .ops = &clk_regmap_divider_ro_ops,
	139	+ .parent_hws = (const struct clk_hw *[]) {
	140	+ &gxbb_fixed_pll_dco.hw
	141	+ },
	142	+ .num_parents = 1,
	143	+ /*
	144	+ * This clock won't ever change at runtime so
	145	+ * CLK_SET_RATE_PARENT is not required
	146	+ */
216	147	},
217	148	};
218	149
..	..	@@ -222,13 +153,20 @@
222	153	.hw.init = &(struct clk_init_data){
223	154	.name = "hdmi_pll_pre_mult",
224	155	.ops = &clk_fixed_factor_ops,
225		- .parent_names = (const char *[]){ "xtal" },
	156	+ .parent_data = &(const struct clk_parent_data) {
	157	+ .fw_name = "xtal",
	158	+ },
226	159	.num_parents = 1,
227	160	},
228	161	};
229	162
230		-static struct clk_regmap gxbb_hdmi_pll = {
	163	+static struct clk_regmap gxbb_hdmi_pll_dco = {
231	164	.data = &(struct meson_clk_pll_data){
	165	+ .en = {
	166	+ .reg_off = HHI_HDMI_PLL_CNTL,
	167	+ .shift = 30,
	168	+ .width = 1,
	169	+ },
232	170	.m = {
233	171	.reg_off = HHI_HDMI_PLL_CNTL,
234	172	.shift = 0,
..	..	@@ -244,21 +182,6 @@
244	182	.shift = 0,
245	183	.width = 12,
246	184	},
247		- .od = {
248		- .reg_off = HHI_HDMI_PLL_CNTL2,
249		- .shift = 16,
250		- .width = 2,
251		- },
252		- .od2 = {
253		- .reg_off = HHI_HDMI_PLL_CNTL2,
254		- .shift = 22,
255		- .width = 2,
256		- },
257		- .od3 = {
258		- .reg_off = HHI_HDMI_PLL_CNTL2,
259		- .shift = 18,
260		- .width = 2,
261		- },
262	185	.l = {
263	186	.reg_off = HHI_HDMI_PLL_CNTL,
264	187	.shift = 31,
..	..	@@ -271,9 +194,11 @@
271	194	},
272	195	},
273	196	.hw.init = &(struct clk_init_data){
274		- .name = "hdmi_pll",
	197	+ .name = "hdmi_pll_dco",
275	198	.ops = &meson_clk_pll_ro_ops,
276		- .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
	199	+ .parent_hws = (const struct clk_hw *[]) {
	200	+ &gxbb_hdmi_pll_pre_mult.hw
	201	+ },
277	202	.num_parents = 1,
278	203	/*
279	204	* Display directly handle hdmi pll registers ATM, we need
..	..	@@ -283,8 +208,13 @@
283	208	},
284	209	};
285	210
286		-static struct clk_regmap gxl_hdmi_pll = {
	211	+static struct clk_regmap gxl_hdmi_pll_dco = {
287	212	.data = &(struct meson_clk_pll_data){
	213	+ .en = {
	214	+ .reg_off = HHI_HDMI_PLL_CNTL,
	215	+ .shift = 30,
	216	+ .width = 1,
	217	+ },
288	218	.m = {
289	219	.reg_off = HHI_HDMI_PLL_CNTL,
290	220	.shift = 0,
..	..	@@ -302,30 +232,9 @@
302	232	* instead which is defined at the same offset.
303	233	*/
304	234	.frac = {
305		- /*
306		- * On gxl, there is a register shift due to
307		- * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
308		- * so we compute the register offset based on the PLL
309		- * base to get it right
310		- */
311		- .reg_off = HHI_HDMI_PLL_CNTL + 4,
	235	+ .reg_off = HHI_HDMI_PLL_CNTL2,
312	236	.shift = 0,
313	237	.width = 10,
314		- },
315		- .od = {
316		- .reg_off = HHI_HDMI_PLL_CNTL + 8,
317		- .shift = 21,
318		- .width = 2,
319		- },
320		- .od2 = {
321		- .reg_off = HHI_HDMI_PLL_CNTL + 8,
322		- .shift = 23,
323		- .width = 2,
324		- },
325		- .od3 = {
326		- .reg_off = HHI_HDMI_PLL_CNTL + 8,
327		- .shift = 19,
328		- .width = 2,
329	238	},
330	239	.l = {
331	240	.reg_off = HHI_HDMI_PLL_CNTL,
..	..	@@ -334,14 +243,16 @@
334	243	},
335	244	.rst = {
336	245	.reg_off = HHI_HDMI_PLL_CNTL,
337		- .shift = 29,
	246	+ .shift = 28,
338	247	.width = 1,
339	248	},
340	249	},
341	250	.hw.init = &(struct clk_init_data){
342		- .name = "hdmi_pll",
	251	+ .name = "hdmi_pll_dco",
343	252	.ops = &meson_clk_pll_ro_ops,
344		- .parent_names = (const char *[]){ "xtal" },
	253	+ .parent_data = &(const struct clk_parent_data) {
	254	+ .fw_name = "xtal",
	255	+ },
345	256	.num_parents = 1,
346	257	/*
347	258	* Display directly handle hdmi pll registers ATM, we need
..	..	@@ -351,8 +262,121 @@
351	262	},
352	263	};
353	264
354		-static struct clk_regmap gxbb_sys_pll = {
	265	+static struct clk_regmap gxbb_hdmi_pll_od = {
	266	+ .data = &(struct clk_regmap_div_data){
	267	+ .offset = HHI_HDMI_PLL_CNTL2,
	268	+ .shift = 16,
	269	+ .width = 2,
	270	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	271	+ },
	272	+ .hw.init = &(struct clk_init_data){
	273	+ .name = "hdmi_pll_od",
	274	+ .ops = &clk_regmap_divider_ro_ops,
	275	+ .parent_hws = (const struct clk_hw *[]) {
	276	+ &gxbb_hdmi_pll_dco.hw
	277	+ },
	278	+ .num_parents = 1,
	279	+ .flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
	280	+ },
	281	+};
	282	+
	283	+static struct clk_regmap gxbb_hdmi_pll_od2 = {
	284	+ .data = &(struct clk_regmap_div_data){
	285	+ .offset = HHI_HDMI_PLL_CNTL2,
	286	+ .shift = 22,
	287	+ .width = 2,
	288	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	289	+ },
	290	+ .hw.init = &(struct clk_init_data){
	291	+ .name = "hdmi_pll_od2",
	292	+ .ops = &clk_regmap_divider_ro_ops,
	293	+ .parent_hws = (const struct clk_hw *[]) {
	294	+ &gxbb_hdmi_pll_od.hw
	295	+ },
	296	+ .num_parents = 1,
	297	+ .flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
	298	+ },
	299	+};
	300	+
	301	+static struct clk_regmap gxbb_hdmi_pll = {
	302	+ .data = &(struct clk_regmap_div_data){
	303	+ .offset = HHI_HDMI_PLL_CNTL2,
	304	+ .shift = 18,
	305	+ .width = 2,
	306	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	307	+ },
	308	+ .hw.init = &(struct clk_init_data){
	309	+ .name = "hdmi_pll",
	310	+ .ops = &clk_regmap_divider_ro_ops,
	311	+ .parent_hws = (const struct clk_hw *[]) {
	312	+ &gxbb_hdmi_pll_od2.hw
	313	+ },
	314	+ .num_parents = 1,
	315	+ .flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
	316	+ },
	317	+};
	318	+
	319	+static struct clk_regmap gxl_hdmi_pll_od = {
	320	+ .data = &(struct clk_regmap_div_data){
	321	+ .offset = HHI_HDMI_PLL_CNTL + 8,
	322	+ .shift = 21,
	323	+ .width = 2,
	324	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	325	+ },
	326	+ .hw.init = &(struct clk_init_data){
	327	+ .name = "hdmi_pll_od",
	328	+ .ops = &clk_regmap_divider_ro_ops,
	329	+ .parent_hws = (const struct clk_hw *[]) {
	330	+ &gxl_hdmi_pll_dco.hw
	331	+ },
	332	+ .num_parents = 1,
	333	+ .flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
	334	+ },
	335	+};
	336	+
	337	+static struct clk_regmap gxl_hdmi_pll_od2 = {
	338	+ .data = &(struct clk_regmap_div_data){
	339	+ .offset = HHI_HDMI_PLL_CNTL + 8,
	340	+ .shift = 23,
	341	+ .width = 2,
	342	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	343	+ },
	344	+ .hw.init = &(struct clk_init_data){
	345	+ .name = "hdmi_pll_od2",
	346	+ .ops = &clk_regmap_divider_ro_ops,
	347	+ .parent_hws = (const struct clk_hw *[]) {
	348	+ &gxl_hdmi_pll_od.hw
	349	+ },
	350	+ .num_parents = 1,
	351	+ .flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
	352	+ },
	353	+};
	354	+
	355	+static struct clk_regmap gxl_hdmi_pll = {
	356	+ .data = &(struct clk_regmap_div_data){
	357	+ .offset = HHI_HDMI_PLL_CNTL + 8,
	358	+ .shift = 19,
	359	+ .width = 2,
	360	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	361	+ },
	362	+ .hw.init = &(struct clk_init_data){
	363	+ .name = "hdmi_pll",
	364	+ .ops = &clk_regmap_divider_ro_ops,
	365	+ .parent_hws = (const struct clk_hw *[]) {
	366	+ &gxl_hdmi_pll_od2.hw
	367	+ },
	368	+ .num_parents = 1,
	369	+ .flags = CLK_GET_RATE_NOCACHE \| CLK_SET_RATE_PARENT,
	370	+ },
	371	+};
	372	+
	373	+static struct clk_regmap gxbb_sys_pll_dco = {
355	374	.data = &(struct meson_clk_pll_data){
	375	+ .en = {
	376	+ .reg_off = HHI_SYS_PLL_CNTL,
	377	+ .shift = 30,
	378	+ .width = 1,
	379	+ },
356	380	.m = {
357	381	.reg_off = HHI_SYS_PLL_CNTL,
358	382	.shift = 0,
..	..	@@ -362,11 +386,6 @@
362	386	.reg_off = HHI_SYS_PLL_CNTL,
363	387	.shift = 9,
364	388	.width = 5,
365		- },
366		- .od = {
367		- .reg_off = HHI_SYS_PLL_CNTL,
368		- .shift = 10,
369		- .width = 2,
370	389	},
371	390	.l = {
372	391	.reg_off = HHI_SYS_PLL_CNTL,
..	..	@@ -380,10 +399,30 @@
380	399	},
381	400	},
382	401	.hw.init = &(struct clk_init_data){
383		- .name = "sys_pll",
	402	+ .name = "sys_pll_dco",
384	403	.ops = &meson_clk_pll_ro_ops,
385		- .parent_names = (const char *[]){ "xtal" },
	404	+ .parent_data = &(const struct clk_parent_data) {
	405	+ .fw_name = "xtal",
	406	+ },
386	407	.num_parents = 1,
	408	+ },
	409	+};
	410	+
	411	+static struct clk_regmap gxbb_sys_pll = {
	412	+ .data = &(struct clk_regmap_div_data){
	413	+ .offset = HHI_SYS_PLL_CNTL,
	414	+ .shift = 10,
	415	+ .width = 2,
	416	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	417	+ },
	418	+ .hw.init = &(struct clk_init_data){
	419	+ .name = "sys_pll",
	420	+ .ops = &clk_regmap_divider_ro_ops,
	421	+ .parent_hws = (const struct clk_hw *[]) {
	422	+ &gxbb_sys_pll_dco.hw
	423	+ },
	424	+ .num_parents = 1,
	425	+ .flags = CLK_SET_RATE_PARENT,
387	426	},
388	427	};
389	428
..	..	@@ -391,11 +430,15 @@
391	430	{ .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
392	431	{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
393	432	{ .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
394		- { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 },
395	433	};
396	434
397		-static struct clk_regmap gxbb_gp0_pll = {
	435	+static struct clk_regmap gxbb_gp0_pll_dco = {
398	436	.data = &(struct meson_clk_pll_data){
	437	+ .en = {
	438	+ .reg_off = HHI_GP0_PLL_CNTL,
	439	+ .shift = 30,
	440	+ .width = 1,
	441	+ },
399	442	.m = {
400	443	.reg_off = HHI_GP0_PLL_CNTL,
401	444	.shift = 0,
..	..	@@ -405,11 +448,6 @@
405	448	.reg_off = HHI_GP0_PLL_CNTL,
406	449	.shift = 9,
407	450	.width = 5,
408		- },
409		- .od = {
410		- .reg_off = HHI_GP0_PLL_CNTL,
411		- .shift = 16,
412		- .width = 2,
413	451	},
414	452	.l = {
415	453	.reg_off = HHI_GP0_PLL_CNTL,
..	..	@@ -421,14 +459,16 @@
421	459	.shift = 29,
422	460	.width = 1,
423	461	},
424		- .table = gxbb_gp0_pll_rate_table,
	462	+ .table = gxbb_gp0_pll_params_table,
425	463	.init_regs = gxbb_gp0_init_regs,
426	464	.init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
427	465	},
428	466	.hw.init = &(struct clk_init_data){
429		- .name = "gp0_pll",
	467	+ .name = "gp0_pll_dco",
430	468	.ops = &meson_clk_pll_ops,
431		- .parent_names = (const char *[]){ "xtal" },
	469	+ .parent_data = &(const struct clk_parent_data) {
	470	+ .fw_name = "xtal",
	471	+ },
432	472	.num_parents = 1,
433	473	},
434	474	};
..	..	@@ -439,11 +479,15 @@
439	479	{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
440	480	{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
441	481	{ .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
442		- { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
443	482	};
444	483
445		-static struct clk_regmap gxl_gp0_pll = {
	484	+static struct clk_regmap gxl_gp0_pll_dco = {
446	485	.data = &(struct meson_clk_pll_data){
	486	+ .en = {
	487	+ .reg_off = HHI_GP0_PLL_CNTL,
	488	+ .shift = 30,
	489	+ .width = 1,
	490	+ },
447	491	.m = {
448	492	.reg_off = HHI_GP0_PLL_CNTL,
449	493	.shift = 0,
..	..	@@ -453,11 +497,6 @@
453	497	.reg_off = HHI_GP0_PLL_CNTL,
454	498	.shift = 9,
455	499	.width = 5,
456		- },
457		- .od = {
458		- .reg_off = HHI_GP0_PLL_CNTL,
459		- .shift = 16,
460		- .width = 2,
461	500	},
462	501	.frac = {
463	502	.reg_off = HHI_GP0_PLL_CNTL1,
..	..	@@ -474,15 +513,43 @@
474	513	.shift = 29,
475	514	.width = 1,
476	515	},
477		- .table = gxl_gp0_pll_rate_table,
	516	+ .table = gxl_gp0_pll_params_table,
478	517	.init_regs = gxl_gp0_init_regs,
479	518	.init_count = ARRAY_SIZE(gxl_gp0_init_regs),
480	519	},
481	520	.hw.init = &(struct clk_init_data){
482		- .name = "gp0_pll",
	521	+ .name = "gp0_pll_dco",
483	522	.ops = &meson_clk_pll_ops,
484		- .parent_names = (const char *[]){ "xtal" },
	523	+ .parent_data = &(const struct clk_parent_data) {
	524	+ .fw_name = "xtal",
	525	+ },
485	526	.num_parents = 1,
	527	+ },
	528	+};
	529	+
	530	+static struct clk_regmap gxbb_gp0_pll = {
	531	+ .data = &(struct clk_regmap_div_data){
	532	+ .offset = HHI_GP0_PLL_CNTL,
	533	+ .shift = 16,
	534	+ .width = 2,
	535	+ .flags = CLK_DIVIDER_POWER_OF_TWO,
	536	+ },
	537	+ .hw.init = &(struct clk_init_data){
	538	+ .name = "gp0_pll",
	539	+ .ops = &clk_regmap_divider_ops,
	540	+ .parent_data = &(const struct clk_parent_data) {
	541	+ /*
	542	+ * Note:
	543	+ * GXL and GXBB have different gp0_pll_dco (with
	544	+ * different struct clk_hw). We fallback to the global
	545	+ * naming string mechanism so gp0_pll picks up the
	546	+ * appropriate one.
	547	+ */
	548	+ .name = "gp0_pll_dco",
	549	+ .index = -1,
	550	+ },
	551	+ .num_parents = 1,
	552	+ .flags = CLK_SET_RATE_PARENT,
486	553	},
487	554	};
488	555
..	..	@@ -492,7 +559,9 @@
492	559	.hw.init = &(struct clk_init_data){
493	560	.name = "fclk_div2_div",
494	561	.ops = &clk_fixed_factor_ops,
495		- .parent_names = (const char *[]){ "fixed_pll" },
	562	+ .parent_hws = (const struct clk_hw *[]) {
	563	+ &gxbb_fixed_pll.hw
	564	+ },
496	565	.num_parents = 1,
497	566	},
498	567	};
..	..	@@ -505,7 +574,9 @@
505	574	.hw.init = &(struct clk_init_data){
506	575	.name = "fclk_div2",
507	576	.ops = &clk_regmap_gate_ops,
508		- .parent_names = (const char *[]){ "fclk_div2_div" },
	577	+ .parent_hws = (const struct clk_hw *[]) {
	578	+ &gxbb_fclk_div2_div.hw
	579	+ },
509	580	.num_parents = 1,
510	581	.flags = CLK_IS_CRITICAL,
511	582	},
..	..	@@ -517,7 +588,7 @@
517	588	.hw.init = &(struct clk_init_data){
518	589	.name = "fclk_div3_div",
519	590	.ops = &clk_fixed_factor_ops,
520		- .parent_names = (const char *[]){ "fixed_pll" },
	591	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
521	592	.num_parents = 1,
522	593	},
523	594	};
..	..	@@ -530,7 +601,9 @@
530	601	.hw.init = &(struct clk_init_data){
531	602	.name = "fclk_div3",
532	603	.ops = &clk_regmap_gate_ops,
533		- .parent_names = (const char *[]){ "fclk_div3_div" },
	604	+ .parent_hws = (const struct clk_hw *[]) {
	605	+ &gxbb_fclk_div3_div.hw
	606	+ },
534	607	.num_parents = 1,
535	608	/*
536	609	* FIXME:
..	..	@@ -553,7 +626,7 @@
553	626	.hw.init = &(struct clk_init_data){
554	627	.name = "fclk_div4_div",
555	628	.ops = &clk_fixed_factor_ops,
556		- .parent_names = (const char *[]){ "fixed_pll" },
	629	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
557	630	.num_parents = 1,
558	631	},
559	632	};
..	..	@@ -566,7 +639,9 @@
566	639	.hw.init = &(struct clk_init_data){
567	640	.name = "fclk_div4",
568	641	.ops = &clk_regmap_gate_ops,
569		- .parent_names = (const char *[]){ "fclk_div4_div" },
	642	+ .parent_hws = (const struct clk_hw *[]) {
	643	+ &gxbb_fclk_div4_div.hw
	644	+ },
570	645	.num_parents = 1,
571	646	},
572	647	};
..	..	@@ -577,7 +652,7 @@
577	652	.hw.init = &(struct clk_init_data){
578	653	.name = "fclk_div5_div",
579	654	.ops = &clk_fixed_factor_ops,
580		- .parent_names = (const char *[]){ "fixed_pll" },
	655	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
581	656	.num_parents = 1,
582	657	},
583	658	};
..	..	@@ -590,7 +665,9 @@
590	665	.hw.init = &(struct clk_init_data){
591	666	.name = "fclk_div5",
592	667	.ops = &clk_regmap_gate_ops,
593		- .parent_names = (const char *[]){ "fclk_div5_div" },
	668	+ .parent_hws = (const struct clk_hw *[]) {
	669	+ &gxbb_fclk_div5_div.hw
	670	+ },
594	671	.num_parents = 1,
595	672	},
596	673	};
..	..	@@ -601,7 +678,7 @@
601	678	.hw.init = &(struct clk_init_data){
602	679	.name = "fclk_div7_div",
603	680	.ops = &clk_fixed_factor_ops,
604		- .parent_names = (const char *[]){ "fixed_pll" },
	681	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
605	682	.num_parents = 1,
606	683	},
607	684	};
..	..	@@ -614,7 +691,9 @@
614	691	.hw.init = &(struct clk_init_data){
615	692	.name = "fclk_div7",
616	693	.ops = &clk_regmap_gate_ops,
617		- .parent_names = (const char *[]){ "fclk_div7_div" },
	694	+ .parent_hws = (const struct clk_hw *[]) {
	695	+ &gxbb_fclk_div7_div.hw
	696	+ },
618	697	.num_parents = 1,
619	698	},
620	699	};
..	..	@@ -628,12 +707,41 @@
628	707	.hw.init = &(struct clk_init_data){
629	708	.name = "mpll_prediv",
630	709	.ops = &clk_regmap_divider_ro_ops,
631		- .parent_names = (const char *[]){ "fixed_pll" },
	710	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
632	711	.num_parents = 1,
633	712	},
634	713	};
635	714
636	715	static struct clk_regmap gxbb_mpll0_div = {
	716	+ .data = &(struct meson_clk_mpll_data){
	717	+ .sdm = {
	718	+ .reg_off = HHI_MPLL_CNTL7,
	719	+ .shift = 0,
	720	+ .width = 14,
	721	+ },
	722	+ .sdm_en = {
	723	+ .reg_off = HHI_MPLL_CNTL,
	724	+ .shift = 25,
	725	+ .width = 1,
	726	+ },
	727	+ .n2 = {
	728	+ .reg_off = HHI_MPLL_CNTL7,
	729	+ .shift = 16,
	730	+ .width = 9,
	731	+ },
	732	+ .lock = &meson_clk_lock,
	733	+ },
	734	+ .hw.init = &(struct clk_init_data){
	735	+ .name = "mpll0_div",
	736	+ .ops = &meson_clk_mpll_ops,
	737	+ .parent_hws = (const struct clk_hw *[]) {
	738	+ &gxbb_mpll_prediv.hw
	739	+ },
	740	+ .num_parents = 1,
	741	+ },
	742	+};
	743	+
	744	+static struct clk_regmap gxl_mpll0_div = {
637	745	.data = &(struct meson_clk_mpll_data){
638	746	.sdm = {
639	747	.reg_off = HHI_MPLL_CNTL7,
..	..	@@ -655,7 +763,9 @@
655	763	.hw.init = &(struct clk_init_data){
656	764	.name = "mpll0_div",
657	765	.ops = &meson_clk_mpll_ops,
658		- .parent_names = (const char *[]){ "mpll_prediv" },
	766	+ .parent_hws = (const struct clk_hw *[]) {
	767	+ &gxbb_mpll_prediv.hw
	768	+ },
659	769	.num_parents = 1,
660	770	},
661	771	};
..	..	@@ -668,7 +778,16 @@
668	778	.hw.init = &(struct clk_init_data){
669	779	.name = "mpll0",
670	780	.ops = &clk_regmap_gate_ops,
671		- .parent_names = (const char *[]){ "mpll0_div" },
	781	+ .parent_data = &(const struct clk_parent_data) {
	782	+ /*
	783	+ * Note:
	784	+ * GXL and GXBB have different SDM_EN registers. We
	785	+ * fallback to the global naming string mechanism so
	786	+ * mpll0_div picks up the appropriate one.
	787	+ */
	788	+ .name = "mpll0_div",
	789	+ .index = -1,
	790	+ },
672	791	.num_parents = 1,
673	792	.flags = CLK_SET_RATE_PARENT,
674	793	},
..	..	@@ -696,7 +815,9 @@
696	815	.hw.init = &(struct clk_init_data){
697	816	.name = "mpll1_div",
698	817	.ops = &meson_clk_mpll_ops,
699		- .parent_names = (const char *[]){ "mpll_prediv" },
	818	+ .parent_hws = (const struct clk_hw *[]) {
	819	+ &gxbb_mpll_prediv.hw
	820	+ },
700	821	.num_parents = 1,
701	822	},
702	823	};
..	..	@@ -709,7 +830,7 @@
709	830	.hw.init = &(struct clk_init_data){
710	831	.name = "mpll1",
711	832	.ops = &clk_regmap_gate_ops,
712		- .parent_names = (const char *[]){ "mpll1_div" },
	833	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
713	834	.num_parents = 1,
714	835	.flags = CLK_SET_RATE_PARENT,
715	836	},
..	..	@@ -737,7 +858,9 @@
737	858	.hw.init = &(struct clk_init_data){
738	859	.name = "mpll2_div",
739	860	.ops = &meson_clk_mpll_ops,
740		- .parent_names = (const char *[]){ "mpll_prediv" },
	861	+ .parent_hws = (const struct clk_hw *[]) {
	862	+ &gxbb_mpll_prediv.hw
	863	+ },
741	864	.num_parents = 1,
742	865	},
743	866	};
..	..	@@ -750,16 +873,21 @@
750	873	.hw.init = &(struct clk_init_data){
751	874	.name = "mpll2",
752	875	.ops = &clk_regmap_gate_ops,
753		- .parent_names = (const char *[]){ "mpll2_div" },
	876	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
754	877	.num_parents = 1,
755	878	.flags = CLK_SET_RATE_PARENT,
756	879	},
757	880	};
758	881
759	882	static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
760		-static const char * const clk81_parent_names[] = {
761		- "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
762		- "fclk_div3", "fclk_div5"
	883	+static const struct clk_parent_data clk81_parent_data[] = {
	884	+ { .fw_name = "xtal", },
	885	+ { .hw = &gxbb_fclk_div7.hw },
	886	+ { .hw = &gxbb_mpll1.hw },
	887	+ { .hw = &gxbb_mpll2.hw },
	888	+ { .hw = &gxbb_fclk_div4.hw },
	889	+ { .hw = &gxbb_fclk_div3.hw },
	890	+ { .hw = &gxbb_fclk_div5.hw },
763	891	};
764	892
765	893	static struct clk_regmap gxbb_mpeg_clk_sel = {
..	..	@@ -777,8 +905,8 @@
777	905	* xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
778	906	* fclk_div4, fclk_div3, fclk_div5
779	907	*/
780		- .parent_names = clk81_parent_names,
781		- .num_parents = ARRAY_SIZE(clk81_parent_names),
	908	+ .parent_data = clk81_parent_data,
	909	+ .num_parents = ARRAY_SIZE(clk81_parent_data),
782	910	},
783	911	};
784	912
..	..	@@ -791,7 +919,9 @@
791	919	.hw.init = &(struct clk_init_data){
792	920	.name = "mpeg_clk_div",
793	921	.ops = &clk_regmap_divider_ro_ops,
794		- .parent_names = (const char *[]){ "mpeg_clk_sel" },
	922	+ .parent_hws = (const struct clk_hw *[]) {
	923	+ &gxbb_mpeg_clk_sel.hw
	924	+ },
795	925	.num_parents = 1,
796	926	},
797	927	};
..	..	@@ -805,7 +935,9 @@
805	935	.hw.init = &(struct clk_init_data){
806	936	.name = "clk81",
807	937	.ops = &clk_regmap_gate_ops,
808		- .parent_names = (const char *[]){ "mpeg_clk_div" },
	938	+ .parent_hws = (const struct clk_hw *[]) {
	939	+ &gxbb_mpeg_clk_div.hw
	940	+ },
809	941	.num_parents = 1,
810	942	.flags = CLK_IS_CRITICAL,
811	943	},
..	..	@@ -821,7 +953,10 @@
821	953	.name = "sar_adc_clk_sel",
822	954	.ops = &clk_regmap_mux_ops,
823	955	/* NOTE: The datasheet doesn't list the parents for bit 10 */
824		- .parent_names = (const char *[]){ "xtal", "clk81", },
	956	+ .parent_data = (const struct clk_parent_data []) {
	957	+ { .fw_name = "xtal", },
	958	+ { .hw = &gxbb_clk81.hw },
	959	+ },
825	960	.num_parents = 2,
826	961	},
827	962	};
..	..	@@ -835,7 +970,9 @@
835	970	.hw.init = &(struct clk_init_data){
836	971	.name = "sar_adc_clk_div",
837	972	.ops = &clk_regmap_divider_ops,
838		- .parent_names = (const char *[]){ "sar_adc_clk_sel" },
	973	+ .parent_hws = (const struct clk_hw *[]) {
	974	+ &gxbb_sar_adc_clk_sel.hw
	975	+ },
839	976	.num_parents = 1,
840	977	.flags = CLK_SET_RATE_PARENT,
841	978	},
..	..	@@ -849,7 +986,9 @@
849	986	.hw.init = &(struct clk_init_data){
850	987	.name = "sar_adc_clk",
851	988	.ops = &clk_regmap_gate_ops,
852		- .parent_names = (const char *[]){ "sar_adc_clk_div" },
	989	+ .parent_hws = (const struct clk_hw *[]) {
	990	+ &gxbb_sar_adc_clk_div.hw
	991	+ },
853	992	.num_parents = 1,
854	993	.flags = CLK_SET_RATE_PARENT,
855	994	},
..	..	@@ -857,12 +996,20 @@
857	996
858	997	/*
859	998	* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
860		- * muxed by a glitch-free switch.
	999	+ * muxed by a glitch-free switch. The CCF can manage this glitch-free
	1000	+ * mux because it does top-to-bottom updates the each clock tree and
	1001	+ * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
861	1002	*/
862	1003
863		-static const char * const gxbb_mali_0_1_parent_names[] = {
864		- "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
865		- "fclk_div4", "fclk_div3", "fclk_div5"
	1004	+static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
	1005	+ { .fw_name = "xtal", },
	1006	+ { .hw = &gxbb_gp0_pll.hw },
	1007	+ { .hw = &gxbb_mpll2.hw },
	1008	+ { .hw = &gxbb_mpll1.hw },
	1009	+ { .hw = &gxbb_fclk_div7.hw },
	1010	+ { .hw = &gxbb_fclk_div4.hw },
	1011	+ { .hw = &gxbb_fclk_div3.hw },
	1012	+ { .hw = &gxbb_fclk_div5.hw },
866	1013	};
867	1014
868	1015	static struct clk_regmap gxbb_mali_0_sel = {
..	..	@@ -874,14 +1021,15 @@
874	1021	.hw.init = &(struct clk_init_data){
875	1022	.name = "mali_0_sel",
876	1023	.ops = &clk_regmap_mux_ops,
877		- /*
878		- * bits 10:9 selects from 8 possible parents:
879		- * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
880		- * fclk_div4, fclk_div3, fclk_div5
881		- */
882		- .parent_names = gxbb_mali_0_1_parent_names,
	1024	+ .parent_data = gxbb_mali_0_1_parent_data,
883	1025	.num_parents = 8,
884		- .flags = CLK_SET_RATE_NO_REPARENT,
	1026	+ /*
	1027	+ * Don't request the parent to change the rate because
	1028	+ * all GPU frequencies can be derived from the fclk_*
	1029	+ * clocks and one special GP0_PLL setting. This is
	1030	+ * important because we need the MPLL clocks for audio.
	1031	+ */
	1032	+ .flags = 0,
885	1033	},
886	1034	};
887	1035
..	..	@@ -894,9 +1042,11 @@
894	1042	.hw.init = &(struct clk_init_data){
895	1043	.name = "mali_0_div",
896	1044	.ops = &clk_regmap_divider_ops,
897		- .parent_names = (const char *[]){ "mali_0_sel" },
	1045	+ .parent_hws = (const struct clk_hw *[]) {
	1046	+ &gxbb_mali_0_sel.hw
	1047	+ },
898	1048	.num_parents = 1,
899		- .flags = CLK_SET_RATE_NO_REPARENT,
	1049	+ .flags = CLK_SET_RATE_PARENT,
900	1050	},
901	1051	};
902	1052
..	..	@@ -908,9 +1058,11 @@
908	1058	.hw.init = &(struct clk_init_data){
909	1059	.name = "mali_0",
910	1060	.ops = &clk_regmap_gate_ops,
911		- .parent_names = (const char *[]){ "mali_0_div" },
	1061	+ .parent_hws = (const struct clk_hw *[]) {
	1062	+ &gxbb_mali_0_div.hw
	1063	+ },
912	1064	.num_parents = 1,
913		- .flags = CLK_SET_RATE_PARENT,
	1065	+ .flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
914	1066	},
915	1067	};
916	1068
..	..	@@ -923,14 +1075,15 @@
923	1075	.hw.init = &(struct clk_init_data){
924	1076	.name = "mali_1_sel",
925	1077	.ops = &clk_regmap_mux_ops,
926		- /*
927		- * bits 10:9 selects from 8 possible parents:
928		- * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
929		- * fclk_div4, fclk_div3, fclk_div5
930		- */
931		- .parent_names = gxbb_mali_0_1_parent_names,
	1078	+ .parent_data = gxbb_mali_0_1_parent_data,
932	1079	.num_parents = 8,
933		- .flags = CLK_SET_RATE_NO_REPARENT,
	1080	+ /*
	1081	+ * Don't request the parent to change the rate because
	1082	+ * all GPU frequencies can be derived from the fclk_*
	1083	+ * clocks and one special GP0_PLL setting. This is
	1084	+ * important because we need the MPLL clocks for audio.
	1085	+ */
	1086	+ .flags = 0,
934	1087	},
935	1088	};
936	1089
..	..	@@ -943,9 +1096,11 @@
943	1096	.hw.init = &(struct clk_init_data){
944	1097	.name = "mali_1_div",
945	1098	.ops = &clk_regmap_divider_ops,
946		- .parent_names = (const char *[]){ "mali_1_sel" },
	1099	+ .parent_hws = (const struct clk_hw *[]) {
	1100	+ &gxbb_mali_1_sel.hw
	1101	+ },
947	1102	.num_parents = 1,
948		- .flags = CLK_SET_RATE_NO_REPARENT,
	1103	+ .flags = CLK_SET_RATE_PARENT,
949	1104	},
950	1105	};
951	1106
..	..	@@ -957,14 +1112,17 @@
957	1112	.hw.init = &(struct clk_init_data){
958	1113	.name = "mali_1",
959	1114	.ops = &clk_regmap_gate_ops,
960		- .parent_names = (const char *[]){ "mali_1_div" },
	1115	+ .parent_hws = (const struct clk_hw *[]) {
	1116	+ &gxbb_mali_1_div.hw
	1117	+ },
961	1118	.num_parents = 1,
962		- .flags = CLK_SET_RATE_PARENT,
	1119	+ .flags = CLK_SET_RATE_GATE \| CLK_SET_RATE_PARENT,
963	1120	},
964	1121	};
965	1122
966		-static const char * const gxbb_mali_parent_names[] = {
967		- "mali_0", "mali_1"
	1123	+static const struct clk_hw *gxbb_mali_parent_hws[] = {
	1124	+ &gxbb_mali_0.hw,
	1125	+ &gxbb_mali_1.hw,
968	1126	};
969	1127
970	1128	static struct clk_regmap gxbb_mali = {
..	..	@@ -976,9 +1134,9 @@
976	1134	.hw.init = &(struct clk_init_data){
977	1135	.name = "mali",
978	1136	.ops = &clk_regmap_mux_ops,
979		- .parent_names = gxbb_mali_parent_names,
	1137	+ .parent_hws = gxbb_mali_parent_hws,
980	1138	.num_parents = 2,
981		- .flags = CLK_SET_RATE_NO_REPARENT,
	1139	+ .flags = CLK_SET_RATE_PARENT,
982	1140	},
983	1141	};
984	1142
..	..	@@ -993,7 +1151,11 @@
993	1151	.hw.init = &(struct clk_init_data){
994	1152	.name = "cts_amclk_sel",
995	1153	.ops = &clk_regmap_mux_ops,
996		- .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
	1154	+ .parent_hws = (const struct clk_hw *[]) {
	1155	+ &gxbb_mpll0.hw,
	1156	+ &gxbb_mpll1.hw,
	1157	+ &gxbb_mpll2.hw,
	1158	+ },
997	1159	.num_parents = 3,
998	1160	},
999	1161	};
..	..	@@ -1008,7 +1170,9 @@
1008	1170	.hw.init = &(struct clk_init_data){
1009	1171	.name = "cts_amclk_div",
1010	1172	.ops = &clk_regmap_divider_ops,
1011		- .parent_names = (const char *[]){ "cts_amclk_sel" },
	1173	+ .parent_hws = (const struct clk_hw *[]) {
	1174	+ &gxbb_cts_amclk_sel.hw
	1175	+ },
1012	1176	.num_parents = 1,
1013	1177	.flags = CLK_SET_RATE_PARENT,
1014	1178	},
..	..	@@ -1022,7 +1186,9 @@
1022	1186	.hw.init = &(struct clk_init_data){
1023	1187	.name = "cts_amclk",
1024	1188	.ops = &clk_regmap_gate_ops,
1025		- .parent_names = (const char *[]){ "cts_amclk_div" },
	1189	+ .parent_hws = (const struct clk_hw *[]) {
	1190	+ &gxbb_cts_amclk_div.hw
	1191	+ },
1026	1192	.num_parents = 1,
1027	1193	.flags = CLK_SET_RATE_PARENT,
1028	1194	},
..	..	@@ -1039,7 +1205,11 @@
1039	1205	.hw.init = &(struct clk_init_data) {
1040	1206	.name = "cts_mclk_i958_sel",
1041	1207	.ops = &clk_regmap_mux_ops,
1042		- .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
	1208	+ .parent_hws = (const struct clk_hw *[]) {
	1209	+ &gxbb_mpll0.hw,
	1210	+ &gxbb_mpll1.hw,
	1211	+ &gxbb_mpll2.hw,
	1212	+ },
1043	1213	.num_parents = 3,
1044	1214	},
1045	1215	};
..	..	@@ -1054,7 +1224,9 @@
1054	1224	.hw.init = &(struct clk_init_data) {
1055	1225	.name = "cts_mclk_i958_div",
1056	1226	.ops = &clk_regmap_divider_ops,
1057		- .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
	1227	+ .parent_hws = (const struct clk_hw *[]) {
	1228	+ &gxbb_cts_mclk_i958_sel.hw
	1229	+ },
1058	1230	.num_parents = 1,
1059	1231	.flags = CLK_SET_RATE_PARENT,
1060	1232	},
..	..	@@ -1068,7 +1240,9 @@
1068	1240	.hw.init = &(struct clk_init_data){
1069	1241	.name = "cts_mclk_i958",
1070	1242	.ops = &clk_regmap_gate_ops,
1071		- .parent_names = (const char *[]){ "cts_mclk_i958_div" },
	1243	+ .parent_hws = (const struct clk_hw *[]) {
	1244	+ &gxbb_cts_mclk_i958_div.hw
	1245	+ },
1072	1246	.num_parents = 1,
1073	1247	.flags = CLK_SET_RATE_PARENT,
1074	1248	},
..	..	@@ -1083,13 +1257,43 @@
1083	1257	.hw.init = &(struct clk_init_data){
1084	1258	.name = "cts_i958",
1085	1259	.ops = &clk_regmap_mux_ops,
1086		- .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
	1260	+ .parent_hws = (const struct clk_hw *[]) {
	1261	+ &gxbb_cts_amclk.hw,
	1262	+ &gxbb_cts_mclk_i958.hw
	1263	+ },
1087	1264	.num_parents = 2,
1088	1265	/*
1089	1266	*The parent is specific to origin of the audio data. Let the
1090	1267	* consumer choose the appropriate parent
1091	1268	*/
1092	1269	.flags = CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
	1270	+ },
	1271	+};
	1272	+
	1273	+static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
	1274	+ { .fw_name = "xtal", },
	1275	+ /*
	1276	+ * FIXME: This clock is provided by the ao clock controller but the
	1277	+ * clock is not yet part of the binding of this controller, so string
	1278	+ * name must be use to set this parent.
	1279	+ */
	1280	+ { .name = "cts_slow_oscin", .index = -1 },
	1281	+ { .hw = &gxbb_fclk_div3.hw },
	1282	+ { .hw = &gxbb_fclk_div5.hw },
	1283	+};
	1284	+
	1285	+static struct clk_regmap gxbb_32k_clk_sel = {
	1286	+ .data = &(struct clk_regmap_mux_data){
	1287	+ .offset = HHI_32K_CLK_CNTL,
	1288	+ .mask = 0x3,
	1289	+ .shift = 16,
	1290	+ },
	1291	+ .hw.init = &(struct clk_init_data){
	1292	+ .name = "32k_clk_sel",
	1293	+ .ops = &clk_regmap_mux_ops,
	1294	+ .parent_data = gxbb_32k_clk_parent_data,
	1295	+ .num_parents = 4,
	1296	+ .flags = CLK_SET_RATE_PARENT,
1093	1297	},
1094	1298	};
1095	1299
..	..	@@ -1102,7 +1306,9 @@
1102	1306	.hw.init = &(struct clk_init_data){
1103	1307	.name = "32k_clk_div",
1104	1308	.ops = &clk_regmap_divider_ops,
1105		- .parent_names = (const char *[]){ "32k_clk_sel" },
	1309	+ .parent_hws = (const struct clk_hw *[]) {
	1310	+ &gxbb_32k_clk_sel.hw
	1311	+ },
1106	1312	.num_parents = 1,
1107	1313	.flags = CLK_SET_RATE_PARENT \| CLK_DIVIDER_ROUND_CLOSEST,
1108	1314	},
..	..	@@ -1116,34 +1322,20 @@
1116	1322	.hw.init = &(struct clk_init_data){
1117	1323	.name = "32k_clk",
1118	1324	.ops = &clk_regmap_gate_ops,
1119		- .parent_names = (const char *[]){ "32k_clk_div" },
	1325	+ .parent_hws = (const struct clk_hw *[]) {
	1326	+ &gxbb_32k_clk_div.hw
	1327	+ },
1120	1328	.num_parents = 1,
1121	1329	.flags = CLK_SET_RATE_PARENT,
1122	1330	},
1123	1331	};
1124	1332
1125		-static const char * const gxbb_32k_clk_parent_names[] = {
1126		- "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1127		-};
1128		-
1129		-static struct clk_regmap gxbb_32k_clk_sel = {
1130		- .data = &(struct clk_regmap_mux_data){
1131		- .offset = HHI_32K_CLK_CNTL,
1132		- .mask = 0x3,
1133		- .shift = 16,
1134		- },
1135		- .hw.init = &(struct clk_init_data){
1136		- .name = "32k_clk_sel",
1137		- .ops = &clk_regmap_mux_ops,
1138		- .parent_names = gxbb_32k_clk_parent_names,
1139		- .num_parents = 4,
1140		- .flags = CLK_SET_RATE_PARENT,
1141		- },
1142		-};
1143		-
1144		-static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
1145		- "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1146		-
	1333	+static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
	1334	+ { .fw_name = "xtal", },
	1335	+ { .hw = &gxbb_fclk_div2.hw },
	1336	+ { .hw = &gxbb_fclk_div3.hw },
	1337	+ { .hw = &gxbb_fclk_div5.hw },
	1338	+ { .hw = &gxbb_fclk_div7.hw },
1147	1339	/*
1148	1340	* Following these parent clocks, we should also have had mpll2, mpll3
1149	1341	* and gp0_pll but these clocks are too precious to be used here. All
..	..	@@ -1162,8 +1354,8 @@
1162	1354	.hw.init = &(struct clk_init_data) {
1163	1355	.name = "sd_emmc_a_clk0_sel",
1164	1356	.ops = &clk_regmap_mux_ops,
1165		- .parent_names = gxbb_sd_emmc_clk0_parent_names,
1166		- .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
	1357	+ .parent_data = gxbb_sd_emmc_clk0_parent_data,
	1358	+ .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1167	1359	.flags = CLK_SET_RATE_PARENT,
1168	1360	},
1169	1361	};
..	..	@@ -1178,7 +1370,9 @@
1178	1370	.hw.init = &(struct clk_init_data) {
1179	1371	.name = "sd_emmc_a_clk0_div",
1180	1372	.ops = &clk_regmap_divider_ops,
1181		- .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
	1373	+ .parent_hws = (const struct clk_hw *[]) {
	1374	+ &gxbb_sd_emmc_a_clk0_sel.hw
	1375	+ },
1182	1376	.num_parents = 1,
1183	1377	.flags = CLK_SET_RATE_PARENT,
1184	1378	},
..	..	@@ -1192,7 +1386,9 @@
1192	1386	.hw.init = &(struct clk_init_data){
1193	1387	.name = "sd_emmc_a_clk0",
1194	1388	.ops = &clk_regmap_gate_ops,
1195		- .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
	1389	+ .parent_hws = (const struct clk_hw *[]) {
	1390	+ &gxbb_sd_emmc_a_clk0_div.hw
	1391	+ },
1196	1392	.num_parents = 1,
1197	1393	.flags = CLK_SET_RATE_PARENT,
1198	1394	},
..	..	@@ -1208,8 +1404,8 @@
1208	1404	.hw.init = &(struct clk_init_data) {
1209	1405	.name = "sd_emmc_b_clk0_sel",
1210	1406	.ops = &clk_regmap_mux_ops,
1211		- .parent_names = gxbb_sd_emmc_clk0_parent_names,
1212		- .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
	1407	+ .parent_data = gxbb_sd_emmc_clk0_parent_data,
	1408	+ .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1213	1409	.flags = CLK_SET_RATE_PARENT,
1214	1410	},
1215	1411	};
..	..	@@ -1224,7 +1420,9 @@
1224	1420	.hw.init = &(struct clk_init_data) {
1225	1421	.name = "sd_emmc_b_clk0_div",
1226	1422	.ops = &clk_regmap_divider_ops,
1227		- .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
	1423	+ .parent_hws = (const struct clk_hw *[]) {
	1424	+ &gxbb_sd_emmc_b_clk0_sel.hw
	1425	+ },
1228	1426	.num_parents = 1,
1229	1427	.flags = CLK_SET_RATE_PARENT,
1230	1428	},
..	..	@@ -1238,7 +1436,9 @@
1238	1436	.hw.init = &(struct clk_init_data){
1239	1437	.name = "sd_emmc_b_clk0",
1240	1438	.ops = &clk_regmap_gate_ops,
1241		- .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
	1439	+ .parent_hws = (const struct clk_hw *[]) {
	1440	+ &gxbb_sd_emmc_b_clk0_div.hw
	1441	+ },
1242	1442	.num_parents = 1,
1243	1443	.flags = CLK_SET_RATE_PARENT,
1244	1444	},
..	..	@@ -1254,8 +1454,8 @@
1254	1454	.hw.init = &(struct clk_init_data) {
1255	1455	.name = "sd_emmc_c_clk0_sel",
1256	1456	.ops = &clk_regmap_mux_ops,
1257		- .parent_names = gxbb_sd_emmc_clk0_parent_names,
1258		- .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
	1457	+ .parent_data = gxbb_sd_emmc_clk0_parent_data,
	1458	+ .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1259	1459	.flags = CLK_SET_RATE_PARENT,
1260	1460	},
1261	1461	};
..	..	@@ -1270,7 +1470,9 @@
1270	1470	.hw.init = &(struct clk_init_data) {
1271	1471	.name = "sd_emmc_c_clk0_div",
1272	1472	.ops = &clk_regmap_divider_ops,
1273		- .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
	1473	+ .parent_hws = (const struct clk_hw *[]) {
	1474	+ &gxbb_sd_emmc_c_clk0_sel.hw
	1475	+ },
1274	1476	.num_parents = 1,
1275	1477	.flags = CLK_SET_RATE_PARENT,
1276	1478	},
..	..	@@ -1284,7 +1486,9 @@
1284	1486	.hw.init = &(struct clk_init_data){
1285	1487	.name = "sd_emmc_c_clk0",
1286	1488	.ops = &clk_regmap_gate_ops,
1287		- .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
	1489	+ .parent_hws = (const struct clk_hw *[]) {
	1490	+ &gxbb_sd_emmc_c_clk0_div.hw
	1491	+ },
1288	1492	.num_parents = 1,
1289	1493	.flags = CLK_SET_RATE_PARENT,
1290	1494	},
..	..	@@ -1292,8 +1496,11 @@
1292	1496
1293	1497	/* VPU Clock */
1294	1498
1295		-static const char * const gxbb_vpu_parent_names[] = {
1296		- "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
	1499	+static const struct clk_hw *gxbb_vpu_parent_hws[] = {
	1500	+ &gxbb_fclk_div4.hw,
	1501	+ &gxbb_fclk_div3.hw,
	1502	+ &gxbb_fclk_div5.hw,
	1503	+ &gxbb_fclk_div7.hw,
1297	1504	};
1298	1505
1299	1506	static struct clk_regmap gxbb_vpu_0_sel = {
..	..	@@ -1309,8 +1516,8 @@
1309	1516	* bits 9:10 selects from 4 possible parents:
1310	1517	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1311	1518	*/
1312		- .parent_names = gxbb_vpu_parent_names,
1313		- .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
	1519	+ .parent_hws = gxbb_vpu_parent_hws,
	1520	+ .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1314	1521	.flags = CLK_SET_RATE_NO_REPARENT,
1315	1522	},
1316	1523	};
..	..	@@ -1324,7 +1531,7 @@
1324	1531	.hw.init = &(struct clk_init_data){
1325	1532	.name = "vpu_0_div",
1326	1533	.ops = &clk_regmap_divider_ops,
1327		- .parent_names = (const char *[]){ "vpu_0_sel" },
	1534	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1328	1535	.num_parents = 1,
1329	1536	.flags = CLK_SET_RATE_PARENT,
1330	1537	},
..	..	@@ -1338,7 +1545,7 @@
1338	1545	.hw.init = &(struct clk_init_data) {
1339	1546	.name = "vpu_0",
1340	1547	.ops = &clk_regmap_gate_ops,
1341		- .parent_names = (const char *[]){ "vpu_0_div" },
	1548	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1342	1549	.num_parents = 1,
1343	1550	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1344	1551	},
..	..	@@ -1357,8 +1564,8 @@
1357	1564	* bits 25:26 selects from 4 possible parents:
1358	1565	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1359	1566	*/
1360		- .parent_names = gxbb_vpu_parent_names,
1361		- .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
	1567	+ .parent_hws = gxbb_vpu_parent_hws,
	1568	+ .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1362	1569	.flags = CLK_SET_RATE_NO_REPARENT,
1363	1570	},
1364	1571	};
..	..	@@ -1372,7 +1579,7 @@
1372	1579	.hw.init = &(struct clk_init_data){
1373	1580	.name = "vpu_1_div",
1374	1581	.ops = &clk_regmap_divider_ops,
1375		- .parent_names = (const char *[]){ "vpu_1_sel" },
	1582	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1376	1583	.num_parents = 1,
1377	1584	.flags = CLK_SET_RATE_PARENT,
1378	1585	},
..	..	@@ -1386,7 +1593,7 @@
1386	1593	.hw.init = &(struct clk_init_data) {
1387	1594	.name = "vpu_1",
1388	1595	.ops = &clk_regmap_gate_ops,
1389		- .parent_names = (const char *[]){ "vpu_1_div" },
	1596	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1390	1597	.num_parents = 1,
1391	1598	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1392	1599	},
..	..	@@ -1405,7 +1612,10 @@
1405	1612	* bit 31 selects from 2 possible parents:
1406	1613	* vpu_0 or vpu_1
1407	1614	*/
1408		- .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
	1615	+ .parent_hws = (const struct clk_hw *[]) {
	1616	+ &gxbb_vpu_0.hw,
	1617	+ &gxbb_vpu_1.hw
	1618	+ },
1409	1619	.num_parents = 2,
1410	1620	.flags = CLK_SET_RATE_NO_REPARENT,
1411	1621	},
..	..	@@ -1413,8 +1623,11 @@
1413	1623
1414	1624	/* VAPB Clock */
1415	1625
1416		-static const char * const gxbb_vapb_parent_names[] = {
1417		- "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
	1626	+static const struct clk_hw *gxbb_vapb_parent_hws[] = {
	1627	+ &gxbb_fclk_div4.hw,
	1628	+ &gxbb_fclk_div3.hw,
	1629	+ &gxbb_fclk_div5.hw,
	1630	+ &gxbb_fclk_div7.hw,
1418	1631	};
1419	1632
1420	1633	static struct clk_regmap gxbb_vapb_0_sel = {
..	..	@@ -1430,8 +1643,8 @@
1430	1643	* bits 9:10 selects from 4 possible parents:
1431	1644	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1432	1645	*/
1433		- .parent_names = gxbb_vapb_parent_names,
1434		- .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
	1646	+ .parent_hws = gxbb_vapb_parent_hws,
	1647	+ .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1435	1648	.flags = CLK_SET_RATE_NO_REPARENT,
1436	1649	},
1437	1650	};
..	..	@@ -1445,7 +1658,9 @@
1445	1658	.hw.init = &(struct clk_init_data){
1446	1659	.name = "vapb_0_div",
1447	1660	.ops = &clk_regmap_divider_ops,
1448		- .parent_names = (const char *[]){ "vapb_0_sel" },
	1661	+ .parent_hws = (const struct clk_hw *[]) {
	1662	+ &gxbb_vapb_0_sel.hw
	1663	+ },
1449	1664	.num_parents = 1,
1450	1665	.flags = CLK_SET_RATE_PARENT,
1451	1666	},
..	..	@@ -1459,7 +1674,9 @@
1459	1674	.hw.init = &(struct clk_init_data) {
1460	1675	.name = "vapb_0",
1461	1676	.ops = &clk_regmap_gate_ops,
1462		- .parent_names = (const char *[]){ "vapb_0_div" },
	1677	+ .parent_hws = (const struct clk_hw *[]) {
	1678	+ &gxbb_vapb_0_div.hw
	1679	+ },
1463	1680	.num_parents = 1,
1464	1681	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1465	1682	},
..	..	@@ -1478,8 +1695,8 @@
1478	1695	* bits 25:26 selects from 4 possible parents:
1479	1696	* fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1480	1697	*/
1481		- .parent_names = gxbb_vapb_parent_names,
1482		- .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
	1698	+ .parent_hws = gxbb_vapb_parent_hws,
	1699	+ .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1483	1700	.flags = CLK_SET_RATE_NO_REPARENT,
1484	1701	},
1485	1702	};
..	..	@@ -1493,7 +1710,9 @@
1493	1710	.hw.init = &(struct clk_init_data){
1494	1711	.name = "vapb_1_div",
1495	1712	.ops = &clk_regmap_divider_ops,
1496		- .parent_names = (const char *[]){ "vapb_1_sel" },
	1713	+ .parent_hws = (const struct clk_hw *[]) {
	1714	+ &gxbb_vapb_1_sel.hw
	1715	+ },
1497	1716	.num_parents = 1,
1498	1717	.flags = CLK_SET_RATE_PARENT,
1499	1718	},
..	..	@@ -1507,7 +1726,9 @@
1507	1726	.hw.init = &(struct clk_init_data) {
1508	1727	.name = "vapb_1",
1509	1728	.ops = &clk_regmap_gate_ops,
1510		- .parent_names = (const char *[]){ "vapb_1_div" },
	1729	+ .parent_hws = (const struct clk_hw *[]) {
	1730	+ &gxbb_vapb_1_div.hw
	1731	+ },
1511	1732	.num_parents = 1,
1512	1733	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1513	1734	},
..	..	@@ -1526,7 +1747,10 @@
1526	1747	* bit 31 selects from 2 possible parents:
1527	1748	* vapb_0 or vapb_1
1528	1749	*/
1529		- .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
	1750	+ .parent_hws = (const struct clk_hw *[]) {
	1751	+ &gxbb_vapb_0.hw,
	1752	+ &gxbb_vapb_1.hw
	1753	+ },
1530	1754	.num_parents = 2,
1531	1755	.flags = CLK_SET_RATE_NO_REPARENT,
1532	1756	},
..	..	@@ -1540,7 +1764,689 @@
1540	1764	.hw.init = &(struct clk_init_data) {
1541	1765	.name = "vapb",
1542	1766	.ops = &clk_regmap_gate_ops,
1543		- .parent_names = (const char *[]){ "vapb_sel" },
	1767	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
	1768	+ .num_parents = 1,
	1769	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1770	+ },
	1771	+};
	1772	+
	1773	+/* Video Clocks */
	1774	+
	1775	+static struct clk_regmap gxbb_vid_pll_div = {
	1776	+ .data = &(struct meson_vid_pll_div_data){
	1777	+ .val = {
	1778	+ .reg_off = HHI_VID_PLL_CLK_DIV,
	1779	+ .shift = 0,
	1780	+ .width = 15,
	1781	+ },
	1782	+ .sel = {
	1783	+ .reg_off = HHI_VID_PLL_CLK_DIV,
	1784	+ .shift = 16,
	1785	+ .width = 2,
	1786	+ },
	1787	+ },
	1788	+ .hw.init = &(struct clk_init_data) {
	1789	+ .name = "vid_pll_div",
	1790	+ .ops = &meson_vid_pll_div_ro_ops,
	1791	+ .parent_data = &(const struct clk_parent_data) {
	1792	+ /*
	1793	+ * Note:
	1794	+ * GXL and GXBB have different hdmi_plls (with
	1795	+ * different struct clk_hw). We fallback to the global
	1796	+ * naming string mechanism so vid_pll_div picks up the
	1797	+ * appropriate one.
	1798	+ */
	1799	+ .name = "hdmi_pll",
	1800	+ .index = -1,
	1801	+ },
	1802	+ .num_parents = 1,
	1803	+ .flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
	1804	+ },
	1805	+};
	1806	+
	1807	+static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
	1808	+ { .hw = &gxbb_vid_pll_div.hw },
	1809	+ /*
	1810	+ * Note:
	1811	+ * GXL and GXBB have different hdmi_plls (with
	1812	+ * different struct clk_hw). We fallback to the global
	1813	+ * naming string mechanism so vid_pll_div picks up the
	1814	+ * appropriate one.
	1815	+ */
	1816	+ { .name = "hdmi_pll", .index = -1 },
	1817	+};
	1818	+
	1819	+static struct clk_regmap gxbb_vid_pll_sel = {
	1820	+ .data = &(struct clk_regmap_mux_data){
	1821	+ .offset = HHI_VID_PLL_CLK_DIV,
	1822	+ .mask = 0x1,
	1823	+ .shift = 18,
	1824	+ },
	1825	+ .hw.init = &(struct clk_init_data){
	1826	+ .name = "vid_pll_sel",
	1827	+ .ops = &clk_regmap_mux_ops,
	1828	+ /*
	1829	+ * bit 18 selects from 2 possible parents:
	1830	+ * vid_pll_div or hdmi_pll
	1831	+ */
	1832	+ .parent_data = gxbb_vid_pll_parent_data,
	1833	+ .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
	1834	+ .flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
	1835	+ },
	1836	+};
	1837	+
	1838	+static struct clk_regmap gxbb_vid_pll = {
	1839	+ .data = &(struct clk_regmap_gate_data){
	1840	+ .offset = HHI_VID_PLL_CLK_DIV,
	1841	+ .bit_idx = 19,
	1842	+ },
	1843	+ .hw.init = &(struct clk_init_data) {
	1844	+ .name = "vid_pll",
	1845	+ .ops = &clk_regmap_gate_ops,
	1846	+ .parent_hws = (const struct clk_hw *[]) {
	1847	+ &gxbb_vid_pll_sel.hw
	1848	+ },
	1849	+ .num_parents = 1,
	1850	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1851	+ },
	1852	+};
	1853	+
	1854	+static const struct clk_hw *gxbb_vclk_parent_hws[] = {
	1855	+ &gxbb_vid_pll.hw,
	1856	+ &gxbb_fclk_div4.hw,
	1857	+ &gxbb_fclk_div3.hw,
	1858	+ &gxbb_fclk_div5.hw,
	1859	+ &gxbb_vid_pll.hw,
	1860	+ &gxbb_fclk_div7.hw,
	1861	+ &gxbb_mpll1.hw,
	1862	+};
	1863	+
	1864	+static struct clk_regmap gxbb_vclk_sel = {
	1865	+ .data = &(struct clk_regmap_mux_data){
	1866	+ .offset = HHI_VID_CLK_CNTL,
	1867	+ .mask = 0x7,
	1868	+ .shift = 16,
	1869	+ },
	1870	+ .hw.init = &(struct clk_init_data){
	1871	+ .name = "vclk_sel",
	1872	+ .ops = &clk_regmap_mux_ops,
	1873	+ /*
	1874	+ * bits 16:18 selects from 8 possible parents:
	1875	+ * vid_pll, fclk_div4, fclk_div3, fclk_div5,
	1876	+ * vid_pll, fclk_div7, mp1
	1877	+ */
	1878	+ .parent_hws = gxbb_vclk_parent_hws,
	1879	+ .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
	1880	+ .flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
	1881	+ },
	1882	+};
	1883	+
	1884	+static struct clk_regmap gxbb_vclk2_sel = {
	1885	+ .data = &(struct clk_regmap_mux_data){
	1886	+ .offset = HHI_VIID_CLK_CNTL,
	1887	+ .mask = 0x7,
	1888	+ .shift = 16,
	1889	+ },
	1890	+ .hw.init = &(struct clk_init_data){
	1891	+ .name = "vclk2_sel",
	1892	+ .ops = &clk_regmap_mux_ops,
	1893	+ /*
	1894	+ * bits 16:18 selects from 8 possible parents:
	1895	+ * vid_pll, fclk_div4, fclk_div3, fclk_div5,
	1896	+ * vid_pll, fclk_div7, mp1
	1897	+ */
	1898	+ .parent_hws = gxbb_vclk_parent_hws,
	1899	+ .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
	1900	+ .flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
	1901	+ },
	1902	+};
	1903	+
	1904	+static struct clk_regmap gxbb_vclk_input = {
	1905	+ .data = &(struct clk_regmap_gate_data){
	1906	+ .offset = HHI_VID_CLK_DIV,
	1907	+ .bit_idx = 16,
	1908	+ },
	1909	+ .hw.init = &(struct clk_init_data) {
	1910	+ .name = "vclk_input",
	1911	+ .ops = &clk_regmap_gate_ops,
	1912	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
	1913	+ .num_parents = 1,
	1914	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1915	+ },
	1916	+};
	1917	+
	1918	+static struct clk_regmap gxbb_vclk2_input = {
	1919	+ .data = &(struct clk_regmap_gate_data){
	1920	+ .offset = HHI_VIID_CLK_DIV,
	1921	+ .bit_idx = 16,
	1922	+ },
	1923	+ .hw.init = &(struct clk_init_data) {
	1924	+ .name = "vclk2_input",
	1925	+ .ops = &clk_regmap_gate_ops,
	1926	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
	1927	+ .num_parents = 1,
	1928	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1929	+ },
	1930	+};
	1931	+
	1932	+static struct clk_regmap gxbb_vclk_div = {
	1933	+ .data = &(struct clk_regmap_div_data){
	1934	+ .offset = HHI_VID_CLK_DIV,
	1935	+ .shift = 0,
	1936	+ .width = 8,
	1937	+ },
	1938	+ .hw.init = &(struct clk_init_data){
	1939	+ .name = "vclk_div",
	1940	+ .ops = &clk_regmap_divider_ops,
	1941	+ .parent_hws = (const struct clk_hw *[]) {
	1942	+ &gxbb_vclk_input.hw
	1943	+ },
	1944	+ .num_parents = 1,
	1945	+ .flags = CLK_GET_RATE_NOCACHE,
	1946	+ },
	1947	+};
	1948	+
	1949	+static struct clk_regmap gxbb_vclk2_div = {
	1950	+ .data = &(struct clk_regmap_div_data){
	1951	+ .offset = HHI_VIID_CLK_DIV,
	1952	+ .shift = 0,
	1953	+ .width = 8,
	1954	+ },
	1955	+ .hw.init = &(struct clk_init_data){
	1956	+ .name = "vclk2_div",
	1957	+ .ops = &clk_regmap_divider_ops,
	1958	+ .parent_hws = (const struct clk_hw *[]) {
	1959	+ &gxbb_vclk2_input.hw
	1960	+ },
	1961	+ .num_parents = 1,
	1962	+ .flags = CLK_GET_RATE_NOCACHE,
	1963	+ },
	1964	+};
	1965	+
	1966	+static struct clk_regmap gxbb_vclk = {
	1967	+ .data = &(struct clk_regmap_gate_data){
	1968	+ .offset = HHI_VID_CLK_CNTL,
	1969	+ .bit_idx = 19,
	1970	+ },
	1971	+ .hw.init = &(struct clk_init_data) {
	1972	+ .name = "vclk",
	1973	+ .ops = &clk_regmap_gate_ops,
	1974	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
	1975	+ .num_parents = 1,
	1976	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1977	+ },
	1978	+};
	1979	+
	1980	+static struct clk_regmap gxbb_vclk2 = {
	1981	+ .data = &(struct clk_regmap_gate_data){
	1982	+ .offset = HHI_VIID_CLK_CNTL,
	1983	+ .bit_idx = 19,
	1984	+ },
	1985	+ .hw.init = &(struct clk_init_data) {
	1986	+ .name = "vclk2",
	1987	+ .ops = &clk_regmap_gate_ops,
	1988	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
	1989	+ .num_parents = 1,
	1990	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	1991	+ },
	1992	+};
	1993	+
	1994	+static struct clk_regmap gxbb_vclk_div1 = {
	1995	+ .data = &(struct clk_regmap_gate_data){
	1996	+ .offset = HHI_VID_CLK_CNTL,
	1997	+ .bit_idx = 0,
	1998	+ },
	1999	+ .hw.init = &(struct clk_init_data) {
	2000	+ .name = "vclk_div1",
	2001	+ .ops = &clk_regmap_gate_ops,
	2002	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
	2003	+ .num_parents = 1,
	2004	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2005	+ },
	2006	+};
	2007	+
	2008	+static struct clk_regmap gxbb_vclk_div2_en = {
	2009	+ .data = &(struct clk_regmap_gate_data){
	2010	+ .offset = HHI_VID_CLK_CNTL,
	2011	+ .bit_idx = 1,
	2012	+ },
	2013	+ .hw.init = &(struct clk_init_data) {
	2014	+ .name = "vclk_div2_en",
	2015	+ .ops = &clk_regmap_gate_ops,
	2016	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
	2017	+ .num_parents = 1,
	2018	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2019	+ },
	2020	+};
	2021	+
	2022	+static struct clk_regmap gxbb_vclk_div4_en = {
	2023	+ .data = &(struct clk_regmap_gate_data){
	2024	+ .offset = HHI_VID_CLK_CNTL,
	2025	+ .bit_idx = 2,
	2026	+ },
	2027	+ .hw.init = &(struct clk_init_data) {
	2028	+ .name = "vclk_div4_en",
	2029	+ .ops = &clk_regmap_gate_ops,
	2030	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
	2031	+ .num_parents = 1,
	2032	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2033	+ },
	2034	+};
	2035	+
	2036	+static struct clk_regmap gxbb_vclk_div6_en = {
	2037	+ .data = &(struct clk_regmap_gate_data){
	2038	+ .offset = HHI_VID_CLK_CNTL,
	2039	+ .bit_idx = 3,
	2040	+ },
	2041	+ .hw.init = &(struct clk_init_data) {
	2042	+ .name = "vclk_div6_en",
	2043	+ .ops = &clk_regmap_gate_ops,
	2044	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
	2045	+ .num_parents = 1,
	2046	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2047	+ },
	2048	+};
	2049	+
	2050	+static struct clk_regmap gxbb_vclk_div12_en = {
	2051	+ .data = &(struct clk_regmap_gate_data){
	2052	+ .offset = HHI_VID_CLK_CNTL,
	2053	+ .bit_idx = 4,
	2054	+ },
	2055	+ .hw.init = &(struct clk_init_data) {
	2056	+ .name = "vclk_div12_en",
	2057	+ .ops = &clk_regmap_gate_ops,
	2058	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
	2059	+ .num_parents = 1,
	2060	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2061	+ },
	2062	+};
	2063	+
	2064	+static struct clk_regmap gxbb_vclk2_div1 = {
	2065	+ .data = &(struct clk_regmap_gate_data){
	2066	+ .offset = HHI_VIID_CLK_CNTL,
	2067	+ .bit_idx = 0,
	2068	+ },
	2069	+ .hw.init = &(struct clk_init_data) {
	2070	+ .name = "vclk2_div1",
	2071	+ .ops = &clk_regmap_gate_ops,
	2072	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
	2073	+ .num_parents = 1,
	2074	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2075	+ },
	2076	+};
	2077	+
	2078	+static struct clk_regmap gxbb_vclk2_div2_en = {
	2079	+ .data = &(struct clk_regmap_gate_data){
	2080	+ .offset = HHI_VIID_CLK_CNTL,
	2081	+ .bit_idx = 1,
	2082	+ },
	2083	+ .hw.init = &(struct clk_init_data) {
	2084	+ .name = "vclk2_div2_en",
	2085	+ .ops = &clk_regmap_gate_ops,
	2086	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
	2087	+ .num_parents = 1,
	2088	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2089	+ },
	2090	+};
	2091	+
	2092	+static struct clk_regmap gxbb_vclk2_div4_en = {
	2093	+ .data = &(struct clk_regmap_gate_data){
	2094	+ .offset = HHI_VIID_CLK_CNTL,
	2095	+ .bit_idx = 2,
	2096	+ },
	2097	+ .hw.init = &(struct clk_init_data) {
	2098	+ .name = "vclk2_div4_en",
	2099	+ .ops = &clk_regmap_gate_ops,
	2100	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
	2101	+ .num_parents = 1,
	2102	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2103	+ },
	2104	+};
	2105	+
	2106	+static struct clk_regmap gxbb_vclk2_div6_en = {
	2107	+ .data = &(struct clk_regmap_gate_data){
	2108	+ .offset = HHI_VIID_CLK_CNTL,
	2109	+ .bit_idx = 3,
	2110	+ },
	2111	+ .hw.init = &(struct clk_init_data) {
	2112	+ .name = "vclk2_div6_en",
	2113	+ .ops = &clk_regmap_gate_ops,
	2114	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
	2115	+ .num_parents = 1,
	2116	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2117	+ },
	2118	+};
	2119	+
	2120	+static struct clk_regmap gxbb_vclk2_div12_en = {
	2121	+ .data = &(struct clk_regmap_gate_data){
	2122	+ .offset = HHI_VIID_CLK_CNTL,
	2123	+ .bit_idx = 4,
	2124	+ },
	2125	+ .hw.init = &(struct clk_init_data) {
	2126	+ .name = "vclk2_div12_en",
	2127	+ .ops = &clk_regmap_gate_ops,
	2128	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
	2129	+ .num_parents = 1,
	2130	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2131	+ },
	2132	+};
	2133	+
	2134	+static struct clk_fixed_factor gxbb_vclk_div2 = {
	2135	+ .mult = 1,
	2136	+ .div = 2,
	2137	+ .hw.init = &(struct clk_init_data){
	2138	+ .name = "vclk_div2",
	2139	+ .ops = &clk_fixed_factor_ops,
	2140	+ .parent_hws = (const struct clk_hw *[]) {
	2141	+ &gxbb_vclk_div2_en.hw
	2142	+ },
	2143	+ .num_parents = 1,
	2144	+ },
	2145	+};
	2146	+
	2147	+static struct clk_fixed_factor gxbb_vclk_div4 = {
	2148	+ .mult = 1,
	2149	+ .div = 4,
	2150	+ .hw.init = &(struct clk_init_data){
	2151	+ .name = "vclk_div4",
	2152	+ .ops = &clk_fixed_factor_ops,
	2153	+ .parent_hws = (const struct clk_hw *[]) {
	2154	+ &gxbb_vclk_div4_en.hw
	2155	+ },
	2156	+ .num_parents = 1,
	2157	+ },
	2158	+};
	2159	+
	2160	+static struct clk_fixed_factor gxbb_vclk_div6 = {
	2161	+ .mult = 1,
	2162	+ .div = 6,
	2163	+ .hw.init = &(struct clk_init_data){
	2164	+ .name = "vclk_div6",
	2165	+ .ops = &clk_fixed_factor_ops,
	2166	+ .parent_hws = (const struct clk_hw *[]) {
	2167	+ &gxbb_vclk_div6_en.hw
	2168	+ },
	2169	+ .num_parents = 1,
	2170	+ },
	2171	+};
	2172	+
	2173	+static struct clk_fixed_factor gxbb_vclk_div12 = {
	2174	+ .mult = 1,
	2175	+ .div = 12,
	2176	+ .hw.init = &(struct clk_init_data){
	2177	+ .name = "vclk_div12",
	2178	+ .ops = &clk_fixed_factor_ops,
	2179	+ .parent_hws = (const struct clk_hw *[]) {
	2180	+ &gxbb_vclk_div12_en.hw
	2181	+ },
	2182	+ .num_parents = 1,
	2183	+ },
	2184	+};
	2185	+
	2186	+static struct clk_fixed_factor gxbb_vclk2_div2 = {
	2187	+ .mult = 1,
	2188	+ .div = 2,
	2189	+ .hw.init = &(struct clk_init_data){
	2190	+ .name = "vclk2_div2",
	2191	+ .ops = &clk_fixed_factor_ops,
	2192	+ .parent_hws = (const struct clk_hw *[]) {
	2193	+ &gxbb_vclk2_div2_en.hw
	2194	+ },
	2195	+ .num_parents = 1,
	2196	+ },
	2197	+};
	2198	+
	2199	+static struct clk_fixed_factor gxbb_vclk2_div4 = {
	2200	+ .mult = 1,
	2201	+ .div = 4,
	2202	+ .hw.init = &(struct clk_init_data){
	2203	+ .name = "vclk2_div4",
	2204	+ .ops = &clk_fixed_factor_ops,
	2205	+ .parent_hws = (const struct clk_hw *[]) {
	2206	+ &gxbb_vclk2_div4_en.hw
	2207	+ },
	2208	+ .num_parents = 1,
	2209	+ },
	2210	+};
	2211	+
	2212	+static struct clk_fixed_factor gxbb_vclk2_div6 = {
	2213	+ .mult = 1,
	2214	+ .div = 6,
	2215	+ .hw.init = &(struct clk_init_data){
	2216	+ .name = "vclk2_div6",
	2217	+ .ops = &clk_fixed_factor_ops,
	2218	+ .parent_hws = (const struct clk_hw *[]) {
	2219	+ &gxbb_vclk2_div6_en.hw
	2220	+ },
	2221	+ .num_parents = 1,
	2222	+ },
	2223	+};
	2224	+
	2225	+static struct clk_fixed_factor gxbb_vclk2_div12 = {
	2226	+ .mult = 1,
	2227	+ .div = 12,
	2228	+ .hw.init = &(struct clk_init_data){
	2229	+ .name = "vclk2_div12",
	2230	+ .ops = &clk_fixed_factor_ops,
	2231	+ .parent_hws = (const struct clk_hw *[]) {
	2232	+ &gxbb_vclk2_div12_en.hw
	2233	+ },
	2234	+ .num_parents = 1,
	2235	+ },
	2236	+};
	2237	+
	2238	+static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
	2239	+static const struct clk_hw *gxbb_cts_parent_hws[] = {
	2240	+ &gxbb_vclk_div1.hw,
	2241	+ &gxbb_vclk_div2.hw,
	2242	+ &gxbb_vclk_div4.hw,
	2243	+ &gxbb_vclk_div6.hw,
	2244	+ &gxbb_vclk_div12.hw,
	2245	+ &gxbb_vclk2_div1.hw,
	2246	+ &gxbb_vclk2_div2.hw,
	2247	+ &gxbb_vclk2_div4.hw,
	2248	+ &gxbb_vclk2_div6.hw,
	2249	+ &gxbb_vclk2_div12.hw,
	2250	+};
	2251	+
	2252	+static struct clk_regmap gxbb_cts_enci_sel = {
	2253	+ .data = &(struct clk_regmap_mux_data){
	2254	+ .offset = HHI_VID_CLK_DIV,
	2255	+ .mask = 0xf,
	2256	+ .shift = 28,
	2257	+ .table = mux_table_cts_sel,
	2258	+ },
	2259	+ .hw.init = &(struct clk_init_data){
	2260	+ .name = "cts_enci_sel",
	2261	+ .ops = &clk_regmap_mux_ops,
	2262	+ .parent_hws = gxbb_cts_parent_hws,
	2263	+ .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
	2264	+ .flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
	2265	+ },
	2266	+};
	2267	+
	2268	+static struct clk_regmap gxbb_cts_encp_sel = {
	2269	+ .data = &(struct clk_regmap_mux_data){
	2270	+ .offset = HHI_VID_CLK_DIV,
	2271	+ .mask = 0xf,
	2272	+ .shift = 20,
	2273	+ .table = mux_table_cts_sel,
	2274	+ },
	2275	+ .hw.init = &(struct clk_init_data){
	2276	+ .name = "cts_encp_sel",
	2277	+ .ops = &clk_regmap_mux_ops,
	2278	+ .parent_hws = gxbb_cts_parent_hws,
	2279	+ .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
	2280	+ .flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
	2281	+ },
	2282	+};
	2283	+
	2284	+static struct clk_regmap gxbb_cts_vdac_sel = {
	2285	+ .data = &(struct clk_regmap_mux_data){
	2286	+ .offset = HHI_VIID_CLK_DIV,
	2287	+ .mask = 0xf,
	2288	+ .shift = 28,
	2289	+ .table = mux_table_cts_sel,
	2290	+ },
	2291	+ .hw.init = &(struct clk_init_data){
	2292	+ .name = "cts_vdac_sel",
	2293	+ .ops = &clk_regmap_mux_ops,
	2294	+ .parent_hws = gxbb_cts_parent_hws,
	2295	+ .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
	2296	+ .flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
	2297	+ },
	2298	+};
	2299	+
	2300	+/* TOFIX: add support for cts_tcon */
	2301	+static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
	2302	+static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
	2303	+ &gxbb_vclk_div1.hw,
	2304	+ &gxbb_vclk_div2.hw,
	2305	+ &gxbb_vclk_div4.hw,
	2306	+ &gxbb_vclk_div6.hw,
	2307	+ &gxbb_vclk_div12.hw,
	2308	+ &gxbb_vclk2_div1.hw,
	2309	+ &gxbb_vclk2_div2.hw,
	2310	+ &gxbb_vclk2_div4.hw,
	2311	+ &gxbb_vclk2_div6.hw,
	2312	+ &gxbb_vclk2_div12.hw,
	2313	+};
	2314	+
	2315	+static struct clk_regmap gxbb_hdmi_tx_sel = {
	2316	+ .data = &(struct clk_regmap_mux_data){
	2317	+ .offset = HHI_HDMI_CLK_CNTL,
	2318	+ .mask = 0xf,
	2319	+ .shift = 16,
	2320	+ .table = mux_table_hdmi_tx_sel,
	2321	+ },
	2322	+ .hw.init = &(struct clk_init_data){
	2323	+ .name = "hdmi_tx_sel",
	2324	+ .ops = &clk_regmap_mux_ops,
	2325	+ /*
	2326	+ * bits 31:28 selects from 12 possible parents:
	2327	+ * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
	2328	+ * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
	2329	+ * cts_tcon
	2330	+ */
	2331	+ .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
	2332	+ .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
	2333	+ .flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
	2334	+ },
	2335	+};
	2336	+
	2337	+static struct clk_regmap gxbb_cts_enci = {
	2338	+ .data = &(struct clk_regmap_gate_data){
	2339	+ .offset = HHI_VID_CLK_CNTL2,
	2340	+ .bit_idx = 0,
	2341	+ },
	2342	+ .hw.init = &(struct clk_init_data) {
	2343	+ .name = "cts_enci",
	2344	+ .ops = &clk_regmap_gate_ops,
	2345	+ .parent_hws = (const struct clk_hw *[]) {
	2346	+ &gxbb_cts_enci_sel.hw
	2347	+ },
	2348	+ .num_parents = 1,
	2349	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2350	+ },
	2351	+};
	2352	+
	2353	+static struct clk_regmap gxbb_cts_encp = {
	2354	+ .data = &(struct clk_regmap_gate_data){
	2355	+ .offset = HHI_VID_CLK_CNTL2,
	2356	+ .bit_idx = 2,
	2357	+ },
	2358	+ .hw.init = &(struct clk_init_data) {
	2359	+ .name = "cts_encp",
	2360	+ .ops = &clk_regmap_gate_ops,
	2361	+ .parent_hws = (const struct clk_hw *[]) {
	2362	+ &gxbb_cts_encp_sel.hw
	2363	+ },
	2364	+ .num_parents = 1,
	2365	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2366	+ },
	2367	+};
	2368	+
	2369	+static struct clk_regmap gxbb_cts_vdac = {
	2370	+ .data = &(struct clk_regmap_gate_data){
	2371	+ .offset = HHI_VID_CLK_CNTL2,
	2372	+ .bit_idx = 4,
	2373	+ },
	2374	+ .hw.init = &(struct clk_init_data) {
	2375	+ .name = "cts_vdac",
	2376	+ .ops = &clk_regmap_gate_ops,
	2377	+ .parent_hws = (const struct clk_hw *[]) {
	2378	+ &gxbb_cts_vdac_sel.hw
	2379	+ },
	2380	+ .num_parents = 1,
	2381	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2382	+ },
	2383	+};
	2384	+
	2385	+static struct clk_regmap gxbb_hdmi_tx = {
	2386	+ .data = &(struct clk_regmap_gate_data){
	2387	+ .offset = HHI_VID_CLK_CNTL2,
	2388	+ .bit_idx = 5,
	2389	+ },
	2390	+ .hw.init = &(struct clk_init_data) {
	2391	+ .name = "hdmi_tx",
	2392	+ .ops = &clk_regmap_gate_ops,
	2393	+ .parent_hws = (const struct clk_hw *[]) {
	2394	+ &gxbb_hdmi_tx_sel.hw
	2395	+ },
	2396	+ .num_parents = 1,
	2397	+ .flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
	2398	+ },
	2399	+};
	2400	+
	2401	+/* HDMI Clocks */
	2402	+
	2403	+static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
	2404	+ { .fw_name = "xtal", },
	2405	+ { .hw = &gxbb_fclk_div4.hw },
	2406	+ { .hw = &gxbb_fclk_div3.hw },
	2407	+ { .hw = &gxbb_fclk_div5.hw },
	2408	+};
	2409	+
	2410	+static struct clk_regmap gxbb_hdmi_sel = {
	2411	+ .data = &(struct clk_regmap_mux_data){
	2412	+ .offset = HHI_HDMI_CLK_CNTL,
	2413	+ .mask = 0x3,
	2414	+ .shift = 9,
	2415	+ .flags = CLK_MUX_ROUND_CLOSEST,
	2416	+ },
	2417	+ .hw.init = &(struct clk_init_data){
	2418	+ .name = "hdmi_sel",
	2419	+ .ops = &clk_regmap_mux_ops,
	2420	+ .parent_data = gxbb_hdmi_parent_data,
	2421	+ .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
	2422	+ .flags = CLK_SET_RATE_NO_REPARENT \| CLK_GET_RATE_NOCACHE,
	2423	+ },
	2424	+};
	2425	+
	2426	+static struct clk_regmap gxbb_hdmi_div = {
	2427	+ .data = &(struct clk_regmap_div_data){
	2428	+ .offset = HHI_HDMI_CLK_CNTL,
	2429	+ .shift = 0,
	2430	+ .width = 7,
	2431	+ },
	2432	+ .hw.init = &(struct clk_init_data){
	2433	+ .name = "hdmi_div",
	2434	+ .ops = &clk_regmap_divider_ops,
	2435	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
	2436	+ .num_parents = 1,
	2437	+ .flags = CLK_GET_RATE_NOCACHE,
	2438	+ },
	2439	+};
	2440	+
	2441	+static struct clk_regmap gxbb_hdmi = {
	2442	+ .data = &(struct clk_regmap_gate_data){
	2443	+ .offset = HHI_HDMI_CLK_CNTL,
	2444	+ .bit_idx = 8,
	2445	+ },
	2446	+ .hw.init = &(struct clk_init_data) {
	2447	+ .name = "hdmi",
	2448	+ .ops = &clk_regmap_gate_ops,
	2449	+ .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
1544	2450	.num_parents = 1,
1545	2451	.flags = CLK_SET_RATE_PARENT \| CLK_IGNORE_UNUSED,
1546	2452	},
..	..	@@ -1548,8 +2454,11 @@
1548	2454
1549	2455	/* VDEC clocks */
1550	2456
1551		-static const char * const gxbb_vdec_parent_names[] = {
1552		- "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
	2457	+static const struct clk_hw *gxbb_vdec_parent_hws[] = {
	2458	+ &gxbb_fclk_div4.hw,
	2459	+ &gxbb_fclk_div3.hw,
	2460	+ &gxbb_fclk_div5.hw,
	2461	+ &gxbb_fclk_div7.hw,
1553	2462	};
1554	2463
1555	2464	static struct clk_regmap gxbb_vdec_1_sel = {
..	..	@@ -1562,8 +2471,8 @@
1562	2471	.hw.init = &(struct clk_init_data){
1563	2472	.name = "vdec_1_sel",
1564	2473	.ops = &clk_regmap_mux_ops,
1565		- .parent_names = gxbb_vdec_parent_names,
1566		- .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
	2474	+ .parent_hws = gxbb_vdec_parent_hws,
	2475	+ .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
1567	2476	.flags = CLK_SET_RATE_PARENT,
1568	2477	},
1569	2478	};
..	..	@@ -1578,7 +2487,9 @@
1578	2487	.hw.init = &(struct clk_init_data){
1579	2488	.name = "vdec_1_div",
1580	2489	.ops = &clk_regmap_divider_ops,
1581		- .parent_names = (const char *[]){ "vdec_1_sel" },
	2490	+ .parent_hws = (const struct clk_hw *[]) {
	2491	+ &gxbb_vdec_1_sel.hw
	2492	+ },
1582	2493	.num_parents = 1,
1583	2494	.flags = CLK_SET_RATE_PARENT,
1584	2495	},
..	..	@@ -1592,7 +2503,9 @@
1592	2503	.hw.init = &(struct clk_init_data) {
1593	2504	.name = "vdec_1",
1594	2505	.ops = &clk_regmap_gate_ops,
1595		- .parent_names = (const char *[]){ "vdec_1_div" },
	2506	+ .parent_hws = (const struct clk_hw *[]) {
	2507	+ &gxbb_vdec_1_div.hw
	2508	+ },
1596	2509	.num_parents = 1,
1597	2510	.flags = CLK_SET_RATE_PARENT,
1598	2511	},
..	..	@@ -1608,8 +2521,8 @@
1608	2521	.hw.init = &(struct clk_init_data){
1609	2522	.name = "vdec_hevc_sel",
1610	2523	.ops = &clk_regmap_mux_ops,
1611		- .parent_names = gxbb_vdec_parent_names,
1612		- .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
	2524	+ .parent_hws = gxbb_vdec_parent_hws,
	2525	+ .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
1613	2526	.flags = CLK_SET_RATE_PARENT,
1614	2527	},
1615	2528	};
..	..	@@ -1624,7 +2537,9 @@
1624	2537	.hw.init = &(struct clk_init_data){
1625	2538	.name = "vdec_hevc_div",
1626	2539	.ops = &clk_regmap_divider_ops,
1627		- .parent_names = (const char *[]){ "vdec_hevc_sel" },
	2540	+ .parent_hws = (const struct clk_hw *[]) {
	2541	+ &gxbb_vdec_hevc_sel.hw
	2542	+ },
1628	2543	.num_parents = 1,
1629	2544	.flags = CLK_SET_RATE_PARENT,
1630	2545	},
..	..	@@ -1638,7 +2553,9 @@
1638	2553	.hw.init = &(struct clk_init_data) {
1639	2554	.name = "vdec_hevc",
1640	2555	.ops = &clk_regmap_gate_ops,
1641		- .parent_names = (const char *[]){ "vdec_hevc_div" },
	2556	+ .parent_hws = (const struct clk_hw *[]) {
	2557	+ &gxbb_vdec_hevc_div.hw
	2558	+ },
1642	2559	.num_parents = 1,
1643	2560	.flags = CLK_SET_RATE_PARENT,
1644	2561	},
..	..	@@ -1646,9 +2563,18 @@
1646	2563
1647	2564	static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
1648	2565	9, 10, 11, 13, 14, };
1649		-static const char * const gen_clk_parent_names[] = {
1650		- "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
1651		- "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
	2566	+static const struct clk_parent_data gen_clk_parent_data[] = {
	2567	+ { .fw_name = "xtal", },
	2568	+ { .hw = &gxbb_vdec_1.hw },
	2569	+ { .hw = &gxbb_vdec_hevc.hw },
	2570	+ { .hw = &gxbb_mpll0.hw },
	2571	+ { .hw = &gxbb_mpll1.hw },
	2572	+ { .hw = &gxbb_mpll2.hw },
	2573	+ { .hw = &gxbb_fclk_div4.hw },
	2574	+ { .hw = &gxbb_fclk_div3.hw },
	2575	+ { .hw = &gxbb_fclk_div5.hw },
	2576	+ { .hw = &gxbb_fclk_div7.hw },
	2577	+ { .hw = &gxbb_gp0_pll.hw },
1652	2578	};
1653	2579
1654	2580	static struct clk_regmap gxbb_gen_clk_sel = {
..	..	@@ -1667,8 +2593,8 @@
1667	2593	* vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
1668	2594	* fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1669	2595	*/
1670		- .parent_names = gen_clk_parent_names,
1671		- .num_parents = ARRAY_SIZE(gen_clk_parent_names),
	2596	+ .parent_data = gen_clk_parent_data,
	2597	+ .num_parents = ARRAY_SIZE(gen_clk_parent_data),
1672	2598	},
1673	2599	};
1674	2600
..	..	@@ -1681,7 +2607,9 @@
1681	2607	.hw.init = &(struct clk_init_data){
1682	2608	.name = "gen_clk_div",
1683	2609	.ops = &clk_regmap_divider_ops,
1684		- .parent_names = (const char *[]){ "gen_clk_sel" },
	2610	+ .parent_hws = (const struct clk_hw *[]) {
	2611	+ &gxbb_gen_clk_sel.hw
	2612	+ },
1685	2613	.num_parents = 1,
1686	2614	.flags = CLK_SET_RATE_PARENT,
1687	2615	},
..	..	@@ -1695,11 +2623,16 @@
1695	2623	.hw.init = &(struct clk_init_data){
1696	2624	.name = "gen_clk",
1697	2625	.ops = &clk_regmap_gate_ops,
1698		- .parent_names = (const char *[]){ "gen_clk_div" },
	2626	+ .parent_hws = (const struct clk_hw *[]) {
	2627	+ &gxbb_gen_clk_div.hw
	2628	+ },
1699	2629	.num_parents = 1,
1700	2630	.flags = CLK_SET_RATE_PARENT,
1701	2631	},
1702	2632	};
	2633	+
	2634	+#define MESON_GATE(_name, _reg, _bit) \
	2635	+ MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
1703	2636
1704	2637	/* Everything Else (EE) domain gates */
1705	2638	static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
..	..	@@ -1723,19 +2656,12 @@
1723	2656	static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1724	2657	static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1725	2658	static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
	2659	+static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
1726	2660	static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
1727	2661
1728	2662	static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1729	2663	static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1730	2664	static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1731		-static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1732		-static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1733		-static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1734		-static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1735		-static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1736		-static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1737		-static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1738		-static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1739	2665	static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1740	2666	static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1741	2667	static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
..	..	@@ -1789,6 +2715,16 @@
1789	2715	static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1790	2716	static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1791	2717	static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
	2718	+
	2719	+/* AIU gates */
	2720	+static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
	2721	+static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
	2722	+static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
	2723	+static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
	2724	+static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
	2725	+static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
	2726	+static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
	2727	+static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
1792	2728
1793	2729	/* Array of all clocks provided by this provider */
1794	2730
..	..	@@ -1953,6 +2889,52 @@
1953	2889	[CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
1954	2890	[CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
1955	2891	[CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
	2892	+ [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
	2893	+ [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
	2894	+ [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
	2895	+ [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
	2896	+ [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
	2897	+ [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
	2898	+ [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
	2899	+ [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
	2900	+ [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
	2901	+ [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
	2902	+ [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
	2903	+ [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
	2904	+ [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
	2905	+ [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
	2906	+ [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
	2907	+ [CLKID_VCLK] = &gxbb_vclk.hw,
	2908	+ [CLKID_VCLK2] = &gxbb_vclk2.hw,
	2909	+ [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
	2910	+ [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
	2911	+ [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
	2912	+ [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
	2913	+ [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
	2914	+ [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
	2915	+ [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
	2916	+ [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
	2917	+ [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
	2918	+ [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
	2919	+ [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
	2920	+ [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
	2921	+ [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
	2922	+ [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
	2923	+ [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
	2924	+ [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
	2925	+ [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
	2926	+ [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
	2927	+ [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
	2928	+ [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
	2929	+ [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
	2930	+ [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
	2931	+ [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
	2932	+ [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
	2933	+ [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
	2934	+ [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
	2935	+ [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
	2936	+ [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
	2937	+ [CLKID_HDMI] = &gxbb_hdmi.hw,
1956	2938	[NR_CLKS] = NULL,
1957	2939	},
1958	2940	.num = NR_CLKS,
..	..	@@ -1968,7 +2950,7 @@
1968	2950	[CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1969	2951	[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1970	2952	[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1971		- [CLKID_GP0_PLL] = &gxl_gp0_pll.hw,
	2953	+ [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
1972	2954	[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1973	2955	[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1974	2956	[CLKID_CLK81] = &gxbb_clk81.hw,
..	..	@@ -2100,7 +3082,7 @@
2100	3082	[CLKID_VAPB_1] = &gxbb_vapb_1.hw,
2101	3083	[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
2102	3084	[CLKID_VAPB] = &gxbb_vapb.hw,
2103		- [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
	3085	+ [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
2104	3086	[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
2105	3087	[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
2106	3088	[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
..	..	@@ -2118,22 +3100,59 @@
2118	3100	[CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
2119	3101	[CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
2120	3102	[CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
	3103	+ [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
	3104	+ [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
	3105	+ [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
	3106	+ [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
	3107	+ [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
	3108	+ [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
	3109	+ [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
	3110	+ [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
	3111	+ [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
	3112	+ [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
	3113	+ [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
	3114	+ [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
	3115	+ [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
	3116	+ [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
	3117	+ [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
	3118	+ [CLKID_VCLK] = &gxbb_vclk.hw,
	3119	+ [CLKID_VCLK2] = &gxbb_vclk2.hw,
	3120	+ [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
	3121	+ [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
	3122	+ [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
	3123	+ [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
	3124	+ [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
	3125	+ [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
	3126	+ [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
	3127	+ [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
	3128	+ [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
	3129	+ [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
	3130	+ [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
	3131	+ [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
	3132	+ [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
	3133	+ [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
	3134	+ [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
	3135	+ [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
	3136	+ [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
	3137	+ [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
	3138	+ [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
	3139	+ [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
	3140	+ [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
	3141	+ [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
	3142	+ [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
	3143	+ [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
	3144	+ [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
	3145	+ [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
	3146	+ [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
	3147	+ [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
	3148	+ [CLKID_HDMI] = &gxbb_hdmi.hw,
	3149	+ [CLKID_ACODEC] = &gxl_acodec.hw,
2121	3150	[NR_CLKS] = NULL,
2122	3151	},
2123	3152	.num = NR_CLKS,
2124	3153	};
2125	3154
2126	3155	static struct clk_regmap *const gxbb_clk_regmaps[] = {
2127		- &gxbb_gp0_pll,
2128		- &gxbb_hdmi_pll,
2129		-};
2130		-
2131		-static struct clk_regmap *const gxl_clk_regmaps[] = {
2132		- &gxl_gp0_pll,
2133		- &gxl_hdmi_pll,
2134		-};
2135		-
2136		-static struct clk_regmap *const gx_clk_regmaps[] = {
2137	3156	&gxbb_clk81,
2138	3157	&gxbb_ddr,
2139	3158	&gxbb_dos,
..	..	@@ -2285,23 +3304,252 @@
2285	3304	&gxbb_gen_clk_sel,
2286	3305	&gxbb_gen_clk_div,
2287	3306	&gxbb_gen_clk,
	3307	+ &gxbb_fixed_pll_dco,
	3308	+ &gxbb_sys_pll_dco,
	3309	+ &gxbb_gp0_pll,
	3310	+ &gxbb_vid_pll,
	3311	+ &gxbb_vid_pll_sel,
	3312	+ &gxbb_vid_pll_div,
	3313	+ &gxbb_vclk,
	3314	+ &gxbb_vclk_sel,
	3315	+ &gxbb_vclk_div,
	3316	+ &gxbb_vclk_input,
	3317	+ &gxbb_vclk_div1,
	3318	+ &gxbb_vclk_div2_en,
	3319	+ &gxbb_vclk_div4_en,
	3320	+ &gxbb_vclk_div6_en,
	3321	+ &gxbb_vclk_div12_en,
	3322	+ &gxbb_vclk2,
	3323	+ &gxbb_vclk2_sel,
	3324	+ &gxbb_vclk2_div,
	3325	+ &gxbb_vclk2_input,
	3326	+ &gxbb_vclk2_div1,
	3327	+ &gxbb_vclk2_div2_en,
	3328	+ &gxbb_vclk2_div4_en,
	3329	+ &gxbb_vclk2_div6_en,
	3330	+ &gxbb_vclk2_div12_en,
	3331	+ &gxbb_cts_enci,
	3332	+ &gxbb_cts_enci_sel,
	3333	+ &gxbb_cts_encp,
	3334	+ &gxbb_cts_encp_sel,
	3335	+ &gxbb_cts_vdac,
	3336	+ &gxbb_cts_vdac_sel,
	3337	+ &gxbb_hdmi_tx,
	3338	+ &gxbb_hdmi_tx_sel,
	3339	+ &gxbb_hdmi_sel,
	3340	+ &gxbb_hdmi_div,
	3341	+ &gxbb_hdmi,
	3342	+ &gxbb_gp0_pll_dco,
	3343	+ &gxbb_hdmi_pll,
	3344	+ &gxbb_hdmi_pll_od,
	3345	+ &gxbb_hdmi_pll_od2,
	3346	+ &gxbb_hdmi_pll_dco,
2288	3347	};
2289	3348
2290		-struct clkc_data {
2291		- struct clk_regmap const regmap_clks;
2292		- unsigned int regmap_clks_count;
2293		- struct clk_hw_onecell_data *hw_onecell_data;
	3349	+static struct clk_regmap *const gxl_clk_regmaps[] = {
	3350	+ &gxbb_clk81,
	3351	+ &gxbb_ddr,
	3352	+ &gxbb_dos,
	3353	+ &gxbb_isa,
	3354	+ &gxbb_pl301,
	3355	+ &gxbb_periphs,
	3356	+ &gxbb_spicc,
	3357	+ &gxbb_i2c,
	3358	+ &gxbb_sar_adc,
	3359	+ &gxbb_smart_card,
	3360	+ &gxbb_rng0,
	3361	+ &gxbb_uart0,
	3362	+ &gxbb_sdhc,
	3363	+ &gxbb_stream,
	3364	+ &gxbb_async_fifo,
	3365	+ &gxbb_sdio,
	3366	+ &gxbb_abuf,
	3367	+ &gxbb_hiu_iface,
	3368	+ &gxbb_assist_misc,
	3369	+ &gxbb_spi,
	3370	+ &gxbb_i2s_spdif,
	3371	+ &gxbb_eth,
	3372	+ &gxbb_demux,
	3373	+ &gxbb_aiu_glue,
	3374	+ &gxbb_iec958,
	3375	+ &gxbb_i2s_out,
	3376	+ &gxbb_amclk,
	3377	+ &gxbb_aififo2,
	3378	+ &gxbb_mixer,
	3379	+ &gxbb_mixer_iface,
	3380	+ &gxbb_adc,
	3381	+ &gxbb_blkmv,
	3382	+ &gxbb_aiu,
	3383	+ &gxbb_uart1,
	3384	+ &gxbb_g2d,
	3385	+ &gxbb_usb0,
	3386	+ &gxbb_usb1,
	3387	+ &gxbb_reset,
	3388	+ &gxbb_nand,
	3389	+ &gxbb_dos_parser,
	3390	+ &gxbb_usb,
	3391	+ &gxbb_vdin1,
	3392	+ &gxbb_ahb_arb0,
	3393	+ &gxbb_efuse,
	3394	+ &gxbb_boot_rom,
	3395	+ &gxbb_ahb_data_bus,
	3396	+ &gxbb_ahb_ctrl_bus,
	3397	+ &gxbb_hdmi_intr_sync,
	3398	+ &gxbb_hdmi_pclk,
	3399	+ &gxbb_usb1_ddr_bridge,
	3400	+ &gxbb_usb0_ddr_bridge,
	3401	+ &gxbb_mmc_pclk,
	3402	+ &gxbb_dvin,
	3403	+ &gxbb_uart2,
	3404	+ &gxbb_sana,
	3405	+ &gxbb_vpu_intr,
	3406	+ &gxbb_sec_ahb_ahb3_bridge,
	3407	+ &gxbb_clk81_a53,
	3408	+ &gxbb_vclk2_venci0,
	3409	+ &gxbb_vclk2_venci1,
	3410	+ &gxbb_vclk2_vencp0,
	3411	+ &gxbb_vclk2_vencp1,
	3412	+ &gxbb_gclk_venci_int0,
	3413	+ &gxbb_gclk_vencp_int,
	3414	+ &gxbb_dac_clk,
	3415	+ &gxbb_aoclk_gate,
	3416	+ &gxbb_iec958_gate,
	3417	+ &gxbb_enc480p,
	3418	+ &gxbb_rng1,
	3419	+ &gxbb_gclk_venci_int1,
	3420	+ &gxbb_vclk2_venclmcc,
	3421	+ &gxbb_vclk2_vencl,
	3422	+ &gxbb_vclk_other,
	3423	+ &gxbb_edp,
	3424	+ &gxbb_ao_media_cpu,
	3425	+ &gxbb_ao_ahb_sram,
	3426	+ &gxbb_ao_ahb_bus,
	3427	+ &gxbb_ao_iface,
	3428	+ &gxbb_ao_i2c,
	3429	+ &gxbb_emmc_a,
	3430	+ &gxbb_emmc_b,
	3431	+ &gxbb_emmc_c,
	3432	+ &gxbb_sar_adc_clk,
	3433	+ &gxbb_mali_0,
	3434	+ &gxbb_mali_1,
	3435	+ &gxbb_cts_amclk,
	3436	+ &gxbb_cts_mclk_i958,
	3437	+ &gxbb_32k_clk,
	3438	+ &gxbb_sd_emmc_a_clk0,
	3439	+ &gxbb_sd_emmc_b_clk0,
	3440	+ &gxbb_sd_emmc_c_clk0,
	3441	+ &gxbb_vpu_0,
	3442	+ &gxbb_vpu_1,
	3443	+ &gxbb_vapb_0,
	3444	+ &gxbb_vapb_1,
	3445	+ &gxbb_vapb,
	3446	+ &gxbb_mpeg_clk_div,
	3447	+ &gxbb_sar_adc_clk_div,
	3448	+ &gxbb_mali_0_div,
	3449	+ &gxbb_mali_1_div,
	3450	+ &gxbb_cts_mclk_i958_div,
	3451	+ &gxbb_32k_clk_div,
	3452	+ &gxbb_sd_emmc_a_clk0_div,
	3453	+ &gxbb_sd_emmc_b_clk0_div,
	3454	+ &gxbb_sd_emmc_c_clk0_div,
	3455	+ &gxbb_vpu_0_div,
	3456	+ &gxbb_vpu_1_div,
	3457	+ &gxbb_vapb_0_div,
	3458	+ &gxbb_vapb_1_div,
	3459	+ &gxbb_mpeg_clk_sel,
	3460	+ &gxbb_sar_adc_clk_sel,
	3461	+ &gxbb_mali_0_sel,
	3462	+ &gxbb_mali_1_sel,
	3463	+ &gxbb_mali,
	3464	+ &gxbb_cts_amclk_sel,
	3465	+ &gxbb_cts_mclk_i958_sel,
	3466	+ &gxbb_cts_i958,
	3467	+ &gxbb_32k_clk_sel,
	3468	+ &gxbb_sd_emmc_a_clk0_sel,
	3469	+ &gxbb_sd_emmc_b_clk0_sel,
	3470	+ &gxbb_sd_emmc_c_clk0_sel,
	3471	+ &gxbb_vpu_0_sel,
	3472	+ &gxbb_vpu_1_sel,
	3473	+ &gxbb_vpu,
	3474	+ &gxbb_vapb_0_sel,
	3475	+ &gxbb_vapb_1_sel,
	3476	+ &gxbb_vapb_sel,
	3477	+ &gxbb_mpll0,
	3478	+ &gxbb_mpll1,
	3479	+ &gxbb_mpll2,
	3480	+ &gxl_mpll0_div,
	3481	+ &gxbb_mpll1_div,
	3482	+ &gxbb_mpll2_div,
	3483	+ &gxbb_cts_amclk_div,
	3484	+ &gxbb_fixed_pll,
	3485	+ &gxbb_sys_pll,
	3486	+ &gxbb_mpll_prediv,
	3487	+ &gxbb_fclk_div2,
	3488	+ &gxbb_fclk_div3,
	3489	+ &gxbb_fclk_div4,
	3490	+ &gxbb_fclk_div5,
	3491	+ &gxbb_fclk_div7,
	3492	+ &gxbb_vdec_1_sel,
	3493	+ &gxbb_vdec_1_div,
	3494	+ &gxbb_vdec_1,
	3495	+ &gxbb_vdec_hevc_sel,
	3496	+ &gxbb_vdec_hevc_div,
	3497	+ &gxbb_vdec_hevc,
	3498	+ &gxbb_gen_clk_sel,
	3499	+ &gxbb_gen_clk_div,
	3500	+ &gxbb_gen_clk,
	3501	+ &gxbb_fixed_pll_dco,
	3502	+ &gxbb_sys_pll_dco,
	3503	+ &gxbb_gp0_pll,
	3504	+ &gxbb_vid_pll,
	3505	+ &gxbb_vid_pll_sel,
	3506	+ &gxbb_vid_pll_div,
	3507	+ &gxbb_vclk,
	3508	+ &gxbb_vclk_sel,
	3509	+ &gxbb_vclk_div,
	3510	+ &gxbb_vclk_input,
	3511	+ &gxbb_vclk_div1,
	3512	+ &gxbb_vclk_div2_en,
	3513	+ &gxbb_vclk_div4_en,
	3514	+ &gxbb_vclk_div6_en,
	3515	+ &gxbb_vclk_div12_en,
	3516	+ &gxbb_vclk2,
	3517	+ &gxbb_vclk2_sel,
	3518	+ &gxbb_vclk2_div,
	3519	+ &gxbb_vclk2_input,
	3520	+ &gxbb_vclk2_div1,
	3521	+ &gxbb_vclk2_div2_en,
	3522	+ &gxbb_vclk2_div4_en,
	3523	+ &gxbb_vclk2_div6_en,
	3524	+ &gxbb_vclk2_div12_en,
	3525	+ &gxbb_cts_enci,
	3526	+ &gxbb_cts_enci_sel,
	3527	+ &gxbb_cts_encp,
	3528	+ &gxbb_cts_encp_sel,
	3529	+ &gxbb_cts_vdac,
	3530	+ &gxbb_cts_vdac_sel,
	3531	+ &gxbb_hdmi_tx,
	3532	+ &gxbb_hdmi_tx_sel,
	3533	+ &gxbb_hdmi_sel,
	3534	+ &gxbb_hdmi_div,
	3535	+ &gxbb_hdmi,
	3536	+ &gxl_gp0_pll_dco,
	3537	+ &gxl_hdmi_pll,
	3538	+ &gxl_hdmi_pll_od,
	3539	+ &gxl_hdmi_pll_od2,
	3540	+ &gxl_hdmi_pll_dco,
	3541	+ &gxl_acodec,
2294	3542	};
2295	3543
2296		-static const struct clkc_data gxbb_clkc_data = {
	3544	+static const struct meson_eeclkc_data gxbb_clkc_data = {
2297	3545	.regmap_clks = gxbb_clk_regmaps,
2298		- .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps),
	3546	+ .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
2299	3547	.hw_onecell_data = &gxbb_hw_onecell_data,
2300	3548	};
2301	3549
2302		-static const struct clkc_data gxl_clkc_data = {
	3550	+static const struct meson_eeclkc_data gxl_clkc_data = {
2303	3551	.regmap_clks = gxl_clk_regmaps,
2304		- .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps),
	3552	+ .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
2305	3553	.hw_onecell_data = &gxl_hw_onecell_data,
2306	3554	};
2307	3555
..	..	@@ -2310,57 +3558,15 @@
2310	3558	{ .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
2311	3559	{},
2312	3560	};
2313		-
2314		-static int gxbb_clkc_probe(struct platform_device *pdev)
2315		-{
2316		- const struct clkc_data *clkc_data;
2317		- struct regmap *map;
2318		- int ret, i;
2319		- struct device *dev = &pdev->dev;
2320		-
2321		- clkc_data = of_device_get_match_data(dev);
2322		- if (!clkc_data)
2323		- return -EINVAL;
2324		-
2325		- /* Get the hhi system controller node if available */
2326		- map = syscon_node_to_regmap(of_get_parent(dev->of_node));
2327		- if (IS_ERR(map)) {
2328		- dev_err(dev, "failed to get HHI regmap\n");
2329		- return PTR_ERR(map);
2330		- }
2331		-
2332		- /* Populate regmap for the common regmap backed clocks */
2333		- for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
2334		- gx_clk_regmaps[i]->map = map;
2335		-
2336		- /* Populate regmap for soc specific clocks */
2337		- for (i = 0; i < clkc_data->regmap_clks_count; i++)
2338		- clkc_data->regmap_clks[i]->map = map;
2339		-
2340		- /* Register all clks */
2341		- for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
2342		- /* array might be sparse */
2343		- if (!clkc_data->hw_onecell_data->hws[i])
2344		- continue;
2345		-
2346		- ret = devm_clk_hw_register(dev,
2347		- clkc_data->hw_onecell_data->hws[i]);
2348		- if (ret) {
2349		- dev_err(dev, "Clock registration failed\n");
2350		- return ret;
2351		- }
2352		- }
2353		-
2354		- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
2355		- clkc_data->hw_onecell_data);
2356		-}
	3561	+MODULE_DEVICE_TABLE(of, clkc_match_table);
2357	3562
2358	3563	static struct platform_driver gxbb_driver = {
2359		- .probe = gxbb_clkc_probe,
	3564	+ .probe = meson_eeclkc_probe,
2360	3565	.driver = {
2361	3566	.name = "gxbb-clkc",
2362	3567	.of_match_table = clkc_match_table,
2363	3568	},
2364	3569	};
2365	3570
2366		-builtin_platform_driver(gxbb_driver);
	3571	+module_platform_driver(gxbb_driver);
	3572	+MODULE_LICENSE("GPL v2");