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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/clk/meson/clk-regmap.h
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@@ -26,7 +26,10 @@
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 	void		*data;
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 };
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-#define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw)
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+static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw)
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+{
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+	return container_of(hw, struct clk_regmap, hw);
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+}
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 /**
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  * struct clk_regmap_gate_data - regmap backed gate specific data
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@@ -51,6 +54,7 @@
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 }
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 extern const struct clk_ops clk_regmap_gate_ops;
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+extern const struct clk_ops clk_regmap_gate_ro_ops;
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 /**
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  * struct clk_regmap_div_data - regmap backed adjustable divider specific data
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@@ -110,4 +114,24 @@
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 extern const struct clk_ops clk_regmap_mux_ops;
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 extern const struct clk_ops clk_regmap_mux_ro_ops;
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+#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname)			\
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+struct clk_regmap _name = {						\
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+	.data = &(struct clk_regmap_gate_data){				\
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+		.offset = (_reg),					\
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+		.bit_idx = (_bit),					\
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+	},								\
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+	.hw.init = &(struct clk_init_data) {				\
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+		.name = #_name,						\
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+		.ops = _ops,						\
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+		.parent_hws = (const struct clk_hw *[]) { _pname },	\
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+		.num_parents = 1,					\
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+		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),	\
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+	},								\
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+}
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+
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+#define MESON_PCLK(_name, _reg, _bit, _pname)	\
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+	__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
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+
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+#define MESON_PCLK_RO(_name, _reg, _bit, _pname)	\
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+	__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
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 #endif /* __CLK_REGMAP_H */