forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb
kernel/drivers/clk/meson/axg-audio.h
....@@ -20,6 +20,9 @@
2020 #define AUDIO_MCLK_D_CTRL 0x010
2121 #define AUDIO_MCLK_E_CTRL 0x014
2222 #define AUDIO_MCLK_F_CTRL 0x018
23
+#define AUDIO_MST_PAD_CTRL0 0x01c
24
+#define AUDIO_MST_PAD_CTRL1 0x020
25
+#define AUDIO_SW_RESET 0x024
2326 #define AUDIO_MST_A_SCLK_CTRL0 0x040
2427 #define AUDIO_MST_A_SCLK_CTRL1 0x044
2528 #define AUDIO_MST_B_SCLK_CTRL0 0x048
....@@ -45,21 +48,27 @@
4548 #define AUDIO_CLK_LOCKER_CTRL 0x0A8
4649 #define AUDIO_CLK_PDMIN_CTRL0 0x0AC
4750 #define AUDIO_CLK_PDMIN_CTRL1 0x0B0
51
+#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
4852
53
+/* SM1 introduce new register and some shifts :( */
54
+#define AUDIO_CLK_GATE_EN1 0x004
55
+#define AUDIO_SM1_MCLK_A_CTRL 0x008
56
+#define AUDIO_SM1_MCLK_B_CTRL 0x00C
57
+#define AUDIO_SM1_MCLK_C_CTRL 0x010
58
+#define AUDIO_SM1_MCLK_D_CTRL 0x014
59
+#define AUDIO_SM1_MCLK_E_CTRL 0x018
60
+#define AUDIO_SM1_MCLK_F_CTRL 0x01C
61
+#define AUDIO_SM1_MST_PAD_CTRL0 0x020
62
+#define AUDIO_SM1_MST_PAD_CTRL1 0x024
63
+#define AUDIO_SM1_SW_RESET0 0x028
64
+#define AUDIO_SM1_SW_RESET1 0x02C
65
+#define AUDIO_CLK81_CTRL 0x030
66
+#define AUDIO_CLK81_EN 0x034
4967 /*
5068 * CLKID index values
5169 * These indices are entirely contrived and do not map onto the hardware.
5270 */
5371
54
-#define AUD_CLKID_PCLK 0
55
-#define AUD_CLKID_MST0 1
56
-#define AUD_CLKID_MST1 2
57
-#define AUD_CLKID_MST2 3
58
-#define AUD_CLKID_MST3 4
59
-#define AUD_CLKID_MST4 5
60
-#define AUD_CLKID_MST5 6
61
-#define AUD_CLKID_MST6 7
62
-#define AUD_CLKID_MST7 8
6372 #define AUD_CLKID_MST_A_MCLK_SEL 59
6473 #define AUD_CLKID_MST_B_MCLK_SEL 60
6574 #define AUD_CLKID_MST_C_MCLK_SEL 61
....@@ -118,10 +127,17 @@
118127 #define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
119128 #define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
120129 #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
130
+#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
131
+#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
132
+#define AUD_CLKID_CLK81_EN 173
133
+#define AUD_CLKID_SYSCLK_A_DIV 174
134
+#define AUD_CLKID_SYSCLK_B_DIV 175
135
+#define AUD_CLKID_SYSCLK_A_EN 176
136
+#define AUD_CLKID_SYSCLK_B_EN 177
121137
122138 /* include the CLKIDs which are part of the DT bindings */
123139 #include <dt-bindings/clock/axg-audio-clkc.h>
124140
125
-#define NR_CLKS 151
141
+#define NR_CLKS 178
126142
127143 #endif /*__AXG_AUDIO_CLKC_H */