forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/clk/meson/axg-audio.c
....@@ -12,32 +12,29 @@
1212 #include <linux/platform_device.h>
1313 #include <linux/regmap.h>
1414 #include <linux/reset.h>
15
+#include <linux/reset-controller.h>
1516 #include <linux/slab.h>
1617 
17
-#include "clkc-audio.h"
1818 #include "axg-audio.h"
19
+#include "clk-regmap.h"
20
+#include "clk-phase.h"
21
+#include "sclk-div.h"
1922 
20
-#define AXG_MST_IN_COUNT	8
21
-#define AXG_SLV_SCLK_COUNT	10
22
-#define AXG_SLV_LRCLK_COUNT	10
23
-
24
-#define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags)		\
25
-struct clk_regmap axg_##_name = {					\
23
+#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) {			\
2624 	.data = &(struct clk_regmap_gate_data){				\
2725 		.offset = (_reg),					\
2826 		.bit_idx = (_bit),					\
2927 	},								\
3028 	.hw.init = &(struct clk_init_data) {				\
31
-		.name = "axg_"#_name,					\
29
+		.name = "aud_"#_name,					\
3230 		.ops = &clk_regmap_gate_ops,				\
33
-		.parent_names = (const char *[]){ _pname },		\
31
+		.parent_names = (const char *[]){ #_pname },		\
3432 		.num_parents = 1,					\
3533 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
3634 	},								\
3735 }
3836 
39
-#define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \
40
-struct clk_regmap axg_##_name = {					\
37
+#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) {	\
4138 	.data = &(struct clk_regmap_mux_data){				\
4239 		.offset = (_reg),					\
4340 		.mask = (_mask),					\
....@@ -45,16 +42,15 @@
4542 		.flags = (_dflags),					\
4643 	},								\
4744 	.hw.init = &(struct clk_init_data){				\
48
-		.name = "axg_"#_name,					\
45
+		.name = "aud_"#_name,					\
4946 		.ops = &clk_regmap_mux_ops,				\
50
-		.parent_names = (_pnames),				\
51
-		.num_parents = ARRAY_SIZE(_pnames),			\
47
+		.parent_data = _pdata,					\
48
+		.num_parents = ARRAY_SIZE(_pdata),			\
5249 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
5350 	},								\
5451 }
5552 
56
-#define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \
57
-struct clk_regmap axg_##_name = {					\
53
+#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \
5854 	.data = &(struct clk_regmap_div_data){				\
5955 		.offset = (_reg),					\
6056 		.shift = (_shift),					\
....@@ -62,105 +58,29 @@
6258 		.flags = (_dflags),					\
6359 	},								\
6460 	.hw.init = &(struct clk_init_data){				\
65
-		.name = "axg_"#_name,					\
61
+		.name = "aud_"#_name,					\
6662 		.ops = &clk_regmap_divider_ops,				\
67
-		.parent_names = (const char *[]) { _pname },		\
63
+		.parent_names = (const char *[]){ #_pname },		\
6864 		.num_parents = 1,					\
6965 		.flags = (_iflags),					\
7066 	},								\
7167 }
7268 
73
-#define AXG_PCLK_GATE(_name, _bit)				\
74
-	AXG_AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "axg_audio_pclk", 0)
69
+#define AUD_PCLK_GATE(_name, _reg, _bit) {				\
70
+	.data = &(struct clk_regmap_gate_data){				\
71
+		.offset = (_reg),					\
72
+		.bit_idx = (_bit),					\
73
+	},								\
74
+	.hw.init = &(struct clk_init_data) {				\
75
+		.name = "aud_"#_name,					\
76
+		.ops = &clk_regmap_gate_ops,				\
77
+		.parent_names = (const char *[]){ "aud_top" },		\
78
+		.num_parents = 1,					\
79
+	},								\
80
+}
7581 
76
-/* Audio peripheral clocks */
77
-static AXG_PCLK_GATE(ddr_arb,	   0);
78
-static AXG_PCLK_GATE(pdm,	   1);
79
-static AXG_PCLK_GATE(tdmin_a,	   2);
80
-static AXG_PCLK_GATE(tdmin_b,	   3);
81
-static AXG_PCLK_GATE(tdmin_c,	   4);
82
-static AXG_PCLK_GATE(tdmin_lb,	   5);
83
-static AXG_PCLK_GATE(tdmout_a,	   6);
84
-static AXG_PCLK_GATE(tdmout_b,	   7);
85
-static AXG_PCLK_GATE(tdmout_c,	   8);
86
-static AXG_PCLK_GATE(frddr_a,	   9);
87
-static AXG_PCLK_GATE(frddr_b,	   10);
88
-static AXG_PCLK_GATE(frddr_c,	   11);
89
-static AXG_PCLK_GATE(toddr_a,	   12);
90
-static AXG_PCLK_GATE(toddr_b,	   13);
91
-static AXG_PCLK_GATE(toddr_c,	   14);
92
-static AXG_PCLK_GATE(loopback,	   15);
93
-static AXG_PCLK_GATE(spdifin,	   16);
94
-static AXG_PCLK_GATE(spdifout,	   17);
95
-static AXG_PCLK_GATE(resample,	   18);
96
-static AXG_PCLK_GATE(power_detect, 19);
97
-
98
-/* Audio Master Clocks */
99
-static const char * const mst_mux_parent_names[] = {
100
-	"axg_mst_in0", "axg_mst_in1", "axg_mst_in2", "axg_mst_in3",
101
-	"axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7",
102
-};
103
-
104
-#define AXG_MST_MCLK_MUX(_name, _reg)					\
105
-	AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, CLK_MUX_ROUND_CLOSEST, \
106
-		    mst_mux_parent_names, CLK_SET_RATE_PARENT)
107
-
108
-static AXG_MST_MCLK_MUX(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
109
-static AXG_MST_MCLK_MUX(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
110
-static AXG_MST_MCLK_MUX(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
111
-static AXG_MST_MCLK_MUX(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
112
-static AXG_MST_MCLK_MUX(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
113
-static AXG_MST_MCLK_MUX(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
114
-static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
115
-static AXG_MST_MCLK_MUX(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
116
-static AXG_MST_MCLK_MUX(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
117
-static AXG_MST_MCLK_MUX(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
118
-
119
-#define AXG_MST_MCLK_DIV(_name, _reg)					\
120
-	AXG_AUD_DIV(_name##_div, _reg, 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \
121
-		    "axg_"#_name"_sel", CLK_SET_RATE_PARENT)		\
122
-
123
-static AXG_MST_MCLK_DIV(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
124
-static AXG_MST_MCLK_DIV(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
125
-static AXG_MST_MCLK_DIV(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
126
-static AXG_MST_MCLK_DIV(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
127
-static AXG_MST_MCLK_DIV(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
128
-static AXG_MST_MCLK_DIV(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
129
-static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
130
-static AXG_MST_MCLK_DIV(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
131
-static AXG_MST_MCLK_DIV(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
132
-static AXG_MST_MCLK_DIV(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
133
-
134
-#define AXG_MST_MCLK_GATE(_name, _reg)					\
135
-	AXG_AUD_GATE(_name, _reg, 31,  "axg_"#_name"_div",		\
136
-		     CLK_SET_RATE_PARENT)
137
-
138
-static AXG_MST_MCLK_GATE(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
139
-static AXG_MST_MCLK_GATE(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
140
-static AXG_MST_MCLK_GATE(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
141
-static AXG_MST_MCLK_GATE(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
142
-static AXG_MST_MCLK_GATE(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
143
-static AXG_MST_MCLK_GATE(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
144
-static AXG_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
145
-static AXG_MST_MCLK_GATE(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
146
-static AXG_MST_MCLK_GATE(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
147
-static AXG_MST_MCLK_GATE(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
148
-
149
-/* Sample Clocks */
150
-#define AXG_MST_SCLK_PRE_EN(_name, _reg)			\
151
-	AXG_AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,	\
152
-		     "axg_mst_"#_name"_mclk", 0)
153
-
154
-static AXG_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
155
-static AXG_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
156
-static AXG_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
157
-static AXG_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
158
-static AXG_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
159
-static AXG_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
160
-
161
-#define AXG_AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\
162
-			 _hi_shift, _hi_width, _pname, _iflags)		\
163
-struct clk_regmap axg_##_name = {					\
82
+#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\
83
+		     _hi_shift, _hi_width, _pname, _iflags) {		\
16484 	.data = &(struct meson_sclk_div_data) {				\
16585 		.div = {						\
16686 			.reg_off = (_reg),				\
....@@ -174,40 +94,16 @@
17494 		},							\
17595 	},								\
17696 	.hw.init = &(struct clk_init_data) {				\
177
-		.name = "axg_"#_name,					\
97
+		.name = "aud_"#_name,					\
17898 		.ops = &meson_sclk_div_ops,				\
179
-		.parent_names = (const char *[]) { _pname },		\
99
+		.parent_names = (const char *[]){ #_pname },		\
180100 		.num_parents = 1,					\
181101 		.flags = (_iflags),					\
182102 	},								\
183103 }
184104 
185
-#define AXG_MST_SCLK_DIV(_name, _reg)					\
186
-	AXG_AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
187
-			 "axg_mst_"#_name"_sclk_pre_en",		\
188
-			 CLK_SET_RATE_PARENT)
189
-
190
-static AXG_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
191
-static AXG_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
192
-static AXG_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
193
-static AXG_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
194
-static AXG_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
195
-static AXG_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
196
-
197
-#define AXG_MST_SCLK_POST_EN(_name, _reg)				\
198
-	AXG_AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,		\
199
-		     "axg_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
200
-
201
-static AXG_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
202
-static AXG_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
203
-static AXG_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
204
-static AXG_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
205
-static AXG_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
206
-static AXG_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
207
-
208
-#define AXG_AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
209
-			 _pname, _iflags)				\
210
-struct clk_regmap axg_##_name = {					\
105
+#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,	\
106
+		     _pname, _iflags) {					\
211107 	.data = &(struct meson_clk_triphase_data) {			\
212108 		.ph0 = {						\
213109 			.reg_off = (_reg),				\
....@@ -226,141 +122,690 @@
226122 		},							\
227123 	},								\
228124 	.hw.init = &(struct clk_init_data) {				\
229
-		.name = "axg_"#_name,					\
125
+		.name = "aud_"#_name,					\
230126 		.ops = &meson_clk_triphase_ops,				\
231
-		.parent_names = (const char *[]) { _pname },		\
127
+		.parent_names = (const char *[]){ #_pname },		\
232128 		.num_parents = 1,					\
233129 		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\
234130 	},								\
235131 }
236132 
237
-#define AXG_MST_SCLK(_name, _reg)					\
238
-	AXG_AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\
239
-			 "axg_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
240
-
241
-static AXG_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
242
-static AXG_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
243
-static AXG_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
244
-static AXG_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
245
-static AXG_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
246
-static AXG_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
247
-
248
-#define AXG_MST_LRCLK_DIV(_name, _reg)					\
249
-	AXG_AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
250
-		    "axg_mst_"#_name"_sclk_post_en", 0)			\
251
-
252
-static AXG_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
253
-static AXG_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
254
-static AXG_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
255
-static AXG_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
256
-static AXG_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
257
-static AXG_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
258
-
259
-#define AXG_MST_LRCLK(_name, _reg)					\
260
-	AXG_AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\
261
-			 "axg_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
262
-
263
-static AXG_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
264
-static AXG_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
265
-static AXG_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
266
-static AXG_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
267
-static AXG_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
268
-static AXG_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
269
-
270
-static const char * const tdm_sclk_parent_names[] = {
271
-	"axg_mst_a_sclk", "axg_mst_b_sclk", "axg_mst_c_sclk",
272
-	"axg_mst_d_sclk", "axg_mst_e_sclk", "axg_mst_f_sclk",
273
-	"axg_slv_sclk0", "axg_slv_sclk1", "axg_slv_sclk2",
274
-	"axg_slv_sclk3", "axg_slv_sclk4", "axg_slv_sclk5",
275
-	"axg_slv_sclk6", "axg_slv_sclk7", "axg_slv_sclk8",
276
-	"axg_slv_sclk9"
277
-};
278
-
279
-#define AXG_TDM_SCLK_MUX(_name, _reg)				\
280
-	AXG_AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,	\
281
-		    CLK_MUX_ROUND_CLOSEST,			\
282
-		    tdm_sclk_parent_names, 0)
283
-
284
-static AXG_TDM_SCLK_MUX(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
285
-static AXG_TDM_SCLK_MUX(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
286
-static AXG_TDM_SCLK_MUX(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
287
-static AXG_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
288
-static AXG_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
289
-static AXG_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
290
-static AXG_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
291
-
292
-#define AXG_TDM_SCLK_PRE_EN(_name, _reg)				\
293
-	AXG_AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,		\
294
-		     "axg_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
295
-
296
-static AXG_TDM_SCLK_PRE_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
297
-static AXG_TDM_SCLK_PRE_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
298
-static AXG_TDM_SCLK_PRE_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
299
-static AXG_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
300
-static AXG_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
301
-static AXG_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
302
-static AXG_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
303
-
304
-#define AXG_TDM_SCLK_POST_EN(_name, _reg)				\
305
-	AXG_AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,		\
306
-		     "axg_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
307
-
308
-static AXG_TDM_SCLK_POST_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
309
-static AXG_TDM_SCLK_POST_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
310
-static AXG_TDM_SCLK_POST_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
311
-static AXG_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
312
-static AXG_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
313
-static AXG_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
314
-static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
315
-
316
-#define AXG_TDM_SCLK(_name, _reg)					\
317
-	struct clk_regmap axg_tdm##_name##_sclk = {			\
133
+#define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) {	\
318134 	.data = &(struct meson_clk_phase_data) {			\
319135 		.ph = {							\
320136 			.reg_off = (_reg),				\
321
-			.shift   = 29,					\
322
-			.width   = 1,					\
137
+			.shift   = (_shift),				\
138
+			.width   = (_width),				\
323139 		},							\
324140 	},								\
325141 	.hw.init = &(struct clk_init_data) {				\
326
-		.name = "axg_tdm"#_name"_sclk",				\
142
+		.name = "aud_"#_name,					\
327143 		.ops = &meson_clk_phase_ops,				\
328
-		.parent_names = (const char *[])			\
329
-		{ "axg_tdm"#_name"_sclk_post_en" },			\
144
+		.parent_names = (const char *[]){ #_pname },		\
330145 		.num_parents = 1,					\
331
-		.flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT,	\
146
+		.flags = (_iflags),					\
332147 	},								\
333148 }
334149 
335
-static AXG_TDM_SCLK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
336
-static AXG_TDM_SCLK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
337
-static AXG_TDM_SCLK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
338
-static AXG_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
339
-static AXG_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
340
-static AXG_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
341
-static AXG_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
150
+#define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname,	\
151
+		    _iflags) {						\
152
+	.data = &(struct meson_sclk_ws_inv_data) {			\
153
+		.ph = {							\
154
+			.reg_off = (_reg),				\
155
+			.shift   = (_shift_ph),				\
156
+			.width   = (_width),				\
157
+		},							\
158
+		.ws = {							\
159
+			.reg_off = (_reg),				\
160
+			.shift   = (_shift_ws),				\
161
+			.width   = (_width),				\
162
+		},							\
163
+	},								\
164
+	.hw.init = &(struct clk_init_data) {				\
165
+		.name = "aud_"#_name,					\
166
+		.ops = &meson_clk_phase_ops,				\
167
+		.parent_names = (const char *[]){ #_pname },		\
168
+		.num_parents = 1,					\
169
+		.flags = (_iflags),					\
170
+	},								\
171
+}
342172 
343
-static const char * const tdm_lrclk_parent_names[] = {
344
-	"axg_mst_a_lrclk", "axg_mst_b_lrclk", "axg_mst_c_lrclk",
345
-	"axg_mst_d_lrclk", "axg_mst_e_lrclk", "axg_mst_f_lrclk",
346
-	"axg_slv_lrclk0", "axg_slv_lrclk1", "axg_slv_lrclk2",
347
-	"axg_slv_lrclk3", "axg_slv_lrclk4", "axg_slv_lrclk5",
348
-	"axg_slv_lrclk6", "axg_slv_lrclk7", "axg_slv_lrclk8",
349
-	"axg_slv_lrclk9"
173
+/* Audio Master Clocks */
174
+static const struct clk_parent_data mst_mux_parent_data[] = {
175
+	{ .fw_name = "mst_in0", },
176
+	{ .fw_name = "mst_in1", },
177
+	{ .fw_name = "mst_in2", },
178
+	{ .fw_name = "mst_in3", },
179
+	{ .fw_name = "mst_in4", },
180
+	{ .fw_name = "mst_in5", },
181
+	{ .fw_name = "mst_in6", },
182
+	{ .fw_name = "mst_in7", },
350183 };
351184 
352
-#define AXG_TDM_LRLCK(_name, _reg)		       \
353
-	AXG_AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
354
-		    CLK_MUX_ROUND_CLOSEST,	       \
355
-		    tdm_lrclk_parent_names, 0)
185
+#define AUD_MST_MUX(_name, _reg, _flag)					\
186
+	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,			\
187
+		mst_mux_parent_data, 0)
188
+#define AUD_MST_DIV(_name, _reg, _flag)					\
189
+	AUD_DIV(_name##_div, _reg, 0, 16, _flag,			\
190
+		aud_##_name##_sel, CLK_SET_RATE_PARENT)
191
+#define AUD_MST_MCLK_GATE(_name, _reg)					\
192
+	AUD_GATE(_name, _reg, 31, aud_##_name##_div,			\
193
+		 CLK_SET_RATE_PARENT)
356194 
357
-static AXG_TDM_LRLCK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
358
-static AXG_TDM_LRLCK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
359
-static AXG_TDM_LRLCK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
360
-static AXG_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
361
-static AXG_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
362
-static AXG_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
363
-static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
195
+#define AUD_MST_MCLK_MUX(_name, _reg)					\
196
+	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
197
+#define AUD_MST_MCLK_DIV(_name, _reg)					\
198
+	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
199
+
200
+#define AUD_MST_SYS_MUX(_name, _reg)					\
201
+	AUD_MST_MUX(_name, _reg, 0)
202
+#define AUD_MST_SYS_DIV(_name, _reg)					\
203
+	AUD_MST_DIV(_name, _reg, 0)
204
+
205
+/* Sample Clocks */
206
+#define AUD_MST_SCLK_PRE_EN(_name, _reg)				\
207
+	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,			\
208
+		 aud_mst_##_name##_mclk, 0)
209
+#define AUD_MST_SCLK_DIV(_name, _reg)					\
210
+	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\
211
+		     aud_mst_##_name##_sclk_pre_en,			\
212
+		     CLK_SET_RATE_PARENT)
213
+#define AUD_MST_SCLK_POST_EN(_name, _reg)				\
214
+	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,			\
215
+		 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
216
+#define AUD_MST_SCLK(_name, _reg)					\
217
+	AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\
218
+		     aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
219
+
220
+#define AUD_MST_LRCLK_DIV(_name, _reg)					\
221
+	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\
222
+		     aud_mst_##_name##_sclk_post_en, 0)
223
+#define AUD_MST_LRCLK(_name, _reg)					\
224
+	AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\
225
+		     aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
226
+
227
+/* TDM bit clock sources */
228
+static const struct clk_parent_data tdm_sclk_parent_data[] = {
229
+	{ .name = "aud_mst_a_sclk", .index = -1, },
230
+	{ .name = "aud_mst_b_sclk", .index = -1, },
231
+	{ .name = "aud_mst_c_sclk", .index = -1, },
232
+	{ .name = "aud_mst_d_sclk", .index = -1, },
233
+	{ .name = "aud_mst_e_sclk", .index = -1, },
234
+	{ .name = "aud_mst_f_sclk", .index = -1, },
235
+	{ .fw_name = "slv_sclk0", },
236
+	{ .fw_name = "slv_sclk1", },
237
+	{ .fw_name = "slv_sclk2", },
238
+	{ .fw_name = "slv_sclk3", },
239
+	{ .fw_name = "slv_sclk4", },
240
+	{ .fw_name = "slv_sclk5", },
241
+	{ .fw_name = "slv_sclk6", },
242
+	{ .fw_name = "slv_sclk7", },
243
+	{ .fw_name = "slv_sclk8", },
244
+	{ .fw_name = "slv_sclk9", },
245
+};
246
+
247
+/* TDM sample clock sources */
248
+static const struct clk_parent_data tdm_lrclk_parent_data[] = {
249
+	{ .name = "aud_mst_a_lrclk", .index = -1, },
250
+	{ .name = "aud_mst_b_lrclk", .index = -1, },
251
+	{ .name = "aud_mst_c_lrclk", .index = -1, },
252
+	{ .name = "aud_mst_d_lrclk", .index = -1, },
253
+	{ .name = "aud_mst_e_lrclk", .index = -1, },
254
+	{ .name = "aud_mst_f_lrclk", .index = -1, },
255
+	{ .fw_name = "slv_lrclk0", },
256
+	{ .fw_name = "slv_lrclk1", },
257
+	{ .fw_name = "slv_lrclk2", },
258
+	{ .fw_name = "slv_lrclk3", },
259
+	{ .fw_name = "slv_lrclk4", },
260
+	{ .fw_name = "slv_lrclk5", },
261
+	{ .fw_name = "slv_lrclk6", },
262
+	{ .fw_name = "slv_lrclk7", },
263
+	{ .fw_name = "slv_lrclk8", },
264
+	{ .fw_name = "slv_lrclk9", },
265
+};
266
+
267
+#define AUD_TDM_SCLK_MUX(_name, _reg)					\
268
+	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,			\
269
+		CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0)
270
+#define AUD_TDM_SCLK_PRE_EN(_name, _reg)				\
271
+	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,			\
272
+		 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
273
+#define AUD_TDM_SCLK_POST_EN(_name, _reg)				\
274
+	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,			\
275
+		 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
276
+#define AUD_TDM_SCLK(_name, _reg)					\
277
+	AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29,			\
278
+		  aud_tdm##_name##_sclk_post_en,			\
279
+		  CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
280
+#define AUD_TDM_SCLK_WS(_name, _reg)					\
281
+	AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28,			\
282
+		    aud_tdm##_name##_sclk_post_en,			\
283
+		    CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)
284
+
285
+#define AUD_TDM_LRLCK(_name, _reg)					\
286
+	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,			\
287
+		CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0)
288
+
289
+/* Pad master clock sources */
290
+static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
291
+	{ .name = "aud_mst_a_mclk", .index = -1,  },
292
+	{ .name = "aud_mst_b_mclk", .index = -1,  },
293
+	{ .name = "aud_mst_c_mclk", .index = -1,  },
294
+	{ .name = "aud_mst_d_mclk", .index = -1,  },
295
+	{ .name = "aud_mst_e_mclk", .index = -1,  },
296
+	{ .name = "aud_mst_f_mclk", .index = -1,  },
297
+};
298
+
299
+/* Pad bit clock sources */
300
+static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
301
+	{ .name = "aud_mst_a_sclk", .index = -1, },
302
+	{ .name = "aud_mst_b_sclk", .index = -1, },
303
+	{ .name = "aud_mst_c_sclk", .index = -1, },
304
+	{ .name = "aud_mst_d_sclk", .index = -1, },
305
+	{ .name = "aud_mst_e_sclk", .index = -1, },
306
+	{ .name = "aud_mst_f_sclk", .index = -1, },
307
+};
308
+
309
+/* Pad sample clock sources */
310
+static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
311
+	{ .name = "aud_mst_a_lrclk", .index = -1, },
312
+	{ .name = "aud_mst_b_lrclk", .index = -1, },
313
+	{ .name = "aud_mst_c_lrclk", .index = -1, },
314
+	{ .name = "aud_mst_d_lrclk", .index = -1, },
315
+	{ .name = "aud_mst_e_lrclk", .index = -1, },
316
+	{ .name = "aud_mst_f_lrclk", .index = -1, },
317
+};
318
+
319
+#define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)		\
320
+	AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents,		\
321
+		CLK_SET_RATE_NO_REPARENT)
322
+
323
+/* Common Clocks */
324
+static struct clk_regmap ddr_arb =
325
+	AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0);
326
+static struct clk_regmap pdm =
327
+	AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1);
328
+static struct clk_regmap tdmin_a =
329
+	AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2);
330
+static struct clk_regmap tdmin_b =
331
+	AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3);
332
+static struct clk_regmap tdmin_c =
333
+	AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4);
334
+static struct clk_regmap tdmin_lb =
335
+	AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5);
336
+static struct clk_regmap tdmout_a =
337
+	AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6);
338
+static struct clk_regmap tdmout_b =
339
+	AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7);
340
+static struct clk_regmap tdmout_c =
341
+	AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8);
342
+static struct clk_regmap frddr_a =
343
+	AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9);
344
+static struct clk_regmap frddr_b =
345
+	AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10);
346
+static struct clk_regmap frddr_c =
347
+	AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11);
348
+static struct clk_regmap toddr_a =
349
+	AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12);
350
+static struct clk_regmap toddr_b =
351
+	AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13);
352
+static struct clk_regmap toddr_c =
353
+	AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14);
354
+static struct clk_regmap loopback =
355
+	AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15);
356
+static struct clk_regmap spdifin =
357
+	AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16);
358
+static struct clk_regmap spdifout =
359
+	AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17);
360
+static struct clk_regmap resample =
361
+	AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18);
362
+static struct clk_regmap power_detect =
363
+	AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19);
364
+
365
+static struct clk_regmap spdifout_clk_sel =
366
+	AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
367
+static struct clk_regmap pdm_dclk_sel =
368
+	AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
369
+static struct clk_regmap spdifin_clk_sel =
370
+	AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
371
+static struct clk_regmap pdm_sysclk_sel =
372
+	AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
373
+static struct clk_regmap spdifout_b_clk_sel =
374
+	AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
375
+
376
+static struct clk_regmap spdifout_clk_div =
377
+	AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
378
+static struct clk_regmap pdm_dclk_div =
379
+	AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
380
+static struct clk_regmap spdifin_clk_div =
381
+	AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
382
+static struct clk_regmap pdm_sysclk_div =
383
+	AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
384
+static struct clk_regmap spdifout_b_clk_div =
385
+	AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
386
+
387
+static struct clk_regmap spdifout_clk =
388
+	AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
389
+static struct clk_regmap spdifin_clk =
390
+	AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
391
+static struct clk_regmap pdm_dclk =
392
+	AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
393
+static struct clk_regmap pdm_sysclk =
394
+	AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
395
+static struct clk_regmap spdifout_b_clk =
396
+	AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
397
+
398
+static struct clk_regmap mst_a_sclk_pre_en =
399
+	AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
400
+static struct clk_regmap mst_b_sclk_pre_en =
401
+	AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
402
+static struct clk_regmap mst_c_sclk_pre_en =
403
+	AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
404
+static struct clk_regmap mst_d_sclk_pre_en =
405
+	AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
406
+static struct clk_regmap mst_e_sclk_pre_en =
407
+	AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
408
+static struct clk_regmap mst_f_sclk_pre_en =
409
+	AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
410
+
411
+static struct clk_regmap mst_a_sclk_div =
412
+	AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
413
+static struct clk_regmap mst_b_sclk_div =
414
+	AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
415
+static struct clk_regmap mst_c_sclk_div =
416
+	AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
417
+static struct clk_regmap mst_d_sclk_div =
418
+	AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
419
+static struct clk_regmap mst_e_sclk_div =
420
+	AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
421
+static struct clk_regmap mst_f_sclk_div =
422
+	AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
423
+
424
+static struct clk_regmap mst_a_sclk_post_en =
425
+	AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
426
+static struct clk_regmap mst_b_sclk_post_en =
427
+	AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
428
+static struct clk_regmap mst_c_sclk_post_en =
429
+	AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
430
+static struct clk_regmap mst_d_sclk_post_en =
431
+	AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
432
+static struct clk_regmap mst_e_sclk_post_en =
433
+	AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
434
+static struct clk_regmap mst_f_sclk_post_en =
435
+	AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
436
+
437
+static struct clk_regmap mst_a_sclk =
438
+	AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
439
+static struct clk_regmap mst_b_sclk =
440
+	AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
441
+static struct clk_regmap mst_c_sclk =
442
+	AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
443
+static struct clk_regmap mst_d_sclk =
444
+	AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
445
+static struct clk_regmap mst_e_sclk =
446
+	AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
447
+static struct clk_regmap mst_f_sclk =
448
+	AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
449
+
450
+static struct clk_regmap mst_a_lrclk_div =
451
+	AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
452
+static struct clk_regmap mst_b_lrclk_div =
453
+	AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
454
+static struct clk_regmap mst_c_lrclk_div =
455
+	AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
456
+static struct clk_regmap mst_d_lrclk_div =
457
+	AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
458
+static struct clk_regmap mst_e_lrclk_div =
459
+	AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
460
+static struct clk_regmap mst_f_lrclk_div =
461
+	AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
462
+
463
+static struct clk_regmap mst_a_lrclk =
464
+	AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
465
+static struct clk_regmap mst_b_lrclk =
466
+	AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
467
+static struct clk_regmap mst_c_lrclk =
468
+	AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
469
+static struct clk_regmap mst_d_lrclk =
470
+	AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
471
+static struct clk_regmap mst_e_lrclk =
472
+	AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
473
+static struct clk_regmap mst_f_lrclk =
474
+	AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
475
+
476
+static struct clk_regmap tdmin_a_sclk_sel =
477
+	AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
478
+static struct clk_regmap tdmin_b_sclk_sel =
479
+	AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
480
+static struct clk_regmap tdmin_c_sclk_sel =
481
+	AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
482
+static struct clk_regmap tdmin_lb_sclk_sel =
483
+	AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
484
+static struct clk_regmap tdmout_a_sclk_sel =
485
+	AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
486
+static struct clk_regmap tdmout_b_sclk_sel =
487
+	AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
488
+static struct clk_regmap tdmout_c_sclk_sel =
489
+	AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
490
+
491
+static struct clk_regmap tdmin_a_sclk_pre_en =
492
+	AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
493
+static struct clk_regmap tdmin_b_sclk_pre_en =
494
+	AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
495
+static struct clk_regmap tdmin_c_sclk_pre_en =
496
+	AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
497
+static struct clk_regmap tdmin_lb_sclk_pre_en =
498
+	AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
499
+static struct clk_regmap tdmout_a_sclk_pre_en =
500
+	AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
501
+static struct clk_regmap tdmout_b_sclk_pre_en =
502
+	AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
503
+static struct clk_regmap tdmout_c_sclk_pre_en =
504
+	AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
505
+
506
+static struct clk_regmap tdmin_a_sclk_post_en =
507
+	AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
508
+static struct clk_regmap tdmin_b_sclk_post_en =
509
+	AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
510
+static struct clk_regmap tdmin_c_sclk_post_en =
511
+	AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
512
+static struct clk_regmap tdmin_lb_sclk_post_en =
513
+	AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
514
+static struct clk_regmap tdmout_a_sclk_post_en =
515
+	AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
516
+static struct clk_regmap tdmout_b_sclk_post_en =
517
+	AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
518
+static struct clk_regmap tdmout_c_sclk_post_en =
519
+	AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
520
+
521
+static struct clk_regmap tdmin_a_sclk =
522
+	AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
523
+static struct clk_regmap tdmin_b_sclk =
524
+	AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
525
+static struct clk_regmap tdmin_c_sclk =
526
+	AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
527
+static struct clk_regmap tdmin_lb_sclk =
528
+	AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
529
+
530
+static struct clk_regmap tdmin_a_lrclk =
531
+	AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
532
+static struct clk_regmap tdmin_b_lrclk =
533
+	AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
534
+static struct clk_regmap tdmin_c_lrclk =
535
+	AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
536
+static struct clk_regmap tdmin_lb_lrclk =
537
+	AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
538
+static struct clk_regmap tdmout_a_lrclk =
539
+	AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
540
+static struct clk_regmap tdmout_b_lrclk =
541
+	AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
542
+static struct clk_regmap tdmout_c_lrclk =
543
+	AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
544
+
545
+/* AXG Clocks */
546
+static struct clk_regmap axg_tdmout_a_sclk =
547
+	AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
548
+static struct clk_regmap axg_tdmout_b_sclk =
549
+	AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
550
+static struct clk_regmap axg_tdmout_c_sclk =
551
+	AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
552
+
553
+/* AXG/G12A Clocks */
554
+static struct clk_hw axg_aud_top = {
555
+	.init = &(struct clk_init_data) {
556
+		/* Provide aud_top signal name on axg and g12a */
557
+		.name = "aud_top",
558
+		.ops = &(const struct clk_ops) {},
559
+		.parent_data = &(const struct clk_parent_data) {
560
+			.fw_name = "pclk",
561
+		},
562
+		.num_parents = 1,
563
+	},
564
+};
565
+
566
+static struct clk_regmap mst_a_mclk_sel =
567
+	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
568
+static struct clk_regmap mst_b_mclk_sel =
569
+	AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
570
+static struct clk_regmap mst_c_mclk_sel =
571
+	AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
572
+static struct clk_regmap mst_d_mclk_sel =
573
+	AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
574
+static struct clk_regmap mst_e_mclk_sel =
575
+	AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
576
+static struct clk_regmap mst_f_mclk_sel =
577
+	AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
578
+
579
+static struct clk_regmap mst_a_mclk_div =
580
+	AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
581
+static struct clk_regmap mst_b_mclk_div =
582
+	AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
583
+static struct clk_regmap mst_c_mclk_div =
584
+	AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
585
+static struct clk_regmap mst_d_mclk_div =
586
+	AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
587
+static struct clk_regmap mst_e_mclk_div =
588
+	AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
589
+static struct clk_regmap mst_f_mclk_div =
590
+	AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
591
+
592
+static struct clk_regmap mst_a_mclk =
593
+	AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
594
+static struct clk_regmap mst_b_mclk =
595
+	AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
596
+static struct clk_regmap mst_c_mclk =
597
+	AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
598
+static struct clk_regmap mst_d_mclk =
599
+	AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
600
+static struct clk_regmap mst_e_mclk =
601
+	AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
602
+static struct clk_regmap mst_f_mclk =
603
+	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
604
+
605
+/* G12a clocks */
606
+static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
607
+	mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
608
+static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
609
+	mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
610
+static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
611
+	lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
612
+static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
613
+	lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
614
+static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
615
+	lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
616
+static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
617
+	sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
618
+static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
619
+	sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
620
+static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
621
+	sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
622
+
623
+static struct clk_regmap g12a_tdmout_a_sclk =
624
+	AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
625
+static struct clk_regmap g12a_tdmout_b_sclk =
626
+	AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
627
+static struct clk_regmap g12a_tdmout_c_sclk =
628
+	AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
629
+
630
+static struct clk_regmap toram =
631
+	AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20);
632
+static struct clk_regmap spdifout_b =
633
+	AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21);
634
+static struct clk_regmap eqdrc =
635
+	AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22);
636
+
637
+/* SM1 Clocks */
638
+static struct clk_regmap sm1_clk81_en = {
639
+	.data = &(struct clk_regmap_gate_data){
640
+		.offset = AUDIO_CLK81_EN,
641
+		.bit_idx = 31,
642
+	},
643
+	.hw.init = &(struct clk_init_data) {
644
+		.name = "aud_clk81_en",
645
+		.ops = &clk_regmap_gate_ops,
646
+		.parent_data = &(const struct clk_parent_data) {
647
+			.fw_name = "pclk",
648
+		},
649
+		.num_parents = 1,
650
+	},
651
+};
652
+
653
+static struct clk_regmap sm1_sysclk_a_div = {
654
+	.data = &(struct clk_regmap_div_data){
655
+		.offset = AUDIO_CLK81_CTRL,
656
+		.shift = 0,
657
+		.width = 8,
658
+	},
659
+	.hw.init = &(struct clk_init_data) {
660
+		.name = "aud_sysclk_a_div",
661
+		.ops = &clk_regmap_divider_ops,
662
+		.parent_hws = (const struct clk_hw *[]) {
663
+			&sm1_clk81_en.hw,
664
+		},
665
+		.num_parents = 1,
666
+		.flags = CLK_SET_RATE_PARENT,
667
+	},
668
+};
669
+
670
+static struct clk_regmap sm1_sysclk_a_en = {
671
+	.data = &(struct clk_regmap_gate_data){
672
+		.offset = AUDIO_CLK81_CTRL,
673
+		.bit_idx = 8,
674
+	},
675
+	.hw.init = &(struct clk_init_data) {
676
+		.name = "aud_sysclk_a_en",
677
+		.ops = &clk_regmap_gate_ops,
678
+		.parent_hws = (const struct clk_hw *[]) {
679
+			&sm1_sysclk_a_div.hw,
680
+		},
681
+		.num_parents = 1,
682
+		.flags = CLK_SET_RATE_PARENT,
683
+	},
684
+};
685
+
686
+static struct clk_regmap sm1_sysclk_b_div = {
687
+	.data = &(struct clk_regmap_div_data){
688
+		.offset = AUDIO_CLK81_CTRL,
689
+		.shift = 16,
690
+		.width = 8,
691
+	},
692
+	.hw.init = &(struct clk_init_data) {
693
+		.name = "aud_sysclk_b_div",
694
+		.ops = &clk_regmap_divider_ops,
695
+		.parent_hws = (const struct clk_hw *[]) {
696
+			&sm1_clk81_en.hw,
697
+		},
698
+		.num_parents = 1,
699
+		.flags = CLK_SET_RATE_PARENT,
700
+	},
701
+};
702
+
703
+static struct clk_regmap sm1_sysclk_b_en = {
704
+	.data = &(struct clk_regmap_gate_data){
705
+		.offset = AUDIO_CLK81_CTRL,
706
+		.bit_idx = 24,
707
+	},
708
+	.hw.init = &(struct clk_init_data) {
709
+		.name = "aud_sysclk_b_en",
710
+		.ops = &clk_regmap_gate_ops,
711
+		.parent_hws = (const struct clk_hw *[]) {
712
+			&sm1_sysclk_b_div.hw,
713
+		},
714
+		.num_parents = 1,
715
+		.flags = CLK_SET_RATE_PARENT,
716
+	},
717
+};
718
+
719
+static const struct clk_hw *sm1_aud_top_parents[] = {
720
+	&sm1_sysclk_a_en.hw,
721
+	&sm1_sysclk_b_en.hw,
722
+};
723
+
724
+static struct clk_regmap sm1_aud_top = {
725
+	.data = &(struct clk_regmap_mux_data){
726
+		.offset = AUDIO_CLK81_CTRL,
727
+		.mask = 0x1,
728
+		.shift = 31,
729
+	},
730
+	.hw.init = &(struct clk_init_data){
731
+		.name = "aud_top",
732
+		.ops = &clk_regmap_mux_ops,
733
+		.parent_hws = sm1_aud_top_parents,
734
+		.num_parents = ARRAY_SIZE(sm1_aud_top_parents),
735
+		.flags = CLK_SET_RATE_NO_REPARENT,
736
+	},
737
+};
738
+
739
+static struct clk_regmap resample_b =
740
+	AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26);
741
+static struct clk_regmap tovad =
742
+	AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27);
743
+static struct clk_regmap locker =
744
+	AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28);
745
+static struct clk_regmap spdifin_lb =
746
+	AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29);
747
+static struct clk_regmap frddr_d =
748
+	AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0);
749
+static struct clk_regmap toddr_d =
750
+	AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1);
751
+static struct clk_regmap loopback_b =
752
+	AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2);
753
+
754
+static struct clk_regmap sm1_mst_a_mclk_sel =
755
+	AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
756
+static struct clk_regmap sm1_mst_b_mclk_sel =
757
+	AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
758
+static struct clk_regmap sm1_mst_c_mclk_sel =
759
+	AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
760
+static struct clk_regmap sm1_mst_d_mclk_sel =
761
+	AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
762
+static struct clk_regmap sm1_mst_e_mclk_sel =
763
+	AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
764
+static struct clk_regmap sm1_mst_f_mclk_sel =
765
+	AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
766
+
767
+static struct clk_regmap sm1_mst_a_mclk_div =
768
+	AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
769
+static struct clk_regmap sm1_mst_b_mclk_div =
770
+	AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
771
+static struct clk_regmap sm1_mst_c_mclk_div =
772
+	AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
773
+static struct clk_regmap sm1_mst_d_mclk_div =
774
+	AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
775
+static struct clk_regmap sm1_mst_e_mclk_div =
776
+	AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
777
+static struct clk_regmap sm1_mst_f_mclk_div =
778
+	AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
779
+
780
+static struct clk_regmap sm1_mst_a_mclk =
781
+	AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL);
782
+static struct clk_regmap sm1_mst_b_mclk =
783
+	AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL);
784
+static struct clk_regmap sm1_mst_c_mclk =
785
+	AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL);
786
+static struct clk_regmap sm1_mst_d_mclk =
787
+	AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL);
788
+static struct clk_regmap sm1_mst_e_mclk =
789
+	AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL);
790
+static struct clk_regmap sm1_mst_f_mclk =
791
+	AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL);
792
+
793
+static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL(
794
+	tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data);
795
+static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL(
796
+	tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data);
797
+static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL(
798
+	tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data);
799
+static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL(
800
+	tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data);
801
+static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL(
802
+	tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data);
803
+static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL(
804
+	tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data);
805
+static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL(
806
+	tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data);
807
+static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
808
+	tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data);
364809 
365810 /*
366811  * Array of all clocks provided by this provider
....@@ -368,273 +813,867 @@
368813  */
369814 static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
370815 	.hws = {
371
-		[AUD_CLKID_DDR_ARB]		= &axg_ddr_arb.hw,
372
-		[AUD_CLKID_PDM]			= &axg_pdm.hw,
373
-		[AUD_CLKID_TDMIN_A]		= &axg_tdmin_a.hw,
374
-		[AUD_CLKID_TDMIN_B]		= &axg_tdmin_b.hw,
375
-		[AUD_CLKID_TDMIN_C]		= &axg_tdmin_c.hw,
376
-		[AUD_CLKID_TDMIN_LB]		= &axg_tdmin_lb.hw,
377
-		[AUD_CLKID_TDMOUT_A]		= &axg_tdmout_a.hw,
378
-		[AUD_CLKID_TDMOUT_B]		= &axg_tdmout_b.hw,
379
-		[AUD_CLKID_TDMOUT_C]		= &axg_tdmout_c.hw,
380
-		[AUD_CLKID_FRDDR_A]		= &axg_frddr_a.hw,
381
-		[AUD_CLKID_FRDDR_B]		= &axg_frddr_b.hw,
382
-		[AUD_CLKID_FRDDR_C]		= &axg_frddr_c.hw,
383
-		[AUD_CLKID_TODDR_A]		= &axg_toddr_a.hw,
384
-		[AUD_CLKID_TODDR_B]		= &axg_toddr_b.hw,
385
-		[AUD_CLKID_TODDR_C]		= &axg_toddr_c.hw,
386
-		[AUD_CLKID_LOOPBACK]		= &axg_loopback.hw,
387
-		[AUD_CLKID_SPDIFIN]		= &axg_spdifin.hw,
388
-		[AUD_CLKID_SPDIFOUT]		= &axg_spdifout.hw,
389
-		[AUD_CLKID_RESAMPLE]		= &axg_resample.hw,
390
-		[AUD_CLKID_POWER_DETECT]	= &axg_power_detect.hw,
391
-		[AUD_CLKID_MST_A_MCLK_SEL]	= &axg_mst_a_mclk_sel.hw,
392
-		[AUD_CLKID_MST_B_MCLK_SEL]	= &axg_mst_b_mclk_sel.hw,
393
-		[AUD_CLKID_MST_C_MCLK_SEL]	= &axg_mst_c_mclk_sel.hw,
394
-		[AUD_CLKID_MST_D_MCLK_SEL]	= &axg_mst_d_mclk_sel.hw,
395
-		[AUD_CLKID_MST_E_MCLK_SEL]	= &axg_mst_e_mclk_sel.hw,
396
-		[AUD_CLKID_MST_F_MCLK_SEL]	= &axg_mst_f_mclk_sel.hw,
397
-		[AUD_CLKID_MST_A_MCLK_DIV]	= &axg_mst_a_mclk_div.hw,
398
-		[AUD_CLKID_MST_B_MCLK_DIV]	= &axg_mst_b_mclk_div.hw,
399
-		[AUD_CLKID_MST_C_MCLK_DIV]	= &axg_mst_c_mclk_div.hw,
400
-		[AUD_CLKID_MST_D_MCLK_DIV]	= &axg_mst_d_mclk_div.hw,
401
-		[AUD_CLKID_MST_E_MCLK_DIV]	= &axg_mst_e_mclk_div.hw,
402
-		[AUD_CLKID_MST_F_MCLK_DIV]	= &axg_mst_f_mclk_div.hw,
403
-		[AUD_CLKID_MST_A_MCLK]		= &axg_mst_a_mclk.hw,
404
-		[AUD_CLKID_MST_B_MCLK]		= &axg_mst_b_mclk.hw,
405
-		[AUD_CLKID_MST_C_MCLK]		= &axg_mst_c_mclk.hw,
406
-		[AUD_CLKID_MST_D_MCLK]		= &axg_mst_d_mclk.hw,
407
-		[AUD_CLKID_MST_E_MCLK]		= &axg_mst_e_mclk.hw,
408
-		[AUD_CLKID_MST_F_MCLK]		= &axg_mst_f_mclk.hw,
409
-		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &axg_spdifout_clk_sel.hw,
410
-		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &axg_spdifout_clk_div.hw,
411
-		[AUD_CLKID_SPDIFOUT_CLK]	= &axg_spdifout_clk.hw,
412
-		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &axg_spdifin_clk_sel.hw,
413
-		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &axg_spdifin_clk_div.hw,
414
-		[AUD_CLKID_SPDIFIN_CLK]		= &axg_spdifin_clk.hw,
415
-		[AUD_CLKID_PDM_DCLK_SEL]	= &axg_pdm_dclk_sel.hw,
416
-		[AUD_CLKID_PDM_DCLK_DIV]	= &axg_pdm_dclk_div.hw,
417
-		[AUD_CLKID_PDM_DCLK]		= &axg_pdm_dclk.hw,
418
-		[AUD_CLKID_PDM_SYSCLK_SEL]	= &axg_pdm_sysclk_sel.hw,
419
-		[AUD_CLKID_PDM_SYSCLK_DIV]	= &axg_pdm_sysclk_div.hw,
420
-		[AUD_CLKID_PDM_SYSCLK]		= &axg_pdm_sysclk.hw,
421
-		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &axg_mst_a_sclk_pre_en.hw,
422
-		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &axg_mst_b_sclk_pre_en.hw,
423
-		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &axg_mst_c_sclk_pre_en.hw,
424
-		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &axg_mst_d_sclk_pre_en.hw,
425
-		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &axg_mst_e_sclk_pre_en.hw,
426
-		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &axg_mst_f_sclk_pre_en.hw,
427
-		[AUD_CLKID_MST_A_SCLK_DIV]	= &axg_mst_a_sclk_div.hw,
428
-		[AUD_CLKID_MST_B_SCLK_DIV]	= &axg_mst_b_sclk_div.hw,
429
-		[AUD_CLKID_MST_C_SCLK_DIV]	= &axg_mst_c_sclk_div.hw,
430
-		[AUD_CLKID_MST_D_SCLK_DIV]	= &axg_mst_d_sclk_div.hw,
431
-		[AUD_CLKID_MST_E_SCLK_DIV]	= &axg_mst_e_sclk_div.hw,
432
-		[AUD_CLKID_MST_F_SCLK_DIV]	= &axg_mst_f_sclk_div.hw,
433
-		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &axg_mst_a_sclk_post_en.hw,
434
-		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &axg_mst_b_sclk_post_en.hw,
435
-		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &axg_mst_c_sclk_post_en.hw,
436
-		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &axg_mst_d_sclk_post_en.hw,
437
-		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &axg_mst_e_sclk_post_en.hw,
438
-		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &axg_mst_f_sclk_post_en.hw,
439
-		[AUD_CLKID_MST_A_SCLK]		= &axg_mst_a_sclk.hw,
440
-		[AUD_CLKID_MST_B_SCLK]		= &axg_mst_b_sclk.hw,
441
-		[AUD_CLKID_MST_C_SCLK]		= &axg_mst_c_sclk.hw,
442
-		[AUD_CLKID_MST_D_SCLK]		= &axg_mst_d_sclk.hw,
443
-		[AUD_CLKID_MST_E_SCLK]		= &axg_mst_e_sclk.hw,
444
-		[AUD_CLKID_MST_F_SCLK]		= &axg_mst_f_sclk.hw,
445
-		[AUD_CLKID_MST_A_LRCLK_DIV]	= &axg_mst_a_lrclk_div.hw,
446
-		[AUD_CLKID_MST_B_LRCLK_DIV]	= &axg_mst_b_lrclk_div.hw,
447
-		[AUD_CLKID_MST_C_LRCLK_DIV]	= &axg_mst_c_lrclk_div.hw,
448
-		[AUD_CLKID_MST_D_LRCLK_DIV]	= &axg_mst_d_lrclk_div.hw,
449
-		[AUD_CLKID_MST_E_LRCLK_DIV]	= &axg_mst_e_lrclk_div.hw,
450
-		[AUD_CLKID_MST_F_LRCLK_DIV]	= &axg_mst_f_lrclk_div.hw,
451
-		[AUD_CLKID_MST_A_LRCLK]		= &axg_mst_a_lrclk.hw,
452
-		[AUD_CLKID_MST_B_LRCLK]		= &axg_mst_b_lrclk.hw,
453
-		[AUD_CLKID_MST_C_LRCLK]		= &axg_mst_c_lrclk.hw,
454
-		[AUD_CLKID_MST_D_LRCLK]		= &axg_mst_d_lrclk.hw,
455
-		[AUD_CLKID_MST_E_LRCLK]		= &axg_mst_e_lrclk.hw,
456
-		[AUD_CLKID_MST_F_LRCLK]		= &axg_mst_f_lrclk.hw,
457
-		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &axg_tdmin_a_sclk_sel.hw,
458
-		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &axg_tdmin_b_sclk_sel.hw,
459
-		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &axg_tdmin_c_sclk_sel.hw,
460
-		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &axg_tdmin_lb_sclk_sel.hw,
461
-		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &axg_tdmout_a_sclk_sel.hw,
462
-		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &axg_tdmout_b_sclk_sel.hw,
463
-		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &axg_tdmout_c_sclk_sel.hw,
464
-		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &axg_tdmin_a_sclk_pre_en.hw,
465
-		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &axg_tdmin_b_sclk_pre_en.hw,
466
-		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &axg_tdmin_c_sclk_pre_en.hw,
467
-		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &axg_tdmin_lb_sclk_pre_en.hw,
468
-		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &axg_tdmout_a_sclk_pre_en.hw,
469
-		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &axg_tdmout_b_sclk_pre_en.hw,
470
-		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &axg_tdmout_c_sclk_pre_en.hw,
471
-		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &axg_tdmin_a_sclk_post_en.hw,
472
-		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &axg_tdmin_b_sclk_post_en.hw,
473
-		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &axg_tdmin_c_sclk_post_en.hw,
474
-		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &axg_tdmin_lb_sclk_post_en.hw,
475
-		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &axg_tdmout_a_sclk_post_en.hw,
476
-		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &axg_tdmout_b_sclk_post_en.hw,
477
-		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &axg_tdmout_c_sclk_post_en.hw,
478
-		[AUD_CLKID_TDMIN_A_SCLK]	= &axg_tdmin_a_sclk.hw,
479
-		[AUD_CLKID_TDMIN_B_SCLK]	= &axg_tdmin_b_sclk.hw,
480
-		[AUD_CLKID_TDMIN_C_SCLK]	= &axg_tdmin_c_sclk.hw,
481
-		[AUD_CLKID_TDMIN_LB_SCLK]	= &axg_tdmin_lb_sclk.hw,
816
+		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
817
+		[AUD_CLKID_PDM]			= &pdm.hw,
818
+		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
819
+		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
820
+		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
821
+		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
822
+		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
823
+		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
824
+		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
825
+		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
826
+		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
827
+		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
828
+		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
829
+		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
830
+		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
831
+		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
832
+		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
833
+		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
834
+		[AUD_CLKID_RESAMPLE]		= &resample.hw,
835
+		[AUD_CLKID_POWER_DETECT]	= &power_detect.hw,
836
+		[AUD_CLKID_MST_A_MCLK_SEL]	= &mst_a_mclk_sel.hw,
837
+		[AUD_CLKID_MST_B_MCLK_SEL]	= &mst_b_mclk_sel.hw,
838
+		[AUD_CLKID_MST_C_MCLK_SEL]	= &mst_c_mclk_sel.hw,
839
+		[AUD_CLKID_MST_D_MCLK_SEL]	= &mst_d_mclk_sel.hw,
840
+		[AUD_CLKID_MST_E_MCLK_SEL]	= &mst_e_mclk_sel.hw,
841
+		[AUD_CLKID_MST_F_MCLK_SEL]	= &mst_f_mclk_sel.hw,
842
+		[AUD_CLKID_MST_A_MCLK_DIV]	= &mst_a_mclk_div.hw,
843
+		[AUD_CLKID_MST_B_MCLK_DIV]	= &mst_b_mclk_div.hw,
844
+		[AUD_CLKID_MST_C_MCLK_DIV]	= &mst_c_mclk_div.hw,
845
+		[AUD_CLKID_MST_D_MCLK_DIV]	= &mst_d_mclk_div.hw,
846
+		[AUD_CLKID_MST_E_MCLK_DIV]	= &mst_e_mclk_div.hw,
847
+		[AUD_CLKID_MST_F_MCLK_DIV]	= &mst_f_mclk_div.hw,
848
+		[AUD_CLKID_MST_A_MCLK]		= &mst_a_mclk.hw,
849
+		[AUD_CLKID_MST_B_MCLK]		= &mst_b_mclk.hw,
850
+		[AUD_CLKID_MST_C_MCLK]		= &mst_c_mclk.hw,
851
+		[AUD_CLKID_MST_D_MCLK]		= &mst_d_mclk.hw,
852
+		[AUD_CLKID_MST_E_MCLK]		= &mst_e_mclk.hw,
853
+		[AUD_CLKID_MST_F_MCLK]		= &mst_f_mclk.hw,
854
+		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
855
+		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
856
+		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
857
+		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
858
+		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
859
+		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
860
+		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
861
+		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
862
+		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
863
+		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
864
+		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
865
+		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
866
+		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
867
+		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
868
+		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
869
+		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
870
+		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
871
+		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
872
+		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
873
+		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
874
+		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
875
+		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
876
+		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
877
+		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
878
+		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
879
+		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
880
+		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
881
+		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
882
+		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
883
+		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
884
+		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
885
+		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
886
+		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
887
+		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
888
+		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
889
+		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
890
+		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
891
+		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
892
+		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
893
+		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
894
+		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
895
+		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
896
+		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
897
+		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
898
+		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
899
+		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
900
+		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
901
+		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
902
+		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
903
+		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
904
+		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
905
+		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
906
+		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
907
+		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
908
+		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
909
+		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
910
+		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
911
+		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
912
+		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
913
+		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
914
+		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
915
+		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
916
+		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
917
+		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
918
+		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
919
+		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
920
+		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
921
+		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
922
+		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
923
+		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
924
+		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
925
+		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
926
+		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
482927 		[AUD_CLKID_TDMOUT_A_SCLK]	= &axg_tdmout_a_sclk.hw,
483928 		[AUD_CLKID_TDMOUT_B_SCLK]	= &axg_tdmout_b_sclk.hw,
484929 		[AUD_CLKID_TDMOUT_C_SCLK]	= &axg_tdmout_c_sclk.hw,
485
-		[AUD_CLKID_TDMIN_A_LRCLK]	= &axg_tdmin_a_lrclk.hw,
486
-		[AUD_CLKID_TDMIN_B_LRCLK]	= &axg_tdmin_b_lrclk.hw,
487
-		[AUD_CLKID_TDMIN_C_LRCLK]	= &axg_tdmin_c_lrclk.hw,
488
-		[AUD_CLKID_TDMIN_LB_LRCLK]	= &axg_tdmin_lb_lrclk.hw,
489
-		[AUD_CLKID_TDMOUT_A_LRCLK]	= &axg_tdmout_a_lrclk.hw,
490
-		[AUD_CLKID_TDMOUT_B_LRCLK]	= &axg_tdmout_b_lrclk.hw,
491
-		[AUD_CLKID_TDMOUT_C_LRCLK]	= &axg_tdmout_c_lrclk.hw,
930
+		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
931
+		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
932
+		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
933
+		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
934
+		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
935
+		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
936
+		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
937
+		[AUD_CLKID_TOP]			= &axg_aud_top,
492938 		[NR_CLKS] = NULL,
493939 	},
494940 	.num = NR_CLKS,
495941 };
496942 
497
-/* Convenience table to populate regmap in .probe() */
498
-static struct clk_regmap *const axg_audio_clk_regmaps[] = {
499
-	&axg_ddr_arb,
500
-	&axg_pdm,
501
-	&axg_tdmin_a,
502
-	&axg_tdmin_b,
503
-	&axg_tdmin_c,
504
-	&axg_tdmin_lb,
505
-	&axg_tdmout_a,
506
-	&axg_tdmout_b,
507
-	&axg_tdmout_c,
508
-	&axg_frddr_a,
509
-	&axg_frddr_b,
510
-	&axg_frddr_c,
511
-	&axg_toddr_a,
512
-	&axg_toddr_b,
513
-	&axg_toddr_c,
514
-	&axg_loopback,
515
-	&axg_spdifin,
516
-	&axg_spdifout,
517
-	&axg_resample,
518
-	&axg_power_detect,
519
-	&axg_mst_a_mclk_sel,
520
-	&axg_mst_b_mclk_sel,
521
-	&axg_mst_c_mclk_sel,
522
-	&axg_mst_d_mclk_sel,
523
-	&axg_mst_e_mclk_sel,
524
-	&axg_mst_f_mclk_sel,
525
-	&axg_mst_a_mclk_div,
526
-	&axg_mst_b_mclk_div,
527
-	&axg_mst_c_mclk_div,
528
-	&axg_mst_d_mclk_div,
529
-	&axg_mst_e_mclk_div,
530
-	&axg_mst_f_mclk_div,
531
-	&axg_mst_a_mclk,
532
-	&axg_mst_b_mclk,
533
-	&axg_mst_c_mclk,
534
-	&axg_mst_d_mclk,
535
-	&axg_mst_e_mclk,
536
-	&axg_mst_f_mclk,
537
-	&axg_spdifout_clk_sel,
538
-	&axg_spdifout_clk_div,
539
-	&axg_spdifout_clk,
540
-	&axg_spdifin_clk_sel,
541
-	&axg_spdifin_clk_div,
542
-	&axg_spdifin_clk,
543
-	&axg_pdm_dclk_sel,
544
-	&axg_pdm_dclk_div,
545
-	&axg_pdm_dclk,
546
-	&axg_pdm_sysclk_sel,
547
-	&axg_pdm_sysclk_div,
548
-	&axg_pdm_sysclk,
549
-	&axg_mst_a_sclk_pre_en,
550
-	&axg_mst_b_sclk_pre_en,
551
-	&axg_mst_c_sclk_pre_en,
552
-	&axg_mst_d_sclk_pre_en,
553
-	&axg_mst_e_sclk_pre_en,
554
-	&axg_mst_f_sclk_pre_en,
555
-	&axg_mst_a_sclk_div,
556
-	&axg_mst_b_sclk_div,
557
-	&axg_mst_c_sclk_div,
558
-	&axg_mst_d_sclk_div,
559
-	&axg_mst_e_sclk_div,
560
-	&axg_mst_f_sclk_div,
561
-	&axg_mst_a_sclk_post_en,
562
-	&axg_mst_b_sclk_post_en,
563
-	&axg_mst_c_sclk_post_en,
564
-	&axg_mst_d_sclk_post_en,
565
-	&axg_mst_e_sclk_post_en,
566
-	&axg_mst_f_sclk_post_en,
567
-	&axg_mst_a_sclk,
568
-	&axg_mst_b_sclk,
569
-	&axg_mst_c_sclk,
570
-	&axg_mst_d_sclk,
571
-	&axg_mst_e_sclk,
572
-	&axg_mst_f_sclk,
573
-	&axg_mst_a_lrclk_div,
574
-	&axg_mst_b_lrclk_div,
575
-	&axg_mst_c_lrclk_div,
576
-	&axg_mst_d_lrclk_div,
577
-	&axg_mst_e_lrclk_div,
578
-	&axg_mst_f_lrclk_div,
579
-	&axg_mst_a_lrclk,
580
-	&axg_mst_b_lrclk,
581
-	&axg_mst_c_lrclk,
582
-	&axg_mst_d_lrclk,
583
-	&axg_mst_e_lrclk,
584
-	&axg_mst_f_lrclk,
585
-	&axg_tdmin_a_sclk_sel,
586
-	&axg_tdmin_b_sclk_sel,
587
-	&axg_tdmin_c_sclk_sel,
588
-	&axg_tdmin_lb_sclk_sel,
589
-	&axg_tdmout_a_sclk_sel,
590
-	&axg_tdmout_b_sclk_sel,
591
-	&axg_tdmout_c_sclk_sel,
592
-	&axg_tdmin_a_sclk_pre_en,
593
-	&axg_tdmin_b_sclk_pre_en,
594
-	&axg_tdmin_c_sclk_pre_en,
595
-	&axg_tdmin_lb_sclk_pre_en,
596
-	&axg_tdmout_a_sclk_pre_en,
597
-	&axg_tdmout_b_sclk_pre_en,
598
-	&axg_tdmout_c_sclk_pre_en,
599
-	&axg_tdmin_a_sclk_post_en,
600
-	&axg_tdmin_b_sclk_post_en,
601
-	&axg_tdmin_c_sclk_post_en,
602
-	&axg_tdmin_lb_sclk_post_en,
603
-	&axg_tdmout_a_sclk_post_en,
604
-	&axg_tdmout_b_sclk_post_en,
605
-	&axg_tdmout_c_sclk_post_en,
606
-	&axg_tdmin_a_sclk,
607
-	&axg_tdmin_b_sclk,
608
-	&axg_tdmin_c_sclk,
609
-	&axg_tdmin_lb_sclk,
943
+/*
944
+ * Array of all G12A clocks provided by this provider
945
+ * The input clocks of the controller will be populated at runtime
946
+ */
947
+static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
948
+	.hws = {
949
+		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
950
+		[AUD_CLKID_PDM]			= &pdm.hw,
951
+		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
952
+		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
953
+		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
954
+		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
955
+		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
956
+		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
957
+		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
958
+		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
959
+		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
960
+		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
961
+		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
962
+		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
963
+		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
964
+		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
965
+		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
966
+		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
967
+		[AUD_CLKID_RESAMPLE]		= &resample.hw,
968
+		[AUD_CLKID_POWER_DETECT]	= &power_detect.hw,
969
+		[AUD_CLKID_SPDIFOUT_B]		= &spdifout_b.hw,
970
+		[AUD_CLKID_MST_A_MCLK_SEL]	= &mst_a_mclk_sel.hw,
971
+		[AUD_CLKID_MST_B_MCLK_SEL]	= &mst_b_mclk_sel.hw,
972
+		[AUD_CLKID_MST_C_MCLK_SEL]	= &mst_c_mclk_sel.hw,
973
+		[AUD_CLKID_MST_D_MCLK_SEL]	= &mst_d_mclk_sel.hw,
974
+		[AUD_CLKID_MST_E_MCLK_SEL]	= &mst_e_mclk_sel.hw,
975
+		[AUD_CLKID_MST_F_MCLK_SEL]	= &mst_f_mclk_sel.hw,
976
+		[AUD_CLKID_MST_A_MCLK_DIV]	= &mst_a_mclk_div.hw,
977
+		[AUD_CLKID_MST_B_MCLK_DIV]	= &mst_b_mclk_div.hw,
978
+		[AUD_CLKID_MST_C_MCLK_DIV]	= &mst_c_mclk_div.hw,
979
+		[AUD_CLKID_MST_D_MCLK_DIV]	= &mst_d_mclk_div.hw,
980
+		[AUD_CLKID_MST_E_MCLK_DIV]	= &mst_e_mclk_div.hw,
981
+		[AUD_CLKID_MST_F_MCLK_DIV]	= &mst_f_mclk_div.hw,
982
+		[AUD_CLKID_MST_A_MCLK]		= &mst_a_mclk.hw,
983
+		[AUD_CLKID_MST_B_MCLK]		= &mst_b_mclk.hw,
984
+		[AUD_CLKID_MST_C_MCLK]		= &mst_c_mclk.hw,
985
+		[AUD_CLKID_MST_D_MCLK]		= &mst_d_mclk.hw,
986
+		[AUD_CLKID_MST_E_MCLK]		= &mst_e_mclk.hw,
987
+		[AUD_CLKID_MST_F_MCLK]		= &mst_f_mclk.hw,
988
+		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
989
+		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
990
+		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
991
+		[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &spdifout_b_clk_sel.hw,
992
+		[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &spdifout_b_clk_div.hw,
993
+		[AUD_CLKID_SPDIFOUT_B_CLK]	= &spdifout_b_clk.hw,
994
+		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
995
+		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
996
+		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
997
+		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
998
+		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
999
+		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
1000
+		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
1001
+		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
1002
+		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
1003
+		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
1004
+		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
1005
+		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
1006
+		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
1007
+		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
1008
+		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
1009
+		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
1010
+		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
1011
+		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
1012
+		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
1013
+		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
1014
+		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
1015
+		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
1016
+		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
1017
+		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
1018
+		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
1019
+		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
1020
+		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
1021
+		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
1022
+		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
1023
+		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
1024
+		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
1025
+		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
1026
+		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
1027
+		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
1028
+		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
1029
+		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
1030
+		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
1031
+		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
1032
+		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
1033
+		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
1034
+		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
1035
+		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
1036
+		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
1037
+		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
1038
+		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
1039
+		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
1040
+		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
1041
+		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
1042
+		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
1043
+		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
1044
+		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
1045
+		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
1046
+		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
1047
+		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
1048
+		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
1049
+		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1050
+		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1051
+		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1052
+		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1053
+		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1054
+		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1055
+		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1056
+		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1057
+		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1058
+		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1059
+		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1060
+		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
1061
+		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
1062
+		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
1063
+		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
1064
+		[AUD_CLKID_TDMOUT_A_SCLK]	= &g12a_tdmout_a_sclk.hw,
1065
+		[AUD_CLKID_TDMOUT_B_SCLK]	= &g12a_tdmout_b_sclk.hw,
1066
+		[AUD_CLKID_TDMOUT_C_SCLK]	= &g12a_tdmout_c_sclk.hw,
1067
+		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
1068
+		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
1069
+		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
1070
+		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
1071
+		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
1072
+		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
1073
+		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
1074
+		[AUD_CLKID_TDM_MCLK_PAD0]	= &g12a_tdm_mclk_pad_0.hw,
1075
+		[AUD_CLKID_TDM_MCLK_PAD1]	= &g12a_tdm_mclk_pad_1.hw,
1076
+		[AUD_CLKID_TDM_LRCLK_PAD0]	= &g12a_tdm_lrclk_pad_0.hw,
1077
+		[AUD_CLKID_TDM_LRCLK_PAD1]	= &g12a_tdm_lrclk_pad_1.hw,
1078
+		[AUD_CLKID_TDM_LRCLK_PAD2]	= &g12a_tdm_lrclk_pad_2.hw,
1079
+		[AUD_CLKID_TDM_SCLK_PAD0]	= &g12a_tdm_sclk_pad_0.hw,
1080
+		[AUD_CLKID_TDM_SCLK_PAD1]	= &g12a_tdm_sclk_pad_1.hw,
1081
+		[AUD_CLKID_TDM_SCLK_PAD2]	= &g12a_tdm_sclk_pad_2.hw,
1082
+		[AUD_CLKID_TOP]			= &axg_aud_top,
1083
+		[NR_CLKS] = NULL,
1084
+	},
1085
+	.num = NR_CLKS,
1086
+};
1087
+
1088
+/*
1089
+ * Array of all SM1 clocks provided by this provider
1090
+ * The input clocks of the controller will be populated at runtime
1091
+ */
1092
+static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
1093
+	.hws = {
1094
+		[AUD_CLKID_DDR_ARB]		= &ddr_arb.hw,
1095
+		[AUD_CLKID_PDM]			= &pdm.hw,
1096
+		[AUD_CLKID_TDMIN_A]		= &tdmin_a.hw,
1097
+		[AUD_CLKID_TDMIN_B]		= &tdmin_b.hw,
1098
+		[AUD_CLKID_TDMIN_C]		= &tdmin_c.hw,
1099
+		[AUD_CLKID_TDMIN_LB]		= &tdmin_lb.hw,
1100
+		[AUD_CLKID_TDMOUT_A]		= &tdmout_a.hw,
1101
+		[AUD_CLKID_TDMOUT_B]		= &tdmout_b.hw,
1102
+		[AUD_CLKID_TDMOUT_C]		= &tdmout_c.hw,
1103
+		[AUD_CLKID_FRDDR_A]		= &frddr_a.hw,
1104
+		[AUD_CLKID_FRDDR_B]		= &frddr_b.hw,
1105
+		[AUD_CLKID_FRDDR_C]		= &frddr_c.hw,
1106
+		[AUD_CLKID_TODDR_A]		= &toddr_a.hw,
1107
+		[AUD_CLKID_TODDR_B]		= &toddr_b.hw,
1108
+		[AUD_CLKID_TODDR_C]		= &toddr_c.hw,
1109
+		[AUD_CLKID_LOOPBACK]		= &loopback.hw,
1110
+		[AUD_CLKID_SPDIFIN]		= &spdifin.hw,
1111
+		[AUD_CLKID_SPDIFOUT]		= &spdifout.hw,
1112
+		[AUD_CLKID_RESAMPLE]		= &resample.hw,
1113
+		[AUD_CLKID_SPDIFOUT_B]		= &spdifout_b.hw,
1114
+		[AUD_CLKID_MST_A_MCLK_SEL]	= &sm1_mst_a_mclk_sel.hw,
1115
+		[AUD_CLKID_MST_B_MCLK_SEL]	= &sm1_mst_b_mclk_sel.hw,
1116
+		[AUD_CLKID_MST_C_MCLK_SEL]	= &sm1_mst_c_mclk_sel.hw,
1117
+		[AUD_CLKID_MST_D_MCLK_SEL]	= &sm1_mst_d_mclk_sel.hw,
1118
+		[AUD_CLKID_MST_E_MCLK_SEL]	= &sm1_mst_e_mclk_sel.hw,
1119
+		[AUD_CLKID_MST_F_MCLK_SEL]	= &sm1_mst_f_mclk_sel.hw,
1120
+		[AUD_CLKID_MST_A_MCLK_DIV]	= &sm1_mst_a_mclk_div.hw,
1121
+		[AUD_CLKID_MST_B_MCLK_DIV]	= &sm1_mst_b_mclk_div.hw,
1122
+		[AUD_CLKID_MST_C_MCLK_DIV]	= &sm1_mst_c_mclk_div.hw,
1123
+		[AUD_CLKID_MST_D_MCLK_DIV]	= &sm1_mst_d_mclk_div.hw,
1124
+		[AUD_CLKID_MST_E_MCLK_DIV]	= &sm1_mst_e_mclk_div.hw,
1125
+		[AUD_CLKID_MST_F_MCLK_DIV]	= &sm1_mst_f_mclk_div.hw,
1126
+		[AUD_CLKID_MST_A_MCLK]		= &sm1_mst_a_mclk.hw,
1127
+		[AUD_CLKID_MST_B_MCLK]		= &sm1_mst_b_mclk.hw,
1128
+		[AUD_CLKID_MST_C_MCLK]		= &sm1_mst_c_mclk.hw,
1129
+		[AUD_CLKID_MST_D_MCLK]		= &sm1_mst_d_mclk.hw,
1130
+		[AUD_CLKID_MST_E_MCLK]		= &sm1_mst_e_mclk.hw,
1131
+		[AUD_CLKID_MST_F_MCLK]		= &sm1_mst_f_mclk.hw,
1132
+		[AUD_CLKID_SPDIFOUT_CLK_SEL]	= &spdifout_clk_sel.hw,
1133
+		[AUD_CLKID_SPDIFOUT_CLK_DIV]	= &spdifout_clk_div.hw,
1134
+		[AUD_CLKID_SPDIFOUT_CLK]	= &spdifout_clk.hw,
1135
+		[AUD_CLKID_SPDIFOUT_B_CLK_SEL]	= &spdifout_b_clk_sel.hw,
1136
+		[AUD_CLKID_SPDIFOUT_B_CLK_DIV]	= &spdifout_b_clk_div.hw,
1137
+		[AUD_CLKID_SPDIFOUT_B_CLK]	= &spdifout_b_clk.hw,
1138
+		[AUD_CLKID_SPDIFIN_CLK_SEL]	= &spdifin_clk_sel.hw,
1139
+		[AUD_CLKID_SPDIFIN_CLK_DIV]	= &spdifin_clk_div.hw,
1140
+		[AUD_CLKID_SPDIFIN_CLK]		= &spdifin_clk.hw,
1141
+		[AUD_CLKID_PDM_DCLK_SEL]	= &pdm_dclk_sel.hw,
1142
+		[AUD_CLKID_PDM_DCLK_DIV]	= &pdm_dclk_div.hw,
1143
+		[AUD_CLKID_PDM_DCLK]		= &pdm_dclk.hw,
1144
+		[AUD_CLKID_PDM_SYSCLK_SEL]	= &pdm_sysclk_sel.hw,
1145
+		[AUD_CLKID_PDM_SYSCLK_DIV]	= &pdm_sysclk_div.hw,
1146
+		[AUD_CLKID_PDM_SYSCLK]		= &pdm_sysclk.hw,
1147
+		[AUD_CLKID_MST_A_SCLK_PRE_EN]	= &mst_a_sclk_pre_en.hw,
1148
+		[AUD_CLKID_MST_B_SCLK_PRE_EN]	= &mst_b_sclk_pre_en.hw,
1149
+		[AUD_CLKID_MST_C_SCLK_PRE_EN]	= &mst_c_sclk_pre_en.hw,
1150
+		[AUD_CLKID_MST_D_SCLK_PRE_EN]	= &mst_d_sclk_pre_en.hw,
1151
+		[AUD_CLKID_MST_E_SCLK_PRE_EN]	= &mst_e_sclk_pre_en.hw,
1152
+		[AUD_CLKID_MST_F_SCLK_PRE_EN]	= &mst_f_sclk_pre_en.hw,
1153
+		[AUD_CLKID_MST_A_SCLK_DIV]	= &mst_a_sclk_div.hw,
1154
+		[AUD_CLKID_MST_B_SCLK_DIV]	= &mst_b_sclk_div.hw,
1155
+		[AUD_CLKID_MST_C_SCLK_DIV]	= &mst_c_sclk_div.hw,
1156
+		[AUD_CLKID_MST_D_SCLK_DIV]	= &mst_d_sclk_div.hw,
1157
+		[AUD_CLKID_MST_E_SCLK_DIV]	= &mst_e_sclk_div.hw,
1158
+		[AUD_CLKID_MST_F_SCLK_DIV]	= &mst_f_sclk_div.hw,
1159
+		[AUD_CLKID_MST_A_SCLK_POST_EN]	= &mst_a_sclk_post_en.hw,
1160
+		[AUD_CLKID_MST_B_SCLK_POST_EN]	= &mst_b_sclk_post_en.hw,
1161
+		[AUD_CLKID_MST_C_SCLK_POST_EN]	= &mst_c_sclk_post_en.hw,
1162
+		[AUD_CLKID_MST_D_SCLK_POST_EN]	= &mst_d_sclk_post_en.hw,
1163
+		[AUD_CLKID_MST_E_SCLK_POST_EN]	= &mst_e_sclk_post_en.hw,
1164
+		[AUD_CLKID_MST_F_SCLK_POST_EN]	= &mst_f_sclk_post_en.hw,
1165
+		[AUD_CLKID_MST_A_SCLK]		= &mst_a_sclk.hw,
1166
+		[AUD_CLKID_MST_B_SCLK]		= &mst_b_sclk.hw,
1167
+		[AUD_CLKID_MST_C_SCLK]		= &mst_c_sclk.hw,
1168
+		[AUD_CLKID_MST_D_SCLK]		= &mst_d_sclk.hw,
1169
+		[AUD_CLKID_MST_E_SCLK]		= &mst_e_sclk.hw,
1170
+		[AUD_CLKID_MST_F_SCLK]		= &mst_f_sclk.hw,
1171
+		[AUD_CLKID_MST_A_LRCLK_DIV]	= &mst_a_lrclk_div.hw,
1172
+		[AUD_CLKID_MST_B_LRCLK_DIV]	= &mst_b_lrclk_div.hw,
1173
+		[AUD_CLKID_MST_C_LRCLK_DIV]	= &mst_c_lrclk_div.hw,
1174
+		[AUD_CLKID_MST_D_LRCLK_DIV]	= &mst_d_lrclk_div.hw,
1175
+		[AUD_CLKID_MST_E_LRCLK_DIV]	= &mst_e_lrclk_div.hw,
1176
+		[AUD_CLKID_MST_F_LRCLK_DIV]	= &mst_f_lrclk_div.hw,
1177
+		[AUD_CLKID_MST_A_LRCLK]		= &mst_a_lrclk.hw,
1178
+		[AUD_CLKID_MST_B_LRCLK]		= &mst_b_lrclk.hw,
1179
+		[AUD_CLKID_MST_C_LRCLK]		= &mst_c_lrclk.hw,
1180
+		[AUD_CLKID_MST_D_LRCLK]		= &mst_d_lrclk.hw,
1181
+		[AUD_CLKID_MST_E_LRCLK]		= &mst_e_lrclk.hw,
1182
+		[AUD_CLKID_MST_F_LRCLK]		= &mst_f_lrclk.hw,
1183
+		[AUD_CLKID_TDMIN_A_SCLK_SEL]	= &tdmin_a_sclk_sel.hw,
1184
+		[AUD_CLKID_TDMIN_B_SCLK_SEL]	= &tdmin_b_sclk_sel.hw,
1185
+		[AUD_CLKID_TDMIN_C_SCLK_SEL]	= &tdmin_c_sclk_sel.hw,
1186
+		[AUD_CLKID_TDMIN_LB_SCLK_SEL]	= &tdmin_lb_sclk_sel.hw,
1187
+		[AUD_CLKID_TDMOUT_A_SCLK_SEL]	= &tdmout_a_sclk_sel.hw,
1188
+		[AUD_CLKID_TDMOUT_B_SCLK_SEL]	= &tdmout_b_sclk_sel.hw,
1189
+		[AUD_CLKID_TDMOUT_C_SCLK_SEL]	= &tdmout_c_sclk_sel.hw,
1190
+		[AUD_CLKID_TDMIN_A_SCLK_PRE_EN]	= &tdmin_a_sclk_pre_en.hw,
1191
+		[AUD_CLKID_TDMIN_B_SCLK_PRE_EN]	= &tdmin_b_sclk_pre_en.hw,
1192
+		[AUD_CLKID_TDMIN_C_SCLK_PRE_EN]	= &tdmin_c_sclk_pre_en.hw,
1193
+		[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1194
+		[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1195
+		[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1196
+		[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1197
+		[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1198
+		[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1199
+		[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1200
+		[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1201
+		[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1202
+		[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1203
+		[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1204
+		[AUD_CLKID_TDMIN_A_SCLK]	= &tdmin_a_sclk.hw,
1205
+		[AUD_CLKID_TDMIN_B_SCLK]	= &tdmin_b_sclk.hw,
1206
+		[AUD_CLKID_TDMIN_C_SCLK]	= &tdmin_c_sclk.hw,
1207
+		[AUD_CLKID_TDMIN_LB_SCLK]	= &tdmin_lb_sclk.hw,
1208
+		[AUD_CLKID_TDMOUT_A_SCLK]	= &g12a_tdmout_a_sclk.hw,
1209
+		[AUD_CLKID_TDMOUT_B_SCLK]	= &g12a_tdmout_b_sclk.hw,
1210
+		[AUD_CLKID_TDMOUT_C_SCLK]	= &g12a_tdmout_c_sclk.hw,
1211
+		[AUD_CLKID_TDMIN_A_LRCLK]	= &tdmin_a_lrclk.hw,
1212
+		[AUD_CLKID_TDMIN_B_LRCLK]	= &tdmin_b_lrclk.hw,
1213
+		[AUD_CLKID_TDMIN_C_LRCLK]	= &tdmin_c_lrclk.hw,
1214
+		[AUD_CLKID_TDMIN_LB_LRCLK]	= &tdmin_lb_lrclk.hw,
1215
+		[AUD_CLKID_TDMOUT_A_LRCLK]	= &tdmout_a_lrclk.hw,
1216
+		[AUD_CLKID_TDMOUT_B_LRCLK]	= &tdmout_b_lrclk.hw,
1217
+		[AUD_CLKID_TDMOUT_C_LRCLK]	= &tdmout_c_lrclk.hw,
1218
+		[AUD_CLKID_TDM_MCLK_PAD0]	= &sm1_tdm_mclk_pad_0.hw,
1219
+		[AUD_CLKID_TDM_MCLK_PAD1]	= &sm1_tdm_mclk_pad_1.hw,
1220
+		[AUD_CLKID_TDM_LRCLK_PAD0]	= &sm1_tdm_lrclk_pad_0.hw,
1221
+		[AUD_CLKID_TDM_LRCLK_PAD1]	= &sm1_tdm_lrclk_pad_1.hw,
1222
+		[AUD_CLKID_TDM_LRCLK_PAD2]	= &sm1_tdm_lrclk_pad_2.hw,
1223
+		[AUD_CLKID_TDM_SCLK_PAD0]	= &sm1_tdm_sclk_pad_0.hw,
1224
+		[AUD_CLKID_TDM_SCLK_PAD1]	= &sm1_tdm_sclk_pad_1.hw,
1225
+		[AUD_CLKID_TDM_SCLK_PAD2]	= &sm1_tdm_sclk_pad_2.hw,
1226
+		[AUD_CLKID_TOP]			= &sm1_aud_top.hw,
1227
+		[AUD_CLKID_TORAM]		= &toram.hw,
1228
+		[AUD_CLKID_EQDRC]		= &eqdrc.hw,
1229
+		[AUD_CLKID_RESAMPLE_B]		= &resample_b.hw,
1230
+		[AUD_CLKID_TOVAD]		= &tovad.hw,
1231
+		[AUD_CLKID_LOCKER]		= &locker.hw,
1232
+		[AUD_CLKID_SPDIFIN_LB]		= &spdifin_lb.hw,
1233
+		[AUD_CLKID_FRDDR_D]		= &frddr_d.hw,
1234
+		[AUD_CLKID_TODDR_D]		= &toddr_d.hw,
1235
+		[AUD_CLKID_LOOPBACK_B]		= &loopback_b.hw,
1236
+		[AUD_CLKID_CLK81_EN]		= &sm1_clk81_en.hw,
1237
+		[AUD_CLKID_SYSCLK_A_DIV]	= &sm1_sysclk_a_div.hw,
1238
+		[AUD_CLKID_SYSCLK_A_EN]		= &sm1_sysclk_a_en.hw,
1239
+		[AUD_CLKID_SYSCLK_B_DIV]	= &sm1_sysclk_b_div.hw,
1240
+		[AUD_CLKID_SYSCLK_B_EN]		= &sm1_sysclk_b_en.hw,
1241
+		[NR_CLKS] = NULL,
1242
+	},
1243
+	.num = NR_CLKS,
1244
+};
1245
+
1246
+
1247
+/* Convenience table to populate regmap in .probe(). */
1248
+static struct clk_regmap *const axg_clk_regmaps[] = {
1249
+	&ddr_arb,
1250
+	&pdm,
1251
+	&tdmin_a,
1252
+	&tdmin_b,
1253
+	&tdmin_c,
1254
+	&tdmin_lb,
1255
+	&tdmout_a,
1256
+	&tdmout_b,
1257
+	&tdmout_c,
1258
+	&frddr_a,
1259
+	&frddr_b,
1260
+	&frddr_c,
1261
+	&toddr_a,
1262
+	&toddr_b,
1263
+	&toddr_c,
1264
+	&loopback,
1265
+	&spdifin,
1266
+	&spdifout,
1267
+	&resample,
1268
+	&power_detect,
1269
+	&mst_a_mclk_sel,
1270
+	&mst_b_mclk_sel,
1271
+	&mst_c_mclk_sel,
1272
+	&mst_d_mclk_sel,
1273
+	&mst_e_mclk_sel,
1274
+	&mst_f_mclk_sel,
1275
+	&mst_a_mclk_div,
1276
+	&mst_b_mclk_div,
1277
+	&mst_c_mclk_div,
1278
+	&mst_d_mclk_div,
1279
+	&mst_e_mclk_div,
1280
+	&mst_f_mclk_div,
1281
+	&mst_a_mclk,
1282
+	&mst_b_mclk,
1283
+	&mst_c_mclk,
1284
+	&mst_d_mclk,
1285
+	&mst_e_mclk,
1286
+	&mst_f_mclk,
1287
+	&spdifout_clk_sel,
1288
+	&spdifout_clk_div,
1289
+	&spdifout_clk,
1290
+	&spdifin_clk_sel,
1291
+	&spdifin_clk_div,
1292
+	&spdifin_clk,
1293
+	&pdm_dclk_sel,
1294
+	&pdm_dclk_div,
1295
+	&pdm_dclk,
1296
+	&pdm_sysclk_sel,
1297
+	&pdm_sysclk_div,
1298
+	&pdm_sysclk,
1299
+	&mst_a_sclk_pre_en,
1300
+	&mst_b_sclk_pre_en,
1301
+	&mst_c_sclk_pre_en,
1302
+	&mst_d_sclk_pre_en,
1303
+	&mst_e_sclk_pre_en,
1304
+	&mst_f_sclk_pre_en,
1305
+	&mst_a_sclk_div,
1306
+	&mst_b_sclk_div,
1307
+	&mst_c_sclk_div,
1308
+	&mst_d_sclk_div,
1309
+	&mst_e_sclk_div,
1310
+	&mst_f_sclk_div,
1311
+	&mst_a_sclk_post_en,
1312
+	&mst_b_sclk_post_en,
1313
+	&mst_c_sclk_post_en,
1314
+	&mst_d_sclk_post_en,
1315
+	&mst_e_sclk_post_en,
1316
+	&mst_f_sclk_post_en,
1317
+	&mst_a_sclk,
1318
+	&mst_b_sclk,
1319
+	&mst_c_sclk,
1320
+	&mst_d_sclk,
1321
+	&mst_e_sclk,
1322
+	&mst_f_sclk,
1323
+	&mst_a_lrclk_div,
1324
+	&mst_b_lrclk_div,
1325
+	&mst_c_lrclk_div,
1326
+	&mst_d_lrclk_div,
1327
+	&mst_e_lrclk_div,
1328
+	&mst_f_lrclk_div,
1329
+	&mst_a_lrclk,
1330
+	&mst_b_lrclk,
1331
+	&mst_c_lrclk,
1332
+	&mst_d_lrclk,
1333
+	&mst_e_lrclk,
1334
+	&mst_f_lrclk,
1335
+	&tdmin_a_sclk_sel,
1336
+	&tdmin_b_sclk_sel,
1337
+	&tdmin_c_sclk_sel,
1338
+	&tdmin_lb_sclk_sel,
1339
+	&tdmout_a_sclk_sel,
1340
+	&tdmout_b_sclk_sel,
1341
+	&tdmout_c_sclk_sel,
1342
+	&tdmin_a_sclk_pre_en,
1343
+	&tdmin_b_sclk_pre_en,
1344
+	&tdmin_c_sclk_pre_en,
1345
+	&tdmin_lb_sclk_pre_en,
1346
+	&tdmout_a_sclk_pre_en,
1347
+	&tdmout_b_sclk_pre_en,
1348
+	&tdmout_c_sclk_pre_en,
1349
+	&tdmin_a_sclk_post_en,
1350
+	&tdmin_b_sclk_post_en,
1351
+	&tdmin_c_sclk_post_en,
1352
+	&tdmin_lb_sclk_post_en,
1353
+	&tdmout_a_sclk_post_en,
1354
+	&tdmout_b_sclk_post_en,
1355
+	&tdmout_c_sclk_post_en,
1356
+	&tdmin_a_sclk,
1357
+	&tdmin_b_sclk,
1358
+	&tdmin_c_sclk,
1359
+	&tdmin_lb_sclk,
6101360 	&axg_tdmout_a_sclk,
6111361 	&axg_tdmout_b_sclk,
6121362 	&axg_tdmout_c_sclk,
613
-	&axg_tdmin_a_lrclk,
614
-	&axg_tdmin_b_lrclk,
615
-	&axg_tdmin_c_lrclk,
616
-	&axg_tdmin_lb_lrclk,
617
-	&axg_tdmout_a_lrclk,
618
-	&axg_tdmout_b_lrclk,
619
-	&axg_tdmout_c_lrclk,
1363
+	&tdmin_a_lrclk,
1364
+	&tdmin_b_lrclk,
1365
+	&tdmin_c_lrclk,
1366
+	&tdmin_lb_lrclk,
1367
+	&tdmout_a_lrclk,
1368
+	&tdmout_b_lrclk,
1369
+	&tdmout_c_lrclk,
6201370 };
6211371 
622
-static struct clk *devm_clk_get_enable(struct device *dev, char *id)
1372
+static struct clk_regmap *const g12a_clk_regmaps[] = {
1373
+	&ddr_arb,
1374
+	&pdm,
1375
+	&tdmin_a,
1376
+	&tdmin_b,
1377
+	&tdmin_c,
1378
+	&tdmin_lb,
1379
+	&tdmout_a,
1380
+	&tdmout_b,
1381
+	&tdmout_c,
1382
+	&frddr_a,
1383
+	&frddr_b,
1384
+	&frddr_c,
1385
+	&toddr_a,
1386
+	&toddr_b,
1387
+	&toddr_c,
1388
+	&loopback,
1389
+	&spdifin,
1390
+	&spdifout,
1391
+	&resample,
1392
+	&power_detect,
1393
+	&spdifout_b,
1394
+	&mst_a_mclk_sel,
1395
+	&mst_b_mclk_sel,
1396
+	&mst_c_mclk_sel,
1397
+	&mst_d_mclk_sel,
1398
+	&mst_e_mclk_sel,
1399
+	&mst_f_mclk_sel,
1400
+	&mst_a_mclk_div,
1401
+	&mst_b_mclk_div,
1402
+	&mst_c_mclk_div,
1403
+	&mst_d_mclk_div,
1404
+	&mst_e_mclk_div,
1405
+	&mst_f_mclk_div,
1406
+	&mst_a_mclk,
1407
+	&mst_b_mclk,
1408
+	&mst_c_mclk,
1409
+	&mst_d_mclk,
1410
+	&mst_e_mclk,
1411
+	&mst_f_mclk,
1412
+	&spdifout_clk_sel,
1413
+	&spdifout_clk_div,
1414
+	&spdifout_clk,
1415
+	&spdifin_clk_sel,
1416
+	&spdifin_clk_div,
1417
+	&spdifin_clk,
1418
+	&pdm_dclk_sel,
1419
+	&pdm_dclk_div,
1420
+	&pdm_dclk,
1421
+	&pdm_sysclk_sel,
1422
+	&pdm_sysclk_div,
1423
+	&pdm_sysclk,
1424
+	&mst_a_sclk_pre_en,
1425
+	&mst_b_sclk_pre_en,
1426
+	&mst_c_sclk_pre_en,
1427
+	&mst_d_sclk_pre_en,
1428
+	&mst_e_sclk_pre_en,
1429
+	&mst_f_sclk_pre_en,
1430
+	&mst_a_sclk_div,
1431
+	&mst_b_sclk_div,
1432
+	&mst_c_sclk_div,
1433
+	&mst_d_sclk_div,
1434
+	&mst_e_sclk_div,
1435
+	&mst_f_sclk_div,
1436
+	&mst_a_sclk_post_en,
1437
+	&mst_b_sclk_post_en,
1438
+	&mst_c_sclk_post_en,
1439
+	&mst_d_sclk_post_en,
1440
+	&mst_e_sclk_post_en,
1441
+	&mst_f_sclk_post_en,
1442
+	&mst_a_sclk,
1443
+	&mst_b_sclk,
1444
+	&mst_c_sclk,
1445
+	&mst_d_sclk,
1446
+	&mst_e_sclk,
1447
+	&mst_f_sclk,
1448
+	&mst_a_lrclk_div,
1449
+	&mst_b_lrclk_div,
1450
+	&mst_c_lrclk_div,
1451
+	&mst_d_lrclk_div,
1452
+	&mst_e_lrclk_div,
1453
+	&mst_f_lrclk_div,
1454
+	&mst_a_lrclk,
1455
+	&mst_b_lrclk,
1456
+	&mst_c_lrclk,
1457
+	&mst_d_lrclk,
1458
+	&mst_e_lrclk,
1459
+	&mst_f_lrclk,
1460
+	&tdmin_a_sclk_sel,
1461
+	&tdmin_b_sclk_sel,
1462
+	&tdmin_c_sclk_sel,
1463
+	&tdmin_lb_sclk_sel,
1464
+	&tdmout_a_sclk_sel,
1465
+	&tdmout_b_sclk_sel,
1466
+	&tdmout_c_sclk_sel,
1467
+	&tdmin_a_sclk_pre_en,
1468
+	&tdmin_b_sclk_pre_en,
1469
+	&tdmin_c_sclk_pre_en,
1470
+	&tdmin_lb_sclk_pre_en,
1471
+	&tdmout_a_sclk_pre_en,
1472
+	&tdmout_b_sclk_pre_en,
1473
+	&tdmout_c_sclk_pre_en,
1474
+	&tdmin_a_sclk_post_en,
1475
+	&tdmin_b_sclk_post_en,
1476
+	&tdmin_c_sclk_post_en,
1477
+	&tdmin_lb_sclk_post_en,
1478
+	&tdmout_a_sclk_post_en,
1479
+	&tdmout_b_sclk_post_en,
1480
+	&tdmout_c_sclk_post_en,
1481
+	&tdmin_a_sclk,
1482
+	&tdmin_b_sclk,
1483
+	&tdmin_c_sclk,
1484
+	&tdmin_lb_sclk,
1485
+	&g12a_tdmout_a_sclk,
1486
+	&g12a_tdmout_b_sclk,
1487
+	&g12a_tdmout_c_sclk,
1488
+	&tdmin_a_lrclk,
1489
+	&tdmin_b_lrclk,
1490
+	&tdmin_c_lrclk,
1491
+	&tdmin_lb_lrclk,
1492
+	&tdmout_a_lrclk,
1493
+	&tdmout_b_lrclk,
1494
+	&tdmout_c_lrclk,
1495
+	&spdifout_b_clk_sel,
1496
+	&spdifout_b_clk_div,
1497
+	&spdifout_b_clk,
1498
+	&g12a_tdm_mclk_pad_0,
1499
+	&g12a_tdm_mclk_pad_1,
1500
+	&g12a_tdm_lrclk_pad_0,
1501
+	&g12a_tdm_lrclk_pad_1,
1502
+	&g12a_tdm_lrclk_pad_2,
1503
+	&g12a_tdm_sclk_pad_0,
1504
+	&g12a_tdm_sclk_pad_1,
1505
+	&g12a_tdm_sclk_pad_2,
1506
+	&toram,
1507
+	&eqdrc,
1508
+};
1509
+
1510
+static struct clk_regmap *const sm1_clk_regmaps[] = {
1511
+	&ddr_arb,
1512
+	&pdm,
1513
+	&tdmin_a,
1514
+	&tdmin_b,
1515
+	&tdmin_c,
1516
+	&tdmin_lb,
1517
+	&tdmout_a,
1518
+	&tdmout_b,
1519
+	&tdmout_c,
1520
+	&frddr_a,
1521
+	&frddr_b,
1522
+	&frddr_c,
1523
+	&toddr_a,
1524
+	&toddr_b,
1525
+	&toddr_c,
1526
+	&loopback,
1527
+	&spdifin,
1528
+	&spdifout,
1529
+	&resample,
1530
+	&spdifout_b,
1531
+	&sm1_mst_a_mclk_sel,
1532
+	&sm1_mst_b_mclk_sel,
1533
+	&sm1_mst_c_mclk_sel,
1534
+	&sm1_mst_d_mclk_sel,
1535
+	&sm1_mst_e_mclk_sel,
1536
+	&sm1_mst_f_mclk_sel,
1537
+	&sm1_mst_a_mclk_div,
1538
+	&sm1_mst_b_mclk_div,
1539
+	&sm1_mst_c_mclk_div,
1540
+	&sm1_mst_d_mclk_div,
1541
+	&sm1_mst_e_mclk_div,
1542
+	&sm1_mst_f_mclk_div,
1543
+	&sm1_mst_a_mclk,
1544
+	&sm1_mst_b_mclk,
1545
+	&sm1_mst_c_mclk,
1546
+	&sm1_mst_d_mclk,
1547
+	&sm1_mst_e_mclk,
1548
+	&sm1_mst_f_mclk,
1549
+	&spdifout_clk_sel,
1550
+	&spdifout_clk_div,
1551
+	&spdifout_clk,
1552
+	&spdifin_clk_sel,
1553
+	&spdifin_clk_div,
1554
+	&spdifin_clk,
1555
+	&pdm_dclk_sel,
1556
+	&pdm_dclk_div,
1557
+	&pdm_dclk,
1558
+	&pdm_sysclk_sel,
1559
+	&pdm_sysclk_div,
1560
+	&pdm_sysclk,
1561
+	&mst_a_sclk_pre_en,
1562
+	&mst_b_sclk_pre_en,
1563
+	&mst_c_sclk_pre_en,
1564
+	&mst_d_sclk_pre_en,
1565
+	&mst_e_sclk_pre_en,
1566
+	&mst_f_sclk_pre_en,
1567
+	&mst_a_sclk_div,
1568
+	&mst_b_sclk_div,
1569
+	&mst_c_sclk_div,
1570
+	&mst_d_sclk_div,
1571
+	&mst_e_sclk_div,
1572
+	&mst_f_sclk_div,
1573
+	&mst_a_sclk_post_en,
1574
+	&mst_b_sclk_post_en,
1575
+	&mst_c_sclk_post_en,
1576
+	&mst_d_sclk_post_en,
1577
+	&mst_e_sclk_post_en,
1578
+	&mst_f_sclk_post_en,
1579
+	&mst_a_sclk,
1580
+	&mst_b_sclk,
1581
+	&mst_c_sclk,
1582
+	&mst_d_sclk,
1583
+	&mst_e_sclk,
1584
+	&mst_f_sclk,
1585
+	&mst_a_lrclk_div,
1586
+	&mst_b_lrclk_div,
1587
+	&mst_c_lrclk_div,
1588
+	&mst_d_lrclk_div,
1589
+	&mst_e_lrclk_div,
1590
+	&mst_f_lrclk_div,
1591
+	&mst_a_lrclk,
1592
+	&mst_b_lrclk,
1593
+	&mst_c_lrclk,
1594
+	&mst_d_lrclk,
1595
+	&mst_e_lrclk,
1596
+	&mst_f_lrclk,
1597
+	&tdmin_a_sclk_sel,
1598
+	&tdmin_b_sclk_sel,
1599
+	&tdmin_c_sclk_sel,
1600
+	&tdmin_lb_sclk_sel,
1601
+	&tdmout_a_sclk_sel,
1602
+	&tdmout_b_sclk_sel,
1603
+	&tdmout_c_sclk_sel,
1604
+	&tdmin_a_sclk_pre_en,
1605
+	&tdmin_b_sclk_pre_en,
1606
+	&tdmin_c_sclk_pre_en,
1607
+	&tdmin_lb_sclk_pre_en,
1608
+	&tdmout_a_sclk_pre_en,
1609
+	&tdmout_b_sclk_pre_en,
1610
+	&tdmout_c_sclk_pre_en,
1611
+	&tdmin_a_sclk_post_en,
1612
+	&tdmin_b_sclk_post_en,
1613
+	&tdmin_c_sclk_post_en,
1614
+	&tdmin_lb_sclk_post_en,
1615
+	&tdmout_a_sclk_post_en,
1616
+	&tdmout_b_sclk_post_en,
1617
+	&tdmout_c_sclk_post_en,
1618
+	&tdmin_a_sclk,
1619
+	&tdmin_b_sclk,
1620
+	&tdmin_c_sclk,
1621
+	&tdmin_lb_sclk,
1622
+	&g12a_tdmout_a_sclk,
1623
+	&g12a_tdmout_b_sclk,
1624
+	&g12a_tdmout_c_sclk,
1625
+	&tdmin_a_lrclk,
1626
+	&tdmin_b_lrclk,
1627
+	&tdmin_c_lrclk,
1628
+	&tdmin_lb_lrclk,
1629
+	&tdmout_a_lrclk,
1630
+	&tdmout_b_lrclk,
1631
+	&tdmout_c_lrclk,
1632
+	&spdifout_b_clk_sel,
1633
+	&spdifout_b_clk_div,
1634
+	&spdifout_b_clk,
1635
+	&sm1_tdm_mclk_pad_0,
1636
+	&sm1_tdm_mclk_pad_1,
1637
+	&sm1_tdm_lrclk_pad_0,
1638
+	&sm1_tdm_lrclk_pad_1,
1639
+	&sm1_tdm_lrclk_pad_2,
1640
+	&sm1_tdm_sclk_pad_0,
1641
+	&sm1_tdm_sclk_pad_1,
1642
+	&sm1_tdm_sclk_pad_2,
1643
+	&sm1_aud_top,
1644
+	&toram,
1645
+	&eqdrc,
1646
+	&resample_b,
1647
+	&tovad,
1648
+	&locker,
1649
+	&spdifin_lb,
1650
+	&frddr_d,
1651
+	&toddr_d,
1652
+	&loopback_b,
1653
+	&sm1_clk81_en,
1654
+	&sm1_sysclk_a_div,
1655
+	&sm1_sysclk_a_en,
1656
+	&sm1_sysclk_b_div,
1657
+	&sm1_sysclk_b_en,
1658
+};
1659
+
1660
+static int devm_clk_get_enable(struct device *dev, char *id)
6231661 {
6241662 	struct clk *clk;
6251663 	int ret;
6261664 
6271665 	clk = devm_clk_get(dev, id);
6281666 	if (IS_ERR(clk)) {
629
-		if (PTR_ERR(clk) != -EPROBE_DEFER)
1667
+		ret = PTR_ERR(clk);
1668
+		if (ret != -EPROBE_DEFER)
6301669 			dev_err(dev, "failed to get %s", id);
631
-		return clk;
1670
+		return ret;
6321671 	}
6331672 
6341673 	ret = clk_prepare_enable(clk);
6351674 	if (ret) {
6361675 		dev_err(dev, "failed to enable %s", id);
637
-		return ERR_PTR(ret);
1676
+		return ret;
6381677 	}
6391678 
6401679 	ret = devm_add_action_or_reset(dev,
....@@ -642,117 +1681,120 @@
6421681 				       clk);
6431682 	if (ret) {
6441683 		dev_err(dev, "failed to add reset action on %s", id);
645
-		return ERR_PTR(ret);
1684
+		return ret;
6461685 	}
6471686 
648
-	return clk;
1687
+	return 0;
6491688 }
6501689 
651
-static const struct clk_ops axg_clk_no_ops = {};
1690
+struct axg_audio_reset_data {
1691
+	struct reset_controller_dev rstc;
1692
+	struct regmap *map;
1693
+	unsigned int offset;
1694
+};
6521695 
653
-static struct clk_hw *axg_clk_hw_register_bypass(struct device *dev,
654
-						 const char *name,
655
-						 const char *parent_name)
1696
+static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
1697
+					unsigned long id,
1698
+					unsigned int *reg,
1699
+					unsigned int *bit)
6561700 {
657
-	struct clk_hw *hw;
658
-	struct clk_init_data init = {};
659
-	char *clk_name;
1701
+	unsigned int stride = regmap_get_reg_stride(rst->map);
1702
+
1703
+	*reg = (id / (stride * BITS_PER_BYTE)) * stride;
1704
+	*reg += rst->offset;
1705
+	*bit = id % (stride * BITS_PER_BYTE);
1706
+}
1707
+
1708
+static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
1709
+				unsigned long id, bool assert)
1710
+{
1711
+	struct axg_audio_reset_data *rst =
1712
+		container_of(rcdev, struct axg_audio_reset_data, rstc);
1713
+	unsigned int offset, bit;
1714
+
1715
+	axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1716
+
1717
+	regmap_update_bits(rst->map, offset, BIT(bit),
1718
+			assert ? BIT(bit) : 0);
1719
+
1720
+	return 0;
1721
+}
1722
+
1723
+static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
1724
+				unsigned long id)
1725
+{
1726
+	struct axg_audio_reset_data *rst =
1727
+		container_of(rcdev, struct axg_audio_reset_data, rstc);
1728
+	unsigned int val, offset, bit;
1729
+
1730
+	axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
1731
+
1732
+	regmap_read(rst->map, offset, &val);
1733
+
1734
+	return !!(val & BIT(bit));
1735
+}
1736
+
1737
+static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
1738
+				unsigned long id)
1739
+{
1740
+	return axg_audio_reset_update(rcdev, id, true);
1741
+}
1742
+
1743
+static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
1744
+				unsigned long id)
1745
+{
1746
+	return axg_audio_reset_update(rcdev, id, false);
1747
+}
1748
+
1749
+static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
1750
+				unsigned long id)
1751
+{
6601752 	int ret;
6611753 
662
-	hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
663
-	if (!hw)
664
-		return ERR_PTR(-ENOMEM);
1754
+	ret = axg_audio_reset_assert(rcdev, id);
1755
+	if (ret)
1756
+		return ret;
6651757 
666
-	clk_name = kasprintf(GFP_KERNEL, "axg_%s", name);
667
-	if (!clk_name)
668
-		return ERR_PTR(-ENOMEM);
669
-
670
-	init.name = clk_name;
671
-	init.ops = &axg_clk_no_ops;
672
-	init.flags = 0;
673
-	init.parent_names = parent_name ? &parent_name : NULL;
674
-	init.num_parents = parent_name ? 1 : 0;
675
-	hw->init = &init;
676
-
677
-	ret = devm_clk_hw_register(dev, hw);
678
-	kfree(clk_name);
679
-
680
-	return ret ? ERR_PTR(ret) : hw;
1758
+	return axg_audio_reset_deassert(rcdev, id);
6811759 }
6821760 
683
-static int axg_register_clk_hw_input(struct device *dev,
684
-				     const char *name,
685
-				     unsigned int clkid)
686
-{
687
-	struct clk *parent_clk = devm_clk_get(dev, name);
688
-	struct clk_hw *hw = NULL;
689
-
690
-	if (IS_ERR(parent_clk)) {
691
-		int err = PTR_ERR(parent_clk);
692
-
693
-		/* It is ok if an input clock is missing */
694
-		if (err == -ENOENT) {
695
-			dev_dbg(dev, "%s not provided", name);
696
-		} else {
697
-			if (err != -EPROBE_DEFER)
698
-				dev_err(dev, "failed to get %s clock", name);
699
-			return err;
700
-		}
701
-	} else {
702
-		hw = axg_clk_hw_register_bypass(dev, name,
703
-						__clk_get_name(parent_clk));
704
-	}
705
-
706
-	if (IS_ERR(hw)) {
707
-		dev_err(dev, "failed to register %s clock", name);
708
-		return PTR_ERR(hw);
709
-	}
710
-
711
-	axg_audio_hw_onecell_data.hws[clkid] = hw;
712
-	return 0;
713
-}
714
-
715
-static int axg_register_clk_hw_inputs(struct device *dev,
716
-				      const char *basename,
717
-				      unsigned int count,
718
-				      unsigned int clkid)
719
-{
720
-	char *name;
721
-	int i, ret;
722
-
723
-	for (i = 0; i < count; i++) {
724
-		name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
725
-		if (!name)
726
-			return -ENOMEM;
727
-
728
-		ret = axg_register_clk_hw_input(dev, name, clkid + i);
729
-		kfree(name);
730
-		if (ret)
731
-			return ret;
732
-	}
733
-
734
-	return 0;
735
-}
1761
+static const struct reset_control_ops axg_audio_rstc_ops = {
1762
+	.assert = axg_audio_reset_assert,
1763
+	.deassert = axg_audio_reset_deassert,
1764
+	.reset = axg_audio_reset_toggle,
1765
+	.status = axg_audio_reset_status,
1766
+};
7361767 
7371768 static const struct regmap_config axg_audio_regmap_cfg = {
7381769 	.reg_bits	= 32,
7391770 	.val_bits	= 32,
7401771 	.reg_stride	= 4,
741
-	.max_register	= AUDIO_CLK_PDMIN_CTRL1,
1772
+	.max_register	= AUDIO_CLK_SPDIFOUT_B_CTRL,
1773
+};
1774
+
1775
+struct audioclk_data {
1776
+	struct clk_regmap *const *regmap_clks;
1777
+	unsigned int regmap_clk_num;
1778
+	struct clk_hw_onecell_data *hw_onecell_data;
1779
+	unsigned int reset_offset;
1780
+	unsigned int reset_num;
7421781 };
7431782 
7441783 static int axg_audio_clkc_probe(struct platform_device *pdev)
7451784 {
7461785 	struct device *dev = &pdev->dev;
1786
+	const struct audioclk_data *data;
1787
+	struct axg_audio_reset_data *rst;
7471788 	struct regmap *map;
748
-	struct resource *res;
7491789 	void __iomem *regs;
750
-	struct clk *clk;
7511790 	struct clk_hw *hw;
7521791 	int ret, i;
7531792 
754
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
755
-	regs = devm_ioremap_resource(dev, res);
1793
+	data = of_device_get_match_data(dev);
1794
+	if (!data)
1795
+		return -EINVAL;
1796
+
1797
+	regs = devm_platform_ioremap_resource(pdev, 0);
7561798 	if (IS_ERR(regs))
7571799 		return PTR_ERR(regs);
7581800 
....@@ -763,9 +1805,9 @@
7631805 	}
7641806 
7651807 	/* Get the mandatory peripheral clock */
766
-	clk = devm_clk_get_enable(dev, "pclk");
767
-	if (IS_ERR(clk))
768
-		return PTR_ERR(clk);
1808
+	ret = devm_clk_get_enable(dev, "pclk");
1809
+	if (ret)
1810
+		return ret;
7691811 
7701812 	ret = device_reset(dev);
7711813 	if (ret) {
....@@ -773,61 +1815,84 @@
7731815 		return ret;
7741816 	}
7751817 
776
-	/* Register the peripheral input clock */
777
-	hw = axg_clk_hw_register_bypass(dev, "audio_pclk",
778
-					__clk_get_name(clk));
779
-	if (IS_ERR(hw))
780
-		return PTR_ERR(hw);
781
-
782
-	axg_audio_hw_onecell_data.hws[AUD_CLKID_PCLK] = hw;
783
-
784
-	/* Register optional input master clocks */
785
-	ret = axg_register_clk_hw_inputs(dev, "mst_in",
786
-					 AXG_MST_IN_COUNT,
787
-					 AUD_CLKID_MST0);
788
-	if (ret)
789
-		return ret;
790
-
791
-	/* Register optional input slave sclks */
792
-	ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
793
-					 AXG_SLV_SCLK_COUNT,
794
-					 AUD_CLKID_SLV_SCLK0);
795
-	if (ret)
796
-		return ret;
797
-
798
-	/* Register optional input slave lrclks */
799
-	ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
800
-					 AXG_SLV_LRCLK_COUNT,
801
-					 AUD_CLKID_SLV_LRCLK0);
802
-	if (ret)
803
-		return ret;
804
-
8051818 	/* Populate regmap for the regmap backed clocks */
806
-	for (i = 0; i < ARRAY_SIZE(axg_audio_clk_regmaps); i++)
807
-		axg_audio_clk_regmaps[i]->map = map;
1819
+	for (i = 0; i < data->regmap_clk_num; i++)
1820
+		data->regmap_clks[i]->map = map;
8081821 
8091822 	/* Take care to skip the registered input clocks */
810
-	for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) {
811
-		hw = axg_audio_hw_onecell_data.hws[i];
1823
+	for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
1824
+		const char *name;
1825
+
1826
+		hw = data->hw_onecell_data->hws[i];
8121827 		/* array might be sparse */
8131828 		if (!hw)
8141829 			continue;
8151830 
1831
+		name = hw->init->name;
1832
+
8161833 		ret = devm_clk_hw_register(dev, hw);
8171834 		if (ret) {
818
-			dev_err(dev, "failed to register clock %s\n",
819
-				hw->init->name);
1835
+			dev_err(dev, "failed to register clock %s\n", name);
8201836 			return ret;
8211837 		}
8221838 	}
8231839 
824
-	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
825
-					   &axg_audio_hw_onecell_data);
1840
+	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1841
+					data->hw_onecell_data);
1842
+	if (ret)
1843
+		return ret;
1844
+
1845
+	/* Stop here if there is no reset */
1846
+	if (!data->reset_num)
1847
+		return 0;
1848
+
1849
+	rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1850
+	if (!rst)
1851
+		return -ENOMEM;
1852
+
1853
+	rst->map = map;
1854
+	rst->offset = data->reset_offset;
1855
+	rst->rstc.nr_resets = data->reset_num;
1856
+	rst->rstc.ops = &axg_audio_rstc_ops;
1857
+	rst->rstc.of_node = dev->of_node;
1858
+	rst->rstc.owner = THIS_MODULE;
1859
+
1860
+	return devm_reset_controller_register(dev, &rst->rstc);
8261861 }
8271862 
1863
+static const struct audioclk_data axg_audioclk_data = {
1864
+	.regmap_clks = axg_clk_regmaps,
1865
+	.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1866
+	.hw_onecell_data = &axg_audio_hw_onecell_data,
1867
+};
1868
+
1869
+static const struct audioclk_data g12a_audioclk_data = {
1870
+	.regmap_clks = g12a_clk_regmaps,
1871
+	.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
1872
+	.hw_onecell_data = &g12a_audio_hw_onecell_data,
1873
+	.reset_offset = AUDIO_SW_RESET,
1874
+	.reset_num = 26,
1875
+};
1876
+
1877
+static const struct audioclk_data sm1_audioclk_data = {
1878
+	.regmap_clks = sm1_clk_regmaps,
1879
+	.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
1880
+	.hw_onecell_data = &sm1_audio_hw_onecell_data,
1881
+	.reset_offset = AUDIO_SM1_SW_RESET0,
1882
+	.reset_num = 39,
1883
+};
1884
+
8281885 static const struct of_device_id clkc_match_table[] = {
829
-	{ .compatible = "amlogic,axg-audio-clkc" },
830
-	{}
1886
+	{
1887
+		.compatible = "amlogic,axg-audio-clkc",
1888
+		.data = &axg_audioclk_data
1889
+	}, {
1890
+		.compatible = "amlogic,g12a-audio-clkc",
1891
+		.data = &g12a_audioclk_data
1892
+	}, {
1893
+		.compatible = "amlogic,sm1-audio-clkc",
1894
+		.data = &sm1_audioclk_data
1895
+	}, {}
8311896 };
8321897 MODULE_DEVICE_TABLE(of, clkc_match_table);
8331898 
....@@ -840,6 +1905,6 @@
8401905 };
8411906 module_platform_driver(axg_audio_driver);
8421907 
843
-MODULE_DESCRIPTION("Amlogic A113x Audio Clock driver");
1908
+MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver");
8441909 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
8451910 MODULE_LICENSE("GPL v2");