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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/clk/ingenic/jz4770-cgu.c
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@@ -7,10 +7,13 @@
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 #include <linux/bitops.h>
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 #include <linux/clk-provider.h>
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 #include <linux/delay.h>
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+#include <linux/io.h>
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 #include <linux/of.h>
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-#include <linux/syscore_ops.h>
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+
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 #include <dt-bindings/clock/jz4770-cgu.h>
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+
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 #include "cgu.h"
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+#include "pm.h"
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 /*
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  * CPM registers offset address definition
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@@ -36,9 +39,6 @@
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 #define CGU_REG_MSC1CDR		0xA4
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 #define CGU_REG_MSC2CDR		0xA8
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 #define CGU_REG_BCHCDR		0xAC
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-
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-/* bits within the LCR register */
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-#define LCR_LPM			BIT(0)		/* Low Power Mode */
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 /* bits within the OPCR register */
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 #define OPCR_SPENDH		BIT(5)		/* UHC PHY suspend */
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@@ -86,6 +86,10 @@
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 	0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
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 };
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+static const u8 jz4770_cgu_cpccr_div_table[] = {
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+	1, 2, 3, 4, 6, 8, 12,
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+};
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+
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 static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
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 	/* External clocks */
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@@ -100,6 +104,7 @@
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 		.parents = { JZ4770_CLK_EXT },
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 		.pll = {
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 			.reg = CGU_REG_CPPCR0,
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+			.rate_multiplier = 1,
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 			.m_shift = 24,
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 			.m_bits = 7,
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 			.m_offset = 1,
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@@ -110,6 +115,7 @@
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 			.od_bits = 2,
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 			.od_max = 8,
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 			.od_encoding = pll_od_encoding,
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+			.bypass_reg = CGU_REG_CPPCR0,
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 			.bypass_bit = 9,
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 			.enable_bit = 8,
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 			.stable_bit = 10,
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@@ -122,6 +128,7 @@
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 		.parents = { JZ4770_CLK_EXT },
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 		.pll = {
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 			.reg = CGU_REG_CPPCR1,
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+			.rate_multiplier = 1,
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 			.m_shift = 24,
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 			.m_bits = 7,
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 			.m_offset = 1,
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@@ -132,9 +139,10 @@
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 			.od_bits = 2,
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 			.od_max = 8,
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 			.od_encoding = pll_od_encoding,
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+			.bypass_reg = CGU_REG_CPPCR1,
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+			.no_bypass_bit = true,
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 			.enable_bit = 7,
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 			.stable_bit = 6,
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-			.no_bypass_bit = true,
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 		},
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 	},
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@@ -143,34 +151,52 @@
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 	[JZ4770_CLK_CCLK] = {
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 		"cclk", CGU_CLK_DIV,
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 		.parents = { JZ4770_CLK_PLL0, },
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-		.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
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+		.div = {
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+			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
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+			jz4770_cgu_cpccr_div_table,
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+		},
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 	},
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 	[JZ4770_CLK_H0CLK] = {
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 		"h0clk", CGU_CLK_DIV,
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 		.parents = { JZ4770_CLK_PLL0, },
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-		.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
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+		.div = {
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+			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
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+			jz4770_cgu_cpccr_div_table,
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+		},
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 	},
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 	[JZ4770_CLK_H1CLK] = {
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 		"h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
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 		.parents = { JZ4770_CLK_PLL0, },
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-		.div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 },
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+		.div = {
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+			CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1,
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+			jz4770_cgu_cpccr_div_table,
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+		},
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 		.gate = { CGU_REG_CLKGR1, 7 },
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 	},
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 	[JZ4770_CLK_H2CLK] = {
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 		"h2clk", CGU_CLK_DIV,
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 		.parents = { JZ4770_CLK_PLL0, },
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-		.div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
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+		.div = {
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+			CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
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+			jz4770_cgu_cpccr_div_table,
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+		},
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 	},
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 	[JZ4770_CLK_C1CLK] = {
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 		"c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
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 		.parents = { JZ4770_CLK_PLL0, },
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-		.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
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+		.div = {
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+			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
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+			jz4770_cgu_cpccr_div_table,
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+		},
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 		.gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
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 	},
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 	[JZ4770_CLK_PCLK] = {
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 		"pclk", CGU_CLK_DIV,
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 		.parents = { JZ4770_CLK_PLL0, },
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-		.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
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+		.div = {
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+			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
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+			jz4770_cgu_cpccr_div_table,
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+		},
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 	},
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 	/* Those divided clocks can connect to PLL0 or PLL1 */
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@@ -406,30 +432,6 @@
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 	},
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 };
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-#if IS_ENABLED(CONFIG_PM_SLEEP)
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-static int jz4770_cgu_pm_suspend(void)
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-{
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-	u32 val;
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-
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-	val = readl(cgu->base + CGU_REG_LCR);
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-	writel(val | LCR_LPM, cgu->base + CGU_REG_LCR);
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-	return 0;
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-}
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-
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-static void jz4770_cgu_pm_resume(void)
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-{
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-	u32 val;
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-
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-	val = readl(cgu->base + CGU_REG_LCR);
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-	writel(val & ~LCR_LPM, cgu->base + CGU_REG_LCR);
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-}
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-
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-static struct syscore_ops jz4770_cgu_pm_ops = {
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-	.suspend = jz4770_cgu_pm_suspend,
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-	.resume = jz4770_cgu_pm_resume,
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-};
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-#endif /* CONFIG_PM_SLEEP */
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-
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 static void __init jz4770_cgu_init(struct device_node *np)
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 {
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 	int retval;
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@@ -445,10 +447,8 @@
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 	if (retval)
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 		pr_err("%s: failed to register CGU Clocks\n", __func__);
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-#if IS_ENABLED(CONFIG_PM_SLEEP)
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-	register_syscore_ops(&jz4770_cgu_pm_ops);
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-#endif
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+	ingenic_cgu_register_syscore_ops(cgu);
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 }
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 /* We only probe via devicetree, no need for a platform driver */
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-CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
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+CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);