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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/drivers/clk/at91/sckc.c
....@@ -1,13 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * drivers/clk/at91/sckc.c
34  *
45  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License, or
9
- * (at your option) any later version.
10
- *
116  */
127 
138 #include <linux/clk-provider.h>
....@@ -23,14 +18,18 @@
2318 				 SLOW_CLOCK_FREQ)
2419 
2520 #define	AT91_SCKC_CR			0x00
26
-#define		AT91_SCKC_RCEN		(1 << 0)
27
-#define		AT91_SCKC_OSC32EN	(1 << 1)
28
-#define		AT91_SCKC_OSC32BYP	(1 << 2)
29
-#define		AT91_SCKC_OSCSEL	(1 << 3)
21
+
22
+struct clk_slow_bits {
23
+	u32 cr_rcen;
24
+	u32 cr_osc32en;
25
+	u32 cr_osc32byp;
26
+	u32 cr_oscsel;
27
+};
3028 
3129 struct clk_slow_osc {
3230 	struct clk_hw hw;
3331 	void __iomem *sckcr;
32
+	const struct clk_slow_bits *bits;
3433 	unsigned long startup_usec;
3534 };
3635 
....@@ -39,6 +38,7 @@
3938 struct clk_sama5d4_slow_osc {
4039 	struct clk_hw hw;
4140 	void __iomem *sckcr;
41
+	const struct clk_slow_bits *bits;
4242 	unsigned long startup_usec;
4343 	bool prepared;
4444 };
....@@ -48,6 +48,7 @@
4848 struct clk_slow_rc_osc {
4949 	struct clk_hw hw;
5050 	void __iomem *sckcr;
51
+	const struct clk_slow_bits *bits;
5152 	unsigned long frequency;
5253 	unsigned long accuracy;
5354 	unsigned long startup_usec;
....@@ -58,6 +59,7 @@
5859 struct clk_sam9x5_slow {
5960 	struct clk_hw hw;
6061 	void __iomem *sckcr;
62
+	const struct clk_slow_bits *bits;
6163 	u8 parent;
6264 };
6365 
....@@ -69,10 +71,10 @@
6971 	void __iomem *sckcr = osc->sckcr;
7072 	u32 tmp = readl(sckcr);
7173 
72
-	if (tmp & (AT91_SCKC_OSC32BYP | AT91_SCKC_OSC32EN))
74
+	if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en))
7375 		return 0;
7476 
75
-	writel(tmp | AT91_SCKC_OSC32EN, sckcr);
77
+	writel(tmp | osc->bits->cr_osc32en, sckcr);
7678 
7779 	if (system_state < SYSTEM_RUNNING)
7880 		udelay(osc->startup_usec);
....@@ -88,10 +90,10 @@
8890 	void __iomem *sckcr = osc->sckcr;
8991 	u32 tmp = readl(sckcr);
9092 
91
-	if (tmp & AT91_SCKC_OSC32BYP)
93
+	if (tmp & osc->bits->cr_osc32byp)
9294 		return;
9395 
94
-	writel(tmp & ~AT91_SCKC_OSC32EN, sckcr);
96
+	writel(tmp & ~osc->bits->cr_osc32en, sckcr);
9597 }
9698 
9799 static int clk_slow_osc_is_prepared(struct clk_hw *hw)
....@@ -100,10 +102,10 @@
100102 	void __iomem *sckcr = osc->sckcr;
101103 	u32 tmp = readl(sckcr);
102104 
103
-	if (tmp & AT91_SCKC_OSC32BYP)
105
+	if (tmp & osc->bits->cr_osc32byp)
104106 		return 1;
105107 
106
-	return !!(tmp & AT91_SCKC_OSC32EN);
108
+	return !!(tmp & osc->bits->cr_osc32en);
107109 }
108110 
109111 static const struct clk_ops slow_osc_ops = {
....@@ -117,11 +119,12 @@
117119 			   const char *name,
118120 			   const char *parent_name,
119121 			   unsigned long startup,
120
-			   bool bypass)
122
+			   bool bypass,
123
+			   const struct clk_slow_bits *bits)
121124 {
122125 	struct clk_slow_osc *osc;
123126 	struct clk_hw *hw;
124
-	struct clk_init_data init = {};
127
+	struct clk_init_data init;
125128 	int ret;
126129 
127130 	if (!sckcr || !name || !parent_name)
....@@ -140,10 +143,11 @@
140143 	osc->hw.init = &init;
141144 	osc->sckcr = sckcr;
142145 	osc->startup_usec = startup;
146
+	osc->bits = bits;
143147 
144148 	if (bypass)
145
-		writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP,
146
-		       sckcr);
149
+		writel((readl(sckcr) & ~osc->bits->cr_osc32en) |
150
+					osc->bits->cr_osc32byp, sckcr);
147151 
148152 	hw = &osc->hw;
149153 	ret = clk_hw_register(NULL, &osc->hw);
....@@ -155,26 +159,12 @@
155159 	return hw;
156160 }
157161 
158
-static void __init
159
-of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr)
162
+static void at91_clk_unregister_slow_osc(struct clk_hw *hw)
160163 {
161
-	struct clk_hw *hw;
162
-	const char *parent_name;
163
-	const char *name = np->name;
164
-	u32 startup;
165
-	bool bypass;
164
+	struct clk_slow_osc *osc = to_clk_slow_osc(hw);
166165 
167
-	parent_name = of_clk_get_parent_name(np, 0);
168
-	of_property_read_string(np, "clock-output-names", &name);
169
-	of_property_read_u32(np, "atmel,startup-time-usec", &startup);
170
-	bypass = of_property_read_bool(np, "atmel,osc-bypass");
171
-
172
-	hw = at91_clk_register_slow_osc(sckcr, name, parent_name, startup,
173
-					 bypass);
174
-	if (IS_ERR(hw))
175
-		return;
176
-
177
-	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
166
+	clk_hw_unregister(hw);
167
+	kfree(osc);
178168 }
179169 
180170 static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,
....@@ -198,7 +188,7 @@
198188 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
199189 	void __iomem *sckcr = osc->sckcr;
200190 
201
-	writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr);
191
+	writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);
202192 
203193 	if (system_state < SYSTEM_RUNNING)
204194 		udelay(osc->startup_usec);
....@@ -213,14 +203,14 @@
213203 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
214204 	void __iomem *sckcr = osc->sckcr;
215205 
216
-	writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr);
206
+	writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr);
217207 }
218208 
219209 static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
220210 {
221211 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
222212 
223
-	return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);
213
+	return !!(readl(osc->sckcr) & osc->bits->cr_rcen);
224214 }
225215 
226216 static const struct clk_ops slow_rc_osc_ops = {
....@@ -236,11 +226,12 @@
236226 			      const char *name,
237227 			      unsigned long frequency,
238228 			      unsigned long accuracy,
239
-			      unsigned long startup)
229
+			      unsigned long startup,
230
+			      const struct clk_slow_bits *bits)
240231 {
241232 	struct clk_slow_rc_osc *osc;
242233 	struct clk_hw *hw;
243
-	struct clk_init_data init = {};
234
+	struct clk_init_data init;
244235 	int ret;
245236 
246237 	if (!sckcr || !name)
....@@ -258,6 +249,7 @@
258249 
259250 	osc->hw.init = &init;
260251 	osc->sckcr = sckcr;
252
+	osc->bits = bits;
261253 	osc->frequency = frequency;
262254 	osc->accuracy = accuracy;
263255 	osc->startup_usec = startup;
....@@ -272,26 +264,12 @@
272264 	return hw;
273265 }
274266 
275
-static void __init
276
-of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr)
267
+static void at91_clk_unregister_slow_rc_osc(struct clk_hw *hw)
277268 {
278
-	struct clk_hw *hw;
279
-	u32 frequency = 0;
280
-	u32 accuracy = 0;
281
-	u32 startup = 0;
282
-	const char *name = np->name;
269
+	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
283270 
284
-	of_property_read_string(np, "clock-output-names", &name);
285
-	of_property_read_u32(np, "clock-frequency", &frequency);
286
-	of_property_read_u32(np, "clock-accuracy", &accuracy);
287
-	of_property_read_u32(np, "atmel,startup-time-usec", &startup);
288
-
289
-	hw = at91_clk_register_slow_rc_osc(sckcr, name, frequency, accuracy,
290
-					    startup);
291
-	if (IS_ERR(hw))
292
-		return;
293
-
294
-	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
271
+	clk_hw_unregister(hw);
272
+	kfree(osc);
295273 }
296274 
297275 static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
....@@ -305,14 +283,14 @@
305283 
306284 	tmp = readl(sckcr);
307285 
308
-	if ((!index && !(tmp & AT91_SCKC_OSCSEL)) ||
309
-	    (index && (tmp & AT91_SCKC_OSCSEL)))
286
+	if ((!index && !(tmp & slowck->bits->cr_oscsel)) ||
287
+	    (index && (tmp & slowck->bits->cr_oscsel)))
310288 		return 0;
311289 
312290 	if (index)
313
-		tmp |= AT91_SCKC_OSCSEL;
291
+		tmp |= slowck->bits->cr_oscsel;
314292 	else
315
-		tmp &= ~AT91_SCKC_OSCSEL;
293
+		tmp &= ~slowck->bits->cr_oscsel;
316294 
317295 	writel(tmp, sckcr);
318296 
....@@ -328,7 +306,7 @@
328306 {
329307 	struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
330308 
331
-	return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);
309
+	return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel);
332310 }
333311 
334312 static const struct clk_ops sam9x5_slow_ops = {
....@@ -340,11 +318,12 @@
340318 at91_clk_register_sam9x5_slow(void __iomem *sckcr,
341319 			      const char *name,
342320 			      const char **parent_names,
343
-			      int num_parents)
321
+			      int num_parents,
322
+			      const struct clk_slow_bits *bits)
344323 {
345324 	struct clk_sam9x5_slow *slowck;
346325 	struct clk_hw *hw;
347
-	struct clk_init_data init = {};
326
+	struct clk_init_data init;
348327 	int ret;
349328 
350329 	if (!sckcr || !name || !parent_names || !num_parents)
....@@ -362,7 +341,8 @@
362341 
363342 	slowck->hw.init = &init;
364343 	slowck->sckcr = sckcr;
365
-	slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);
344
+	slowck->bits = bits;
345
+	slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel);
366346 
367347 	hw = &slowck->hw;
368348 	ret = clk_hw_register(NULL, &slowck->hw);
....@@ -374,67 +354,177 @@
374354 	return hw;
375355 }
376356 
377
-static void __init
378
-of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr)
357
+static void at91_clk_unregister_sam9x5_slow(struct clk_hw *hw)
379358 {
380
-	struct clk_hw *hw;
381
-	const char *parent_names[2];
382
-	unsigned int num_parents;
383
-	const char *name = np->name;
359
+	struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
384360 
385
-	num_parents = of_clk_get_parent_count(np);
386
-	if (num_parents == 0 || num_parents > 2)
387
-		return;
388
-
389
-	of_clk_parent_fill(np, parent_names, num_parents);
390
-
391
-	of_property_read_string(np, "clock-output-names", &name);
392
-
393
-	hw = at91_clk_register_sam9x5_slow(sckcr, name, parent_names,
394
-					    num_parents);
395
-	if (IS_ERR(hw))
396
-		return;
397
-
398
-	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
361
+	clk_hw_unregister(hw);
362
+	kfree(slowck);
399363 }
400364 
401
-static const struct of_device_id sckc_clk_ids[] __initconst = {
402
-	/* Slow clock */
403
-	{
404
-		.compatible = "atmel,at91sam9x5-clk-slow-osc",
405
-		.data = of_at91sam9x5_clk_slow_osc_setup,
406
-	},
407
-	{
408
-		.compatible = "atmel,at91sam9x5-clk-slow-rc-osc",
409
-		.data = of_at91sam9x5_clk_slow_rc_osc_setup,
410
-	},
411
-	{
412
-		.compatible = "atmel,at91sam9x5-clk-slow",
413
-		.data = of_at91sam9x5_clk_slow_setup,
414
-	},
415
-	{ /*sentinel*/ }
416
-};
417
-
418
-static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
365
+static void __init at91sam9x5_sckc_register(struct device_node *np,
366
+					    unsigned int rc_osc_startup_us,
367
+					    const struct clk_slow_bits *bits)
419368 {
420
-	struct device_node *childnp;
421
-	void (*clk_setup)(struct device_node *, void __iomem *);
422
-	const struct of_device_id *clk_id;
369
+	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
423370 	void __iomem *regbase = of_iomap(np, 0);
371
+	struct device_node *child = NULL;
372
+	const char *xtal_name;
373
+	struct clk_hw *slow_rc, *slow_osc, *slowck;
374
+	bool bypass;
375
+	int ret;
424376 
425377 	if (!regbase)
426378 		return;
427379 
428
-	for_each_child_of_node(np, childnp) {
429
-		clk_id = of_match_node(sckc_clk_ids, childnp);
430
-		if (!clk_id)
431
-			continue;
432
-		clk_setup = clk_id->data;
433
-		clk_setup(childnp, regbase);
380
+	slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0],
381
+						32768, 50000000,
382
+						rc_osc_startup_us, bits);
383
+	if (IS_ERR(slow_rc))
384
+		return;
385
+
386
+	xtal_name = of_clk_get_parent_name(np, 0);
387
+	if (!xtal_name) {
388
+		/* DT backward compatibility */
389
+		child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc");
390
+		if (!child)
391
+			goto unregister_slow_rc;
392
+
393
+		xtal_name = of_clk_get_parent_name(child, 0);
394
+		bypass = of_property_read_bool(child, "atmel,osc-bypass");
395
+
396
+		child =  of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow");
397
+	} else {
398
+		bypass = of_property_read_bool(np, "atmel,osc-bypass");
434399 	}
400
+
401
+	if (!xtal_name)
402
+		goto unregister_slow_rc;
403
+
404
+	slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
405
+					      xtal_name, 1200000, bypass, bits);
406
+	if (IS_ERR(slow_osc))
407
+		goto unregister_slow_rc;
408
+
409
+	slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names,
410
+					       2, bits);
411
+	if (IS_ERR(slowck))
412
+		goto unregister_slow_osc;
413
+
414
+	/* DT backward compatibility */
415
+	if (child)
416
+		ret = of_clk_add_hw_provider(child, of_clk_hw_simple_get,
417
+					     slowck);
418
+	else
419
+		ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);
420
+
421
+	if (WARN_ON(ret))
422
+		goto unregister_slowck;
423
+
424
+	return;
425
+
426
+unregister_slowck:
427
+	at91_clk_unregister_sam9x5_slow(slowck);
428
+unregister_slow_osc:
429
+	at91_clk_unregister_slow_osc(slow_osc);
430
+unregister_slow_rc:
431
+	at91_clk_unregister_slow_rc_osc(slow_rc);
432
+}
433
+
434
+static const struct clk_slow_bits at91sam9x5_bits = {
435
+	.cr_rcen = BIT(0),
436
+	.cr_osc32en = BIT(1),
437
+	.cr_osc32byp = BIT(2),
438
+	.cr_oscsel = BIT(3),
439
+};
440
+
441
+static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
442
+{
443
+	at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits);
435444 }
436445 CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
437446 	       of_at91sam9x5_sckc_setup);
447
+
448
+static void __init of_sama5d3_sckc_setup(struct device_node *np)
449
+{
450
+	at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits);
451
+}
452
+CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc",
453
+	       of_sama5d3_sckc_setup);
454
+
455
+static const struct clk_slow_bits at91sam9x60_bits = {
456
+	.cr_osc32en = BIT(1),
457
+	.cr_osc32byp = BIT(2),
458
+	.cr_oscsel = BIT(24),
459
+};
460
+
461
+static void __init of_sam9x60_sckc_setup(struct device_node *np)
462
+{
463
+	void __iomem *regbase = of_iomap(np, 0);
464
+	struct clk_hw_onecell_data *clk_data;
465
+	struct clk_hw *slow_rc, *slow_osc;
466
+	const char *xtal_name;
467
+	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
468
+	bool bypass;
469
+	int ret;
470
+
471
+	if (!regbase)
472
+		return;
473
+
474
+	slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
475
+							   NULL, 0, 32768,
476
+							   93750000);
477
+	if (IS_ERR(slow_rc))
478
+		return;
479
+
480
+	xtal_name = of_clk_get_parent_name(np, 0);
481
+	if (!xtal_name)
482
+		goto unregister_slow_rc;
483
+
484
+	bypass = of_property_read_bool(np, "atmel,osc-bypass");
485
+	slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
486
+					      xtal_name, 5000000, bypass,
487
+					      &at91sam9x60_bits);
488
+	if (IS_ERR(slow_osc))
489
+		goto unregister_slow_rc;
490
+
491
+	clk_data = kzalloc(struct_size(clk_data, hws, 2), GFP_KERNEL);
492
+	if (!clk_data)
493
+		goto unregister_slow_osc;
494
+
495
+	/* MD_SLCK and TD_SLCK. */
496
+	clk_data->num = 2;
497
+	clk_data->hws[0] = clk_hw_register_fixed_rate(NULL, "md_slck",
498
+						      parent_names[0],
499
+						      0, 32768);
500
+	if (IS_ERR(clk_data->hws[0]))
501
+		goto clk_data_free;
502
+
503
+	clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",
504
+							 parent_names, 2,
505
+							 &at91sam9x60_bits);
506
+	if (IS_ERR(clk_data->hws[1]))
507
+		goto unregister_md_slck;
508
+
509
+	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
510
+	if (WARN_ON(ret))
511
+		goto unregister_td_slck;
512
+
513
+	return;
514
+
515
+unregister_td_slck:
516
+	at91_clk_unregister_sam9x5_slow(clk_data->hws[1]);
517
+unregister_md_slck:
518
+	clk_hw_unregister(clk_data->hws[0]);
519
+clk_data_free:
520
+	kfree(clk_data);
521
+unregister_slow_osc:
522
+	at91_clk_unregister_slow_osc(slow_osc);
523
+unregister_slow_rc:
524
+	clk_hw_unregister(slow_rc);
525
+}
526
+CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc",
527
+	       of_sam9x60_sckc_setup);
438528 
439529 static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
440530 {
....@@ -447,7 +537,7 @@
447537 	 * Assume that if it has already been selected (for example by the
448538 	 * bootloader), enough time has aready passed.
449539 	 */
450
-	if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) {
540
+	if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {
451541 		osc->prepared = true;
452542 		return 0;
453543 	}
....@@ -473,33 +563,35 @@
473563 	.is_prepared = clk_sama5d4_slow_osc_is_prepared,
474564 };
475565 
566
+static const struct clk_slow_bits at91sama5d4_bits = {
567
+	.cr_oscsel = BIT(3),
568
+};
569
+
476570 static void __init of_sama5d4_sckc_setup(struct device_node *np)
477571 {
478572 	void __iomem *regbase = of_iomap(np, 0);
479
-	struct clk_hw *hw;
573
+	struct clk_hw *slow_rc, *slowck;
480574 	struct clk_sama5d4_slow_osc *osc;
481
-	struct clk_init_data init = {};
575
+	struct clk_init_data init;
482576 	const char *xtal_name;
483577 	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
484
-	bool bypass;
485578 	int ret;
486579 
487580 	if (!regbase)
488581 		return;
489582 
490
-	hw = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
491
-						      NULL, 0, 32768,
492
-						      250000000);
493
-	if (IS_ERR(hw))
583
+	slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL,
584
+							   parent_names[0],
585
+							   NULL, 0, 32768,
586
+							   250000000);
587
+	if (IS_ERR(slow_rc))
494588 		return;
495589 
496590 	xtal_name = of_clk_get_parent_name(np, 0);
497591 
498
-	bypass = of_property_read_bool(np, "atmel,osc-bypass");
499
-
500592 	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
501593 	if (!osc)
502
-		return;
594
+		goto unregister_slow_rc;
503595 
504596 	init.name = parent_names[1];
505597 	init.ops = &sama5d4_slow_osc_ops;
....@@ -510,22 +602,32 @@
510602 	osc->hw.init = &init;
511603 	osc->sckcr = regbase;
512604 	osc->startup_usec = 1200000;
605
+	osc->bits = &at91sama5d4_bits;
513606 
514
-	if (bypass)
515
-		writel((readl(regbase) | AT91_SCKC_OSC32BYP), regbase);
516
-
517
-	hw = &osc->hw;
518607 	ret = clk_hw_register(NULL, &osc->hw);
519
-	if (ret) {
520
-		kfree(osc);
521
-		return;
522
-	}
608
+	if (ret)
609
+		goto free_slow_osc_data;
523610 
524
-	hw = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2);
525
-	if (IS_ERR(hw))
526
-		return;
611
+	slowck = at91_clk_register_sam9x5_slow(regbase, "slowck",
612
+					       parent_names, 2,
613
+					       &at91sama5d4_bits);
614
+	if (IS_ERR(slowck))
615
+		goto unregister_slow_osc;
527616 
528
-	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
617
+	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);
618
+	if (WARN_ON(ret))
619
+		goto unregister_slowck;
620
+
621
+	return;
622
+
623
+unregister_slowck:
624
+	at91_clk_unregister_sam9x5_slow(slowck);
625
+unregister_slow_osc:
626
+	clk_hw_unregister(&osc->hw);
627
+free_slow_osc_data:
628
+	kfree(osc);
629
+unregister_slow_rc:
630
+	clk_hw_unregister(slow_rc);
529631 }
530632 CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",
531633 	       of_sama5d4_sckc_setup);