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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/clk/actions/owl-s900.c
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@@ -19,8 +19,10 @@
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 #include "owl-gate.h"
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 #include "owl-mux.h"
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 #include "owl-pll.h"
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+#include "owl-reset.h"
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 #include <dt-bindings/clock/actions,s900-cmu.h>
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+#include <dt-bindings/reset/actions,s900-reset.h>
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 #define CMU_COREPLL		(0x0000)
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 #define CMU_DEVPLL		(0x0004)
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@@ -138,7 +140,7 @@
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 static struct clk_div_table usb3_mac_div_table[] = {
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 	{ 1, 2 }, { 2, 3 }, { 3, 4 },
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-	{ 0, 8 },
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+	{ 0, 0 }
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 };
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 static struct clk_div_table i2s_div_table[] = {
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@@ -684,20 +686,100 @@
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 	.num	= CLK_NR_CLKS,
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 };
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688
 
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-static const struct owl_clk_desc s900_clk_desc = {
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+static const struct owl_reset_map s900_resets[] = {
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+	[RESET_DMAC]		= { CMU_DEVRST0, BIT(0) },
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+	[RESET_SRAMI]		= { CMU_DEVRST0, BIT(1) },
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+	[RESET_DDR_CTL_PHY]	= { CMU_DEVRST0, BIT(2) },
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+	[RESET_NANDC0]		= { CMU_DEVRST0, BIT(3) },
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+	[RESET_SD0]		= { CMU_DEVRST0, BIT(4) },
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+	[RESET_SD1]		= { CMU_DEVRST0, BIT(5) },
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+	[RESET_PCM1]		= { CMU_DEVRST0, BIT(6) },
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+	[RESET_DE]		= { CMU_DEVRST0, BIT(7) },
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+	[RESET_LVDS]		= { CMU_DEVRST0, BIT(8) },
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+	[RESET_SD2]		= { CMU_DEVRST0, BIT(9) },
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+	[RESET_DSI]		= { CMU_DEVRST0, BIT(10) },
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+	[RESET_CSI0]		= { CMU_DEVRST0, BIT(11) },
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+	[RESET_BISP_AXI]	= { CMU_DEVRST0, BIT(12) },
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+	[RESET_CSI1]		= { CMU_DEVRST0, BIT(13) },
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+	[RESET_GPIO]		= { CMU_DEVRST0, BIT(15) },
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+	[RESET_EDP]		= { CMU_DEVRST0, BIT(16) },
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+	[RESET_AUDIO]		= { CMU_DEVRST0, BIT(17) },
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+	[RESET_PCM0]		= { CMU_DEVRST0, BIT(18) },
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+	[RESET_HDE]		= { CMU_DEVRST0, BIT(21) },
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+	[RESET_GPU3D_PA]	= { CMU_DEVRST0, BIT(22) },
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+	[RESET_IMX]		= { CMU_DEVRST0, BIT(23) },
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+	[RESET_SE]		= { CMU_DEVRST0, BIT(24) },
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+	[RESET_NANDC1]		= { CMU_DEVRST0, BIT(25) },
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+	[RESET_SD3]		= { CMU_DEVRST0, BIT(26) },
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+	[RESET_GIC]		= { CMU_DEVRST0, BIT(27) },
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+	[RESET_GPU3D_PB]	= { CMU_DEVRST0, BIT(28) },
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+	[RESET_DDR_CTL_PHY_AXI]	= { CMU_DEVRST0, BIT(29) },
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+	[RESET_CMU_DDR]		= { CMU_DEVRST0, BIT(30) },
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+	[RESET_DMM]		= { CMU_DEVRST0, BIT(31) },
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+	[RESET_USB2HUB]		= { CMU_DEVRST1, BIT(0) },
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+	[RESET_USB2HSIC]	= { CMU_DEVRST1, BIT(1) },
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+	[RESET_HDMI]		= { CMU_DEVRST1, BIT(2) },
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+	[RESET_HDCP2TX]		= { CMU_DEVRST1, BIT(3) },
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+	[RESET_UART6]		= { CMU_DEVRST1, BIT(4) },
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+	[RESET_UART0]		= { CMU_DEVRST1, BIT(5) },
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+	[RESET_UART1]		= { CMU_DEVRST1, BIT(6) },
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+	[RESET_UART2]		= { CMU_DEVRST1, BIT(7) },
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+	[RESET_SPI0]		= { CMU_DEVRST1, BIT(8) },
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+	[RESET_SPI1]		= { CMU_DEVRST1, BIT(9) },
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+	[RESET_SPI2]		= { CMU_DEVRST1, BIT(10) },
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+	[RESET_SPI3]		= { CMU_DEVRST1, BIT(11) },
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+	[RESET_I2C0]		= { CMU_DEVRST1, BIT(12) },
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+	[RESET_I2C1]		= { CMU_DEVRST1, BIT(13) },
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+	[RESET_USB3]		= { CMU_DEVRST1, BIT(14) },
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+	[RESET_UART3]		= { CMU_DEVRST1, BIT(15) },
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+	[RESET_UART4]		= { CMU_DEVRST1, BIT(16) },
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+	[RESET_UART5]		= { CMU_DEVRST1, BIT(17) },
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+	[RESET_I2C2]		= { CMU_DEVRST1, BIT(18) },
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+	[RESET_I2C3]		= { CMU_DEVRST1, BIT(19) },
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+	[RESET_ETHERNET]	= { CMU_DEVRST1, BIT(20) },
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+	[RESET_CHIPID]		= { CMU_DEVRST1, BIT(21) },
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+	[RESET_I2C4]		= { CMU_DEVRST1, BIT(22) },
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+	[RESET_I2C5]		= { CMU_DEVRST1, BIT(23) },
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+	[RESET_CPU_SCNT]	= { CMU_DEVRST1, BIT(30) }
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+};
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+
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+static struct owl_clk_desc s900_clk_desc = {
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 	.clks	    = s900_clks,
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 	.num_clks   = ARRAY_SIZE(s900_clks),
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 	.hw_clks    = &s900_hw_clks,
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+
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+	.resets     = s900_resets,
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+	.num_resets = ARRAY_SIZE(s900_resets),
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 };
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 static int s900_clk_probe(struct platform_device *pdev)
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 {
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-	const struct owl_clk_desc *desc;
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+	struct owl_clk_desc *desc;
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+	struct owl_reset *reset;
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+	int ret;
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 	desc = &s900_clk_desc;
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 	owl_clk_regmap_init(pdev, desc);
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764
 
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+	/*
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+	 * FIXME: Reset controller registration should be moved to
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+	 * common code, once all SoCs of Owl family supports it.
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+	 */
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+	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
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+	if (!reset)
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+		return -ENOMEM;
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+
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+	reset->rcdev.of_node = pdev->dev.of_node;
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+	reset->rcdev.ops = &owl_reset_ops;
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+	reset->rcdev.nr_resets = desc->num_resets;
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+	reset->reset_map = desc->resets;
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+	reset->regmap = desc->regmap;
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+
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+	ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
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+	if (ret)
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+		dev_err(&pdev->dev, "Failed to register reset controller\n");
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+
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 	return owl_clk_probe(&pdev->dev, desc->hw_clks);
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 }
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