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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/drivers/ata/ahci_sunxi.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Allwinner sunxi AHCI SATA platform driver
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  * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
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@@ -6,15 +7,6 @@
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  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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  * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
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  * Daniel Wang <danielwang@allwinnertech.com>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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- * more details.
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  */
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 #include <linux/ahci_platform.h>
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@@ -157,8 +149,51 @@
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 	void __iomem *port_mmio = ahci_port_base(ap);
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 	struct ahci_host_priv *hpriv = ap->host->private_data;
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-	/* Setup DMA before DMA start */
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-	sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
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+	/* Setup DMA before DMA start
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+	 *
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+	 * NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents
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+	 *   this Vendor Specific Port (P0DMACR, aka PxDMACR) in its
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+	 *   User's Guide document (TMS320C674x/OMAP-L1x Processor
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+	 *   Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C,
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+	 *   March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR),
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+	 *   p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf)
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+	 *   as equivalent to the following struct:
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+	 *
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+	 *   struct AHCI_P0DMACR_t
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+	 *   {
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+	 *     unsigned TXTS     : 4;
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+	 *     unsigned RXTS     : 4;
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+	 *     unsigned TXABL    : 4;
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+	 *     unsigned RXABL    : 4;
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+	 *     unsigned Reserved : 16;
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+	 *   };
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+	 *
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+	 *   TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE).
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+	 *     This field defines the DMA transaction size in DWORDs for
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+	 *     transmit (system bus read, device write) operation. [...]
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+	 *
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+	 *   RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE).
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+	 *     This field defines the Port DMA transaction size in DWORDs
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+	 *     for receive (system bus write, device read) operation. [...]
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+	 *
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+	 *   TXABL: Transmit Burst Limit.
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+	 *     This field allows software to limit the VBUSP master read
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+	 *     burst size. [...]
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+	 *
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+	 *   RXABL: Receive Burst Limit.
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+	 *     Allows software to limit the VBUSP master write burst
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+	 *     size. [...]
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+	 *
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+	 *   Reserved: Reserved.
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+	 *
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+	 *
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+	 * NOTE: According to the above document, the following alternative
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+	 *   to the code below could perhaps be a better option
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+	 *   (or preparation) for possible further improvements later:
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+	 *     sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,
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+	 *		0x00000033);
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+	 */
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+	sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);
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 	/* Start DMA */
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 	sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
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@@ -181,7 +216,7 @@
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 	struct ahci_host_priv *hpriv;
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 	int rc;
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-	hpriv = ahci_platform_get_resources(pdev, 0);
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+	hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);
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 	if (IS_ERR(hpriv))
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 		return PTR_ERR(hpriv);
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@@ -250,6 +285,7 @@
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 static const struct of_device_id ahci_sunxi_of_match[] = {
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 	{ .compatible = "allwinner,sun4i-a10-ahci", },
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+	{ .compatible = "allwinner,sun8i-r40-ahci", },
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 	{ },
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 };
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 MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);