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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/x86/kernel/cpu/mtrr/generic.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
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  * because MTRRs can span up to 40 bits (36bits on most modern x86)
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@@ -14,7 +15,7 @@
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 #include <asm/tlbflush.h>
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 #include <asm/mtrr.h>
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 #include <asm/msr.h>
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-#include <asm/pat.h>
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+#include <asm/memtype.h>
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 #include "mtrr.h"
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@@ -742,7 +743,15 @@
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 	/* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
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 	cr0 = read_cr0() | X86_CR0_CD;
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 	write_cr0(cr0);
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-	wbinvd();
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+
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+	/*
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+	 * Cache flushing is the most time-consuming step when programming
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+	 * the MTRRs. Fortunately, as per the Intel Software Development
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+	 * Manual, we can skip it if the processor supports cache self-
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+	 * snooping.
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+	 */
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+	if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
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+		wbinvd();
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 	/* Save value of CR4 and clear Page Global Enable (bit 7) */
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 	if (boot_cpu_has(X86_FEATURE_PGE)) {
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@@ -752,21 +761,24 @@
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 	/* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
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 	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
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-	__flush_tlb();
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+	flush_tlb_local();
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 	/* Save MTRR state */
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 	rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
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 	/* Disable MTRRs, and set the default type to uncached */
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 	mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
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-	wbinvd();
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+
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+	/* Again, only flush caches if we have to. */
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+	if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
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+		wbinvd();
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 }
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 static void post_set(void) __releases(set_atomicity_lock)
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 {
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 	/* Flush TLBs (no need to flush caches - they are disabled) */
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 	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
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-	__flush_tlb();
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+	flush_tlb_local();
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 	/* Intel (P6) standard MTRRs */
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 	mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
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@@ -798,7 +810,7 @@
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 	local_irq_restore(flags);
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 	/* Use the atomic bitops to update the global mask */
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-	for (count = 0; count < sizeof mask * 8; ++count) {
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+	for (count = 0; count < sizeof(mask) * 8; ++count) {
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 		if (mask & 0x01)
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 			set_bit(count, &smp_changes_mask);
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 		mask >>= 1;