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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/x86/kernel/cpu/cpu.h
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@@ -14,7 +14,6 @@
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 	void		(*c_init)(struct cpuinfo_x86 *);
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 	void		(*c_identify)(struct cpuinfo_x86 *);
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 	void		(*c_detect_tlb)(struct cpuinfo_x86 *);
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-	void		(*c_bsp_resume)(struct cpuinfo_x86 *);
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 	int		c_x86_vendor;
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 #ifdef CONFIG_X86_32
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 	/* Optional vendor specific routine to obtain the cache size. */
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@@ -39,7 +38,7 @@
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 #define cpu_dev_register(cpu_devX) \
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 	static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
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-	__attribute__((__section__(".x86_cpu_dev.init"))) = \
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+	__section(".x86_cpu_dev.init") = \
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 	&cpu_devX;
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 extern const struct cpu_dev *const __x86_cpu_dev_start[],
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@@ -61,15 +60,15 @@
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 static inline void tsx_init(void) { }
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 #endif /* CONFIG_CPU_SUP_INTEL */
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+extern void init_spectral_chicken(struct cpuinfo_x86 *c);
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+
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 extern void get_cpu_cap(struct cpuinfo_x86 *c);
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 extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
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 extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
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 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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-extern u32 get_scattered_cpuid_leaf(unsigned int level,
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-				    unsigned int sub_leaf,
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-				    enum cpuid_regs_idx reg);
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 extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
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 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
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+extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
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 extern void detect_num_cpu_cores(struct cpuinfo_x86 *c);
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 extern int detect_extended_topology_early(struct cpuinfo_x86 *c);
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@@ -79,9 +78,11 @@
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 extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);
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 unsigned int aperfmperf_get_khz(int cpu);
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+void cpu_select_mitigations(void);
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 extern void x86_spec_ctrl_setup_ap(void);
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 extern void update_srbds_msr(void);
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+extern void update_gds_msr(void);
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 extern u64 x86_read_arch_cap_msr(void);
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