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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/x86/kernel/amd_nb.c
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@@ -1,6 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Shared support code for AMD K8 northbridges and derivates.
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- * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
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+ * Copyright 2006 Andi Kleen, SUSE Labs.
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  */
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6
 
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 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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@@ -17,9 +18,11 @@
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 #define PCI_DEVICE_ID_AMD_17H_ROOT	0x1450
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 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT	0x15d0
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 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT	0x1480
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+#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT	0x1630
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 #define PCI_DEVICE_ID_AMD_17H_DF_F4	0x1464
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 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
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 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
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+#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
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 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
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 #define PCI_DEVICE_ID_AMD_19H_DF_F4	0x1654
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@@ -32,13 +35,13 @@
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
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+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
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 	{}
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 };
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41
 
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-
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 #define PCI_DEVICE_ID_AMD_CNB17H_F4     0x1704
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-const struct pci_device_id amd_nb_misc_ids[] = {
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+static const struct pci_device_id amd_nb_misc_ids[] = {
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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@@ -50,12 +53,12 @@
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
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+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
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 	{}
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 };
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-EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
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62
 
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 static const struct pci_device_id amd_nb_link_ids[] = {
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
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@@ -66,9 +69,25 @@
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
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+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
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 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
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+	{}
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+};
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+
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+static const struct pci_device_id hygon_root_ids[] = {
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+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
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+	{}
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+};
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+
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+static const struct pci_device_id hygon_nb_misc_ids[] = {
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+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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+	{}
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+};
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+
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+static const struct pci_device_id hygon_nb_link_ids[] = {
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+	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
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 	{}
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 };
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@@ -205,35 +224,76 @@
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224
 
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 int amd_cache_northbridges(void)
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 {
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-	u16 i = 0;
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-	struct amd_northbridge *nb;
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+	const struct pci_device_id *misc_ids = amd_nb_misc_ids;
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+	const struct pci_device_id *link_ids = amd_nb_link_ids;
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+	const struct pci_device_id *root_ids = amd_root_ids;
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 	struct pci_dev *root, *misc, *link;
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+	struct amd_northbridge *nb;
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+	u16 roots_per_misc = 0;
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+	u16 misc_count = 0;
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+	u16 root_count = 0;
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+	u16 i, j;
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236
 
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 	if (amd_northbridges.num)
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 		return 0;
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-	misc = NULL;
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-	while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
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-		i++;
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+	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
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+		root_ids = hygon_root_ids;
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+		misc_ids = hygon_nb_misc_ids;
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+		link_ids = hygon_nb_link_ids;
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+	}
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-	if (!i)
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+	misc = NULL;
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+	while ((misc = next_northbridge(misc, misc_ids)) != NULL)
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+		misc_count++;
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+
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+	if (!misc_count)
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 		return -ENODEV;
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-	nb = kcalloc(i, sizeof(struct amd_northbridge), GFP_KERNEL);
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+	root = NULL;
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+	while ((root = next_northbridge(root, root_ids)) != NULL)
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+		root_count++;
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+
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+	if (root_count) {
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+		roots_per_misc = root_count / misc_count;
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+
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+		/*
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+		 * There should be _exactly_ N roots for each DF/SMN
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+		 * interface.
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+		 */
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+		if (!roots_per_misc || (root_count % roots_per_misc)) {
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+			pr_info("Unsupported AMD DF/PCI configuration found\n");
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+			return -ENODEV;
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+		}
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+	}
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+
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+	nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
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 	if (!nb)
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 		return -ENOMEM;
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 	amd_northbridges.nb = nb;
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-	amd_northbridges.num = i;
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+	amd_northbridges.num = misc_count;
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 	link = misc = root = NULL;
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-	for (i = 0; i != amd_northbridges.num; i++) {
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+	for (i = 0; i < amd_northbridges.num; i++) {
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 		node_to_amd_nb(i)->root = root =
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-			next_northbridge(root, amd_root_ids);
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+			next_northbridge(root, root_ids);
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 		node_to_amd_nb(i)->misc = misc =
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-			next_northbridge(misc, amd_nb_misc_ids);
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+			next_northbridge(misc, misc_ids);
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 		node_to_amd_nb(i)->link = link =
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-			next_northbridge(link, amd_nb_link_ids);
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+			next_northbridge(link, link_ids);
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+
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+		/*
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+		 * If there are more PCI root devices than data fabric/
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+		 * system management network interfaces, then the (N)
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+		 * PCI roots per DF/SMN interface are functionally the
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+		 * same (for DF/SMN access) and N-1 are redundant.  N-1
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+		 * PCI roots should be skipped per DF/SMN interface so
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+		 * the following DF/SMN interfaces get mapped to
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+		 * correct PCI roots.
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+		 */
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+		for (j = 1; j < roots_per_misc; j++)
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+			root = next_northbridge(root, root_ids);
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 	}
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 	if (amd_gart_present())
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@@ -272,11 +332,19 @@
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  */
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 bool __init early_is_amd_nb(u32 device)
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 {
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+	const struct pci_device_id *misc_ids = amd_nb_misc_ids;
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 	const struct pci_device_id *id;
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 	u32 vendor = device & 0xffff;
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338
 
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+	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
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+	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
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+		return false;
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+
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+	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
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+		misc_ids = hygon_nb_misc_ids;
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+
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 	device >>= 16;
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-	for (id = amd_nb_misc_ids; id->vendor; id++)
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+	for (id = misc_ids; id->vendor; id++)
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 		if (vendor == id->vendor && device == id->device)
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 			return true;
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 	return false;
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@@ -288,7 +356,8 @@
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 	u64 base, msr;
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 	unsigned int segn_busn_bits;
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-	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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+	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
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+	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
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 		return NULL;
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 	/* assume all cpus from fam10h have mmconfig */