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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/sh/include/asm/mmu_context.h
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@@ -8,7 +8,6 @@
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 #ifndef __ASM_SH_MMU_CONTEXT_H
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 #define __ASM_SH_MMU_CONTEXT_H
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-#ifdef __KERNEL__
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 #include <cpu/mmu_context.h>
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 #include <asm/tlbflush.h>
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 #include <linux/uaccess.h>
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@@ -48,11 +47,7 @@
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  */
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 #define MMU_VPN_MASK	0xfffff000
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-#if defined(CONFIG_SUPERH32)
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 #include <asm/mmu_context_32.h>
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-#else
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-#include <asm/mmu_context_64.h>
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-#endif
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 /*
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  * Get MMU context if needed.
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@@ -73,14 +68,6 @@
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 		 * Flush all TLB and start new cycle.
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 		 */
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 		local_flush_tlb_all();
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-
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-#ifdef CONFIG_SUPERH64
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-		/*
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-		 * The SH-5 cache uses the ASIDs, requiring both the I and D
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-		 * cache to be flushed when the ASID is exhausted. Weak.
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-		 */
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-		flush_cache_all();
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-#endif
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 		/*
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 		 * Fix version; Note that we avoid version #0
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@@ -189,5 +176,4 @@
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 #define disable_mmu()	do { } while (0)
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 #endif
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-#endif /* __KERNEL__ */
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 #endif /* __ASM_SH_MMU_CONTEXT_H */