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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/sh/include/asm/barrier.h
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@@ -6,7 +6,7 @@
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 #ifndef __ASM_SH_BARRIER_H
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 #define __ASM_SH_BARRIER_H
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-#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
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+#if defined(CONFIG_CPU_SH4A)
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 #include <asm/cache_insns.h>
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 #endif
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@@ -24,7 +24,7 @@
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  * Historically we have only done this type of barrier for the MMUCR, but
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  * it's also necessary for the CCR, so we make it generic here instead.
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  */
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-#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
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+#if defined(CONFIG_CPU_SH4A)
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 #define mb()		__asm__ __volatile__ ("synco": : :"memory")
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 #define rmb()		mb()
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 #define wmb()		mb()