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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/powerpc/include/uapi/asm/kvm.h
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@@ -463,10 +463,12 @@
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 #define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED	(1ULL << 58)
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 #define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF	(1ULL << 57)
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 #define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS	(1ULL << 56)
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+#define KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST	(1ull << 54)
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 #define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY	(1ULL << 63)
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 #define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR		(1ULL << 62)
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 #define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR	(1ULL << 61)
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+#define KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE	(1ull << 58)
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 /* Per-vcpu XICS interrupt controller state */
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 #define KVM_REG_PPC_ICP_STATE	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
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@@ -479,6 +481,8 @@
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 #define  KVM_REG_PPC_ICP_MFRR_MASK	0xff
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 #define  KVM_REG_PPC_ICP_PPRI_SHIFT	16	/* pending irq priority */
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 #define  KVM_REG_PPC_ICP_PPRI_MASK	0xff
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+
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+#define KVM_REG_PPC_VP_STATE	(KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x8d)
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 /* Device control API: PPC-specific devices */
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 #define KVM_DEV_MPIC_GRP_MISC		1
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@@ -634,6 +638,12 @@
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 #define KVM_REG_PPC_DEC_EXPIRY	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
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 #define KVM_REG_PPC_ONLINE	(KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
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+#define KVM_REG_PPC_PTCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0)
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+
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+/* POWER10 registers */
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+#define KVM_REG_PPC_MMCR3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc1)
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+#define KVM_REG_PPC_SIER2	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc2)
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+#define KVM_REG_PPC_SIER3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)
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 /* Transactional Memory checkpointed state:
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  * This is all GPRs, all VSX regs and a subset of SPRs
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@@ -662,6 +672,8 @@
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 /* PPC64 eXternal Interrupt Controller Specification */
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 #define KVM_DEV_XICS_GRP_SOURCES	1	/* 64-bit source attributes */
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+#define KVM_DEV_XICS_GRP_CTRL		2
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+#define   KVM_DEV_XICS_NR_SERVERS	1
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 /* Layout of 64-bit source attribute values */
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 #define  KVM_XICS_DESTINATION_SHIFT	0
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@@ -674,4 +686,49 @@
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 #define  KVM_XICS_PRESENTED		(1ULL << 43)
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 #define  KVM_XICS_QUEUED		(1ULL << 44)
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688
 
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+/* POWER9 XIVE Native Interrupt Controller */
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+#define KVM_DEV_XIVE_GRP_CTRL		1
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+#define   KVM_DEV_XIVE_RESET		1
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+#define   KVM_DEV_XIVE_EQ_SYNC		2
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+#define   KVM_DEV_XIVE_NR_SERVERS	3
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+#define KVM_DEV_XIVE_GRP_SOURCE		2	/* 64-bit source identifier */
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+#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG	3	/* 64-bit source identifier */
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+#define KVM_DEV_XIVE_GRP_EQ_CONFIG	4	/* 64-bit EQ identifier */
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+#define KVM_DEV_XIVE_GRP_SOURCE_SYNC	5       /* 64-bit source identifier */
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+
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+/* Layout of 64-bit XIVE source attribute values */
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+#define KVM_XIVE_LEVEL_SENSITIVE	(1ULL << 0)
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+#define KVM_XIVE_LEVEL_ASSERTED		(1ULL << 1)
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+
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+/* Layout of 64-bit XIVE source configuration attribute values */
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+#define KVM_XIVE_SOURCE_PRIORITY_SHIFT	0
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+#define KVM_XIVE_SOURCE_PRIORITY_MASK	0x7
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+#define KVM_XIVE_SOURCE_SERVER_SHIFT	3
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+#define KVM_XIVE_SOURCE_SERVER_MASK	0xfffffff8ULL
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+#define KVM_XIVE_SOURCE_MASKED_SHIFT	32
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+#define KVM_XIVE_SOURCE_MASKED_MASK	0x100000000ULL
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+#define KVM_XIVE_SOURCE_EISN_SHIFT	33
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+#define KVM_XIVE_SOURCE_EISN_MASK	0xfffffffe00000000ULL
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+
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+/* Layout of 64-bit EQ identifier */
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+#define KVM_XIVE_EQ_PRIORITY_SHIFT	0
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+#define KVM_XIVE_EQ_PRIORITY_MASK	0x7
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+#define KVM_XIVE_EQ_SERVER_SHIFT	3
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+#define KVM_XIVE_EQ_SERVER_MASK		0xfffffff8ULL
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+
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+/* Layout of EQ configuration values (64 bytes) */
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+struct kvm_ppc_xive_eq {
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+	__u32 flags;
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+	__u32 qshift;
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+	__u64 qaddr;
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+	__u32 qtoggle;
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+	__u32 qindex;
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+	__u8  pad[40];
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+};
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+
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+#define KVM_XIVE_EQ_ALWAYS_NOTIFY	0x00000001
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+
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+#define KVM_XIVE_TIMA_PAGE_OFFSET	0
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+#define KVM_XIVE_ESB_PAGE_OFFSET	4
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+
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 #endif /* __LINUX_KVM_POWERPC_H */