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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/powerpc/include/asm/synch.h
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@@ -3,8 +3,9 @@
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 #define _ASM_POWERPC_SYNCH_H 
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 #ifdef __KERNEL__
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+#include <asm/cputable.h>
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 #include <asm/feature-fixups.h>
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-#include <asm/asm-const.h>
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+#include <asm/ppc-opcode.h>
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 #ifndef __ASSEMBLY__
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 extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
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@@ -20,6 +21,22 @@
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 {
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 	__asm__ __volatile__ ("isync" : : : "memory");
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 }
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+
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+static inline void ppc_after_tlbiel_barrier(void)
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+{
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+	asm volatile("ptesync": : :"memory");
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+	/*
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+	 * POWER9, POWER10 need a cp_abort after tlbiel to ensure the copy is
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+	 * invalidated correctly. If this is not done, the paste can take data
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+	 * from the physical address that was translated at copy time.
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+	 *
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+	 * POWER9 in practice does not need this, because address spaces with
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+	 * accelerators mapped will use tlbie (which does invalidate the copy)
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+	 * to invalidate translations. It's not possible to limit POWER10 this
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+	 * way due to local copy-paste.
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+	 */
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+	asm volatile(ASM_FTR_IFSET(PPC_CP_ABORT, "", %0) : : "i" (CPU_FTR_ARCH_31) : "memory");
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+}
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 #endif /* __ASSEMBLY__ */
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 #if defined(__powerpc64__)