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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/powerpc/include/asm/sstep.h
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@@ -1,11 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  */
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+#include <asm/inst.h>
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 struct pt_regs;
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8
 
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@@ -19,9 +16,9 @@
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  * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
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  * and an mtmsrd (64-bit).
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  */
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-#define IS_MTMSRD(instr)	(((instr) & 0xfc0007be) == 0x7c000124)
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-#define IS_RFID(instr)		(((instr) & 0xfc0007fe) == 0x4c000024)
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-#define IS_RFI(instr)		(((instr) & 0xfc0007fe) == 0x4c000064)
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+#define IS_MTMSRD(instr)	((ppc_inst_val(instr) & 0xfc0007be) == 0x7c000124)
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+#define IS_RFID(instr)		((ppc_inst_val(instr) & 0xfc0007fe) == 0x4c000024)
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+#define IS_RFI(instr)		((ppc_inst_val(instr) & 0xfc0007fe) == 0x4c000064)
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 enum instruction_type {
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 	COMPUTE,		/* arith/logical/CR op, etc. */
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@@ -43,6 +40,7 @@
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 	CACHEOP,
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 	BARRIER,
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 	SYSCALL,
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+	SYSCALL_VECTORED_0,
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 	MFMSR,
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 	MTMSR,
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 	RFI,
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@@ -52,6 +50,8 @@
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 #define INSTR_TYPE_MASK	0x1f
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+#define OP_IS_LOAD(type)	((LOAD <= (type) && (type) <= LOAD_VSX) || (type) == LARX)
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+#define OP_IS_STORE(type)	((STORE <= (type) && (type) <= STORE_VSX) || (type) == STCX)
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 #define OP_IS_LOAD_STORE(type)	(LOAD <= (type) && (type) <= STCX)
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 /* Compute flags, ORed in with type */
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@@ -93,13 +93,23 @@
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 #define VSX_LDLEFT	4	/* load VSX register from left */
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 #define VSX_CHECK_VEC	8	/* check MSR_VEC not MSR_VSX for reg >= 32 */
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+/* Prefixed flag, ORed in with type */
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+#define PREFIXED       0x800
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+
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 /* Size field in type word */
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 #define SIZE(n)		((n) << 12)
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 #define GETSIZE(w)	((w) >> 12)
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 #define GETTYPE(t)	((t) & INSTR_TYPE_MASK)
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+#define GETLENGTH(t)   (((t) & PREFIXED) ? 8 : 4)
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 #define MKOP(t, f, s)	((t) | (f) | SIZE(s))
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+
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+/* Prefix instruction operands */
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+#define GET_PREFIX_RA(i)	(((i) >> 16) & 0x1f)
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+#define GET_PREFIX_R(i)		((i) & (1ul << 20))
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+
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+extern s32 patch__exec_instr;
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 struct instruction_op {
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 	int type;
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@@ -136,7 +146,7 @@
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  * otherwise.
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  */
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 extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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-			 unsigned int instr);
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+			 struct ppc_inst instr);
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 /*
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  * Emulate an instruction that can be executed just by updating
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@@ -153,7 +163,7 @@
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  * 0 if it could not be emulated, or -1 for an instruction that
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  * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
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  */
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-extern int emulate_step(struct pt_regs *regs, unsigned int instr);
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+extern int emulate_step(struct pt_regs *regs, struct ppc_inst instr);
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 /*
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  * Emulate a load or store instruction by reading/writing the