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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/powerpc/include/asm/bitops.h
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * PowerPC atomic bit operations.
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  *
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@@ -26,11 +27,6 @@
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  * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
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  * number field needs to be reversed compared to the big-endian bit
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  * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  */
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 #ifndef _ASM_POWERPC_BITOPS_H
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@@ -45,7 +41,6 @@
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 #include <linux/compiler.h>
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 #include <asm/asm-compat.h>
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 #include <asm/synch.h>
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-#include <asm/asm-405.h>
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 /* PPC bit number conversion */
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 #define PPC_BITLSHIFT(be)	(BITS_PER_LONG - 1 - (be))
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@@ -68,7 +63,7 @@
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 /* Macro for generating the ***_bits() functions */
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 #define DEFINE_BITOP(fn, op, prefix)		\
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-static __inline__ void fn(unsigned long mask,	\
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+static inline void fn(unsigned long mask,	\
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 		volatile unsigned long *_p)	\
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 {						\
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 	unsigned long old;			\
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@@ -77,7 +72,6 @@
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 	prefix					\
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 "1:"	PPC_LLARX(%0,0,%3,0) "\n"		\
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 	stringify_in_c(op) "%0,%0,%2\n"		\
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-	PPC405_ERR77(0,%3)			\
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 	PPC_STLCX "%0,0,%3\n"			\
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 	"bne- 1b\n"				\
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 	: "=&r" (old), "+m" (*p)		\
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@@ -90,22 +84,22 @@
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 DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER)
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 DEFINE_BITOP(change_bits, xor, "")
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-static __inline__ void set_bit(int nr, volatile unsigned long *addr)
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+static inline void arch_set_bit(int nr, volatile unsigned long *addr)
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 {
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 	set_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
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 }
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-static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
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+static inline void arch_clear_bit(int nr, volatile unsigned long *addr)
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 {
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 	clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
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 }
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-static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
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+static inline void arch_clear_bit_unlock(int nr, volatile unsigned long *addr)
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 {
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 	clear_bits_unlock(BIT_MASK(nr), addr + BIT_WORD(nr));
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 }
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-static __inline__ void change_bit(int nr, volatile unsigned long *addr)
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+static inline void arch_change_bit(int nr, volatile unsigned long *addr)
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 {
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 	change_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
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 }
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@@ -113,7 +107,7 @@
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 /* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
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  * operands. */
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 #define DEFINE_TESTOP(fn, op, prefix, postfix, eh)	\
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-static __inline__ unsigned long fn(			\
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+static inline unsigned long fn(			\
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 		unsigned long mask,			\
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 		volatile unsigned long *_p)		\
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 {							\
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@@ -123,7 +117,6 @@
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 	prefix						\
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 "1:"	PPC_LLARX(%0,0,%3,eh) "\n"			\
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 	stringify_in_c(op) "%1,%0,%2\n"			\
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-	PPC405_ERR77(0,%3)				\
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 	PPC_STLCX "%1,0,%3\n"				\
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 	"bne- 1b\n"					\
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 	postfix						\
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@@ -142,34 +135,34 @@
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 DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER,
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 	      PPC_ATOMIC_EXIT_BARRIER, 0)
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-static __inline__ int test_and_set_bit(unsigned long nr,
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-				       volatile unsigned long *addr)
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+static inline int arch_test_and_set_bit(unsigned long nr,
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+					volatile unsigned long *addr)
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 {
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 	return test_and_set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
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 }
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-static __inline__ int test_and_set_bit_lock(unsigned long nr,
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-				       volatile unsigned long *addr)
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+static inline int arch_test_and_set_bit_lock(unsigned long nr,
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+					     volatile unsigned long *addr)
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 {
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 	return test_and_set_bits_lock(BIT_MASK(nr),
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 				addr + BIT_WORD(nr)) != 0;
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 }
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-static __inline__ int test_and_clear_bit(unsigned long nr,
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-					 volatile unsigned long *addr)
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+static inline int arch_test_and_clear_bit(unsigned long nr,
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+					  volatile unsigned long *addr)
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 {
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 	return test_and_clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
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 }
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-static __inline__ int test_and_change_bit(unsigned long nr,
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-					  volatile unsigned long *addr)
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+static inline int arch_test_and_change_bit(unsigned long nr,
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+					   volatile unsigned long *addr)
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 {
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 	return test_and_change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
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 }
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 #ifdef CONFIG_PPC64
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-static __inline__ unsigned long clear_bit_unlock_return_word(int nr,
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-						volatile unsigned long *addr)
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+static inline unsigned long
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+clear_bit_unlock_return_word(int nr, volatile unsigned long *addr)
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 {
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 	unsigned long old, t;
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 	unsigned long *p = (unsigned long *)addr + BIT_WORD(nr);
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@@ -179,7 +172,6 @@
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 	PPC_RELEASE_BARRIER
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 "1:"	PPC_LLARX(%0,0,%3,0) "\n"
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 	"andc %1,%0,%2\n"
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-	PPC405_ERR77(0,%3)
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 	PPC_STLCX "%1,0,%3\n"
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 	"bne- 1b\n"
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 	: "=&r" (old), "=&r" (t)
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@@ -189,15 +181,18 @@
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 	return old;
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 }
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-/* This is a special function for mm/filemap.c */
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-#define clear_bit_unlock_is_negative_byte(nr, addr)			\
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-	(clear_bit_unlock_return_word(nr, addr) & BIT_MASK(PG_waiters))
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+/*
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+ * This is a special function for mm/filemap.c
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+ * Bit 7 corresponds to PG_waiters.
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+ */
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+#define arch_clear_bit_unlock_is_negative_byte(nr, addr)		\
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+	(clear_bit_unlock_return_word(nr, addr) & BIT_MASK(7))
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 #endif /* CONFIG_PPC64 */
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 #include <asm-generic/bitops/non-atomic.h>
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-static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
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+static inline void arch___clear_bit_unlock(int nr, volatile unsigned long *addr)
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 {
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 	__asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
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 	__clear_bit(nr, addr);
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@@ -219,7 +214,7 @@
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  * fls: find last (most-significant) bit set.
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  * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
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  */
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-static __inline__ int fls(unsigned int x)
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+static inline int fls(unsigned int x)
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 {
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 	int lz;
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@@ -237,7 +232,7 @@
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  * 32-bit fls calls.
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  */
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 #ifdef CONFIG_PPC64
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-static __inline__ int fls64(__u64 x)
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+static inline int fls64(__u64 x)
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 {
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 	int lz;
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@@ -262,6 +257,10 @@
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 #include <asm-generic/bitops/find.h>
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+/* wrappers that deal with KASAN instrumentation */
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+#include <asm-generic/bitops/instrumented-atomic.h>
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+#include <asm-generic/bitops/instrumented-lock.h>
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+
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 /* Little-endian versions */
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 #include <asm-generic/bitops/le.h>
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