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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/m68k/include/asm/m5441xsim.h
..
..
@@ -279,9 +279,39 @@
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 #define MCFGPIO_PIN_MAX		87
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 /*
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+ * Phase Locked Loop (PLL)
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+ */
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+#define MCF_PLL_CR		0xFC0C0000
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+#define MCF_PLL_DR		0xFC0C0004
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+#define MCF_PLL_SR		0xFC0C0008
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+
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+/*
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  *  DSPI module.
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  */
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 #define MCFDSPI_BASE0		0xfc05c000
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+#define MCFDSPI_BASE1		0xfC03c000
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 #define MCF_IRQ_DSPI0		(MCFINT0_VECBASE + MCFINT0_DSPI0)
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+#define MCF_IRQ_DSPI1		(MCFINT1_VECBASE + MCFINT1_DSPI1)
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+/*
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+ *  eDMA module.
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+ */
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+#define MCFEDMA_BASE		0xfc044000
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+#define MCFEDMA_SIZE		0x4000
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+#define MCFINT0_EDMA_INTR0	8
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+#define MCFINT0_EDMA_ERR	24
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+#define MCFEDMA_EDMA_INTR16	8
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+#define MCFEDMA_EDMA_INTR56	0
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+#define MCFEDMA_IRQ_INTR0	(MCFINT0_VECBASE + MCFINT0_EDMA_INTR0)
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+#define MCFEDMA_IRQ_INTR16	(MCFINT1_VECBASE + MCFEDMA_EDMA_INTR16)
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+#define MCFEDMA_IRQ_INTR56	(MCFINT2_VECBASE + MCFEDMA_EDMA_INTR56)
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+#define MCFEDMA_IRQ_ERR	(MCFINT0_VECBASE + MCFINT0_EDMA_ERR)
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+/*
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+ *  esdhc module.
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+ */
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+#define MCFSDHC_BASE		0xfc0cc000
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+#define MCFSDHC_SIZE		256
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+#define MCFINT2_SDHC		31
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+#define MCF_IRQ_SDHC		(MCFINT2_VECBASE + MCFINT2_SDHC)
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+#define MCFSDHC_CLK		(MCFSDHC_BASE + 0x2c)
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 #endif /* m5441xsim_h */