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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/m68k/coldfire/device.c
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@@ -14,11 +14,15 @@
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 #include <linux/spi/spi.h>
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 #include <linux/gpio.h>
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 #include <linux/fec.h>
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+#include <linux/dmaengine.h>
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 #include <asm/traps.h>
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 #include <asm/coldfire.h>
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 #include <asm/mcfsim.h>
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 #include <asm/mcfuart.h>
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 #include <asm/mcfqspi.h>
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+#include <linux/platform_data/edma.h>
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+#include <linux/platform_data/dma-mcf-edma.h>
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+#include <linux/platform_data/mmc-esdhc-mcf.h>
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 /*
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  *	All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
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@@ -476,6 +480,107 @@
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 #endif /* MCFI2C_BASE5 */
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 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
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+#ifdef MCFEDMA_BASE
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+
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+static const struct dma_slave_map mcf_edma_map[] = {
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+	{ "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) },
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+	{ "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) },
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+	{ "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) },
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+	{ "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) },
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+	{ "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) },
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+	{ "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) },
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+	{ "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) },
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+	{ "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) },
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+	{ "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) },
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+	{ "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) },
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+	{ "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) },
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+	{ "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) },
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+	{ "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) },
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+	{ "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) },
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+	{ "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) },
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+	{ "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) },
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+};
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+
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+static struct mcf_edma_platform_data mcf_edma_data = {
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+	.dma_channels		= 64,
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+	.slave_map		= mcf_edma_map,
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+	.slavecnt		= ARRAY_SIZE(mcf_edma_map),
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+};
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+
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+static struct resource mcf_edma_resources[] = {
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+	{
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+		.start		= MCFEDMA_BASE,
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+		.end		= MCFEDMA_BASE + MCFEDMA_SIZE - 1,
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+		.flags		= IORESOURCE_MEM,
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+	},
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+	{
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+		.start		= MCFEDMA_IRQ_INTR0,
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+		.end		= MCFEDMA_IRQ_INTR0 + 15,
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+		.flags		= IORESOURCE_IRQ,
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+		.name		= "edma-tx-00-15",
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+	},
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+	{
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+		.start		= MCFEDMA_IRQ_INTR16,
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+		.end		= MCFEDMA_IRQ_INTR16 + 39,
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+		.flags		= IORESOURCE_IRQ,
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+		.name		= "edma-tx-16-55",
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+	},
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+	{
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+		.start		= MCFEDMA_IRQ_INTR56,
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+		.end		= MCFEDMA_IRQ_INTR56,
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+		.flags		= IORESOURCE_IRQ,
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+		.name		= "edma-tx-56-63",
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+	},
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+	{
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+		.start		= MCFEDMA_IRQ_ERR,
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+		.end		= MCFEDMA_IRQ_ERR,
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+		.flags		= IORESOURCE_IRQ,
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+		.name		= "edma-err",
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+	},
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+};
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+
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+static u64 mcf_edma_dmamask = DMA_BIT_MASK(32);
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+
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+static struct platform_device mcf_edma = {
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+	.name			= "mcf-edma",
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+	.id			= 0,
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+	.num_resources		= ARRAY_SIZE(mcf_edma_resources),
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+	.resource		= mcf_edma_resources,
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+	.dev = {
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+		.dma_mask = &mcf_edma_dmamask,
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+		.coherent_dma_mask = DMA_BIT_MASK(32),
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+		.platform_data = &mcf_edma_data,
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+	}
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+};
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+#endif /* MCFEDMA_BASE */
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+
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+#ifdef MCFSDHC_BASE
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+static struct mcf_esdhc_platform_data mcf_esdhc_data = {
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+	.max_bus_width = 4,
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+	.cd_type = ESDHC_CD_NONE,
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+};
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+
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+static struct resource mcf_esdhc_resources[] = {
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+	{
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+		.start = MCFSDHC_BASE,
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+		.end = MCFSDHC_BASE + MCFSDHC_SIZE - 1,
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+		.flags = IORESOURCE_MEM,
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+	}, {
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+		.start = MCF_IRQ_SDHC,
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+		.end = MCF_IRQ_SDHC,
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+		.flags = IORESOURCE_IRQ,
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+	},
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+};
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+
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+static struct platform_device mcf_esdhc = {
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+	.name			= "sdhci-esdhc-mcf",
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+	.id			= 0,
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+	.num_resources		= ARRAY_SIZE(mcf_esdhc_resources),
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+	.resource		= mcf_esdhc_resources,
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+	.dev.platform_data	= &mcf_esdhc_data,
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+};
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+#endif /* MCFSDHC_BASE */
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+
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 static struct platform_device *mcf_devices[] __initdata = {
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 	&mcf_uart,
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 #if IS_ENABLED(CONFIG_FEC)
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@@ -505,6 +610,12 @@
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 	&mcf_i2c5,
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 #endif
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 #endif
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+#ifdef MCFEDMA_BASE
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+	&mcf_edma,
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+#endif
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+#ifdef MCFSDHC_BASE
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+	&mcf_esdhc,
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+#endif
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 };
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 /*
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@@ -533,4 +644,3 @@
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 }
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 arch_initcall(mcf_init_devices);
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-