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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/ia64/include/asm/tlbflush.h
..
..
@@ -14,6 +14,31 @@
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 #include <asm/mmu_context.h>
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 #include <asm/page.h>
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+struct ia64_tr_entry {
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+	u64 ifa;
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+	u64 itir;
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+	u64 pte;
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+	u64 rr;
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+}; /*Record for tr entry!*/
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+
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+extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
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+extern void ia64_ptr_entry(u64 target_mask, int slot);
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+extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
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+
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+/*
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+ region register macros
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+*/
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+#define RR_TO_VE(val)   (((val) >> 0) & 0x0000000000000001)
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+#define RR_VE(val)     (((val) & 0x0000000000000001) << 0)
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+#define RR_VE_MASK     0x0000000000000001L
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+#define RR_VE_SHIFT    0
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+#define RR_TO_PS(val)  (((val) >> 2) & 0x000000000000003f)
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+#define RR_PS(val)     (((val) & 0x000000000000003f) << 2)
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+#define RR_PS_MASK     0x00000000000000fcL
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+#define RR_PS_SHIFT    2
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+#define RR_RID_MASK    0x00000000ffffff00L
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+#define RR_TO_RID(val)         ((val >> 8) & 0xffffff)
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+
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 /*
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  * Now for some TLB flushing routines.  This is the kind of stuff that
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  * can be very expensive, so try to avoid them whenever possible.