forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/arch/arm64/boot/dts/exynos/exynos5433.dtsi
....@@ -23,13 +23,38 @@
2323 
2424 	interrupt-parent = <&gic>;
2525 
26
+	arm_a53_pmu {
27
+		compatible = "arm,cortex-a53-pmu";
28
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
29
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
30
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
31
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
32
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
33
+	};
34
+
35
+	arm_a57_pmu {
36
+		compatible = "arm,cortex-a57-pmu";
37
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
38
+			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
39
+			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
40
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
41
+		interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
42
+	};
43
+
44
+	xxti: clock {
45
+		/* XXTI */
46
+		compatible = "fixed-clock";
47
+		clock-output-names = "oscclk";
48
+		#clock-cells = <0>;
49
+	};
50
+
2651 	cpus {
2752 		#address-cells = <1>;
2853 		#size-cells = <0>;
2954 
3055 		cpu0: cpu@100 {
3156 			device_type = "cpu";
32
-			compatible = "arm,cortex-a53", "arm,armv8";
57
+			compatible = "arm,cortex-a53";
3358 			enable-method = "psci";
3459 			reg = <0x100>;
3560 			clock-frequency = <1300000000>;
....@@ -41,7 +66,7 @@
4166 
4267 		cpu1: cpu@101 {
4368 			device_type = "cpu";
44
-			compatible = "arm,cortex-a53", "arm,armv8";
69
+			compatible = "arm,cortex-a53";
4570 			enable-method = "psci";
4671 			reg = <0x101>;
4772 			clock-frequency = <1300000000>;
....@@ -51,7 +76,7 @@
5176 
5277 		cpu2: cpu@102 {
5378 			device_type = "cpu";
54
-			compatible = "arm,cortex-a53", "arm,armv8";
79
+			compatible = "arm,cortex-a53";
5580 			enable-method = "psci";
5681 			reg = <0x102>;
5782 			clock-frequency = <1300000000>;
....@@ -61,7 +86,7 @@
6186 
6287 		cpu3: cpu@103 {
6388 			device_type = "cpu";
64
-			compatible = "arm,cortex-a53", "arm,armv8";
89
+			compatible = "arm,cortex-a53";
6590 			enable-method = "psci";
6691 			reg = <0x103>;
6792 			clock-frequency = <1300000000>;
....@@ -71,7 +96,7 @@
7196 
7297 		cpu4: cpu@0 {
7398 			device_type = "cpu";
74
-			compatible = "arm,cortex-a57", "arm,armv8";
99
+			compatible = "arm,cortex-a57";
75100 			enable-method = "psci";
76101 			reg = <0x0>;
77102 			clock-frequency = <1900000000>;
....@@ -83,7 +108,7 @@
83108 
84109 		cpu5: cpu@1 {
85110 			device_type = "cpu";
86
-			compatible = "arm,cortex-a57", "arm,armv8";
111
+			compatible = "arm,cortex-a57";
87112 			enable-method = "psci";
88113 			reg = <0x1>;
89114 			clock-frequency = <1900000000>;
....@@ -93,7 +118,7 @@
93118 
94119 		cpu6: cpu@2 {
95120 			device_type = "cpu";
96
-			compatible = "arm,cortex-a57", "arm,armv8";
121
+			compatible = "arm,cortex-a57";
97122 			enable-method = "psci";
98123 			reg = <0x2>;
99124 			clock-frequency = <1900000000>;
....@@ -103,7 +128,7 @@
103128 
104129 		cpu7: cpu@3 {
105130 			device_type = "cpu";
106
-			compatible = "arm,cortex-a57", "arm,armv8";
131
+			compatible = "arm,cortex-a57";
107132 			enable-method = "psci";
108133 			reg = <0x3>;
109134 			clock-frequency = <1900000000>;
....@@ -231,39 +256,15 @@
231256 		cpu_on = <0xC4000003>;
232257 	};
233258 
234
-	soc: soc {
259
+	soc: soc@0 {
235260 		compatible = "simple-bus";
236261 		#address-cells = <1>;
237262 		#size-cells = <1>;
238263 		ranges = <0x0 0x0 0x0 0x18000000>;
239264 
240
-		arm_a53_pmu {
241
-			compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
242
-			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
243
-				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
244
-				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
245
-				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
246
-			interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
247
-		};
248
-
249
-		arm_a57_pmu {
250
-			compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
251
-			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
252
-				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
253
-				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
254
-				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
255
-			interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
256
-		};
257
-
258265 		chipid@10000000 {
259266 			compatible = "samsung,exynos4210-chipid";
260267 			reg = <0x10000000 0x100>;
261
-		};
262
-
263
-		xxti: xxti {
264
-			compatible = "fixed-clock";
265
-			clock-output-names = "oscclk";
266
-			#clock-cells = <0>;
267268 		};
268269 
269270 		cmu_top: clock-controller@10030000 {
....@@ -544,6 +545,30 @@
544545 			power-domains = <&pd_cam1>;
545546 		};
546547 
548
+		cmu_imem: clock-controller@11060000 {
549
+			compatible = "samsung,exynos5433-cmu-imem";
550
+			reg = <0x11060000 0x1000>;
551
+			#clock-cells = <1>;
552
+
553
+			clock-names = "oscclk",
554
+				"aclk_imem_sssx_266",
555
+				"aclk_imem_266",
556
+				"aclk_imem_200";
557
+			clocks = <&xxti>,
558
+				<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
559
+				<&cmu_top CLK_DIV_ACLK_IMEM_266>,
560
+				<&cmu_top CLK_DIV_ACLK_IMEM_200>;
561
+		};
562
+
563
+		slim_sss: slim-sss@11140000 {
564
+			compatible = "samsung,exynos5433-slim-sss";
565
+			reg = <0x11140000 0x1000>;
566
+			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
567
+			clock-names = "aclk", "pclk";
568
+			clocks = <&cmu_imem CLK_ACLK_SLIMSSS>,
569
+				 <&cmu_imem CLK_PCLK_SLIMSSS>;
570
+		};
571
+
547572 		pd_gscl: power-domain@105c4000 {
548573 			compatible = "samsung,exynos5433-pd";
549574 			reg = <0x105c4000 0x20>;
....@@ -678,7 +703,7 @@
678703 			status = "disabled";
679704 		};
680705 
681
-		mct@101c0000 {
706
+		timer@101c0000 {
682707 			compatible = "samsung,exynos4210-mct";
683708 			reg = <0x101c0000 0x800>;
684709 			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
....@@ -833,12 +858,13 @@
833858 				<&cmu_disp CLK_ACLK_XIU_DECON1X>,
834859 				<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
835860 				<&cmu_disp CLK_SCLK_DECON_VCLK>,
836
-				<&cmu_disp CLK_SCLK_DECON_ECLK>;
861
+				<&cmu_disp CLK_SCLK_DECON_ECLK>,
862
+				<&cmu_disp CLK_SCLK_DSD>;
837863 			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
838864 				"aclk_xiu_decon0x", "pclk_smmu_decon0x",
839865 				"aclk_smmu_decon1x", "aclk_xiu_decon1x",
840866 				"pclk_smmu_decon1x", "sclk_decon_vclk",
841
-				"sclk_decon_eclk";
867
+				"sclk_decon_eclk", "dsd";
842868 			power-domains = <&pd_disp>;
843869 			interrupt-names = "fifo", "vsync", "lcd_sys";
844870 			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
....@@ -875,12 +901,13 @@
875901 				 <&cmu_disp CLK_ACLK_XIU_TV1X>,
876902 				 <&cmu_disp CLK_PCLK_SMMU_TV1X>,
877903 				 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
878
-				 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
904
+				 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>,
905
+				 <&cmu_disp CLK_SCLK_DSD>;
879906 			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
880907 				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
881908 				      "aclk_smmu_decon1x", "aclk_xiu_decon1x",
882909 				      "pclk_smmu_decon1x", "sclk_decon_vclk",
883
-				      "sclk_decon_eclk";
910
+				      "sclk_decon_eclk", "dsd";
884911 			samsung,disp-sysreg = <&syscon_disp>;
885912 			power-domains = <&pd_disp>;
886913 			interrupt-names = "fifo", "vsync", "lcd_sys";
....@@ -988,17 +1015,17 @@
9881015 		};
9891016 
9901017 		syscon_disp: syscon@13b80000 {
991
-			compatible = "syscon";
1018
+			compatible = "samsung,exynos5433-sysreg", "syscon";
9921019 			reg = <0x13b80000 0x1010>;
9931020 		};
9941021 
9951022 		syscon_cam0: syscon@120f0000 {
996
-			compatible = "syscon";
1023
+			compatible = "samsung,exynos5433-sysreg", "syscon";
9971024 			reg = <0x120f0000 0x1020>;
9981025 		};
9991026 
10001027 		syscon_cam1: syscon@145f0000 {
1001
-			compatible = "syscon";
1028
+			compatible = "samsung,exynos5433-sysreg", "syscon";
10021029 			reg = <0x145f0000 0x1038>;
10031030 		};
10041031 
....@@ -1007,11 +1034,12 @@
10071034 			reg = <0x13c00000 0x1000>;
10081035 			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
10091036 			clock-names = "pclk", "aclk", "aclk_xiu",
1010
-				      "aclk_gsclbend";
1037
+				      "aclk_gsclbend", "gsd";
10111038 			clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
10121039 				 <&cmu_gscl CLK_ACLK_GSCL0>,
10131040 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1014
-				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1041
+				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1042
+				 <&cmu_gscl CLK_ACLK_GSD>;
10151043 			iommus = <&sysmmu_gscl0>;
10161044 			power-domains = <&pd_gscl>;
10171045 		};
....@@ -1021,11 +1049,12 @@
10211049 			reg = <0x13c10000 0x1000>;
10221050 			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
10231051 			clock-names = "pclk", "aclk", "aclk_xiu",
1024
-				      "aclk_gsclbend";
1052
+				      "aclk_gsclbend", "gsd";
10251053 			clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
10261054 				 <&cmu_gscl CLK_ACLK_GSCL1>,
10271055 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1028
-				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1056
+				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1057
+				 <&cmu_gscl CLK_ACLK_GSD>;
10291058 			iommus = <&sysmmu_gscl1>;
10301059 			power-domains = <&pd_gscl>;
10311060 		};
....@@ -1035,13 +1064,65 @@
10351064 			reg = <0x13c20000 0x1000>;
10361065 			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
10371066 			clock-names = "pclk", "aclk", "aclk_xiu",
1038
-				      "aclk_gsclbend";
1067
+				      "aclk_gsclbend", "gsd";
10391068 			clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
10401069 				 <&cmu_gscl CLK_ACLK_GSCL2>,
10411070 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1042
-				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1071
+				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>,
1072
+				 <&cmu_gscl CLK_ACLK_GSD>;
10431073 			iommus = <&sysmmu_gscl2>;
10441074 			power-domains = <&pd_gscl>;
1075
+		};
1076
+
1077
+		gpu: gpu@14ac0000 {
1078
+			compatible = "samsung,exynos5433-mali", "arm,mali-t760";
1079
+			reg = <0x14ac0000 0x5000>;
1080
+			interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1081
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1082
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
1083
+			interrupt-names = "job", "mmu", "gpu";
1084
+			clocks = <&cmu_g3d CLK_ACLK_G3D>;
1085
+			clock-names = "core";
1086
+			power-domains = <&pd_g3d>;
1087
+			operating-points-v2 = <&gpu_opp_table>;
1088
+			status = "disabled";
1089
+
1090
+			gpu_opp_table: opp-table {
1091
+				compatible = "operating-points-v2";
1092
+
1093
+				opp-160000000 {
1094
+					opp-hz = /bits/ 64 <160000000>;
1095
+					opp-microvolt = <1000000>;
1096
+				};
1097
+				opp-267000000 {
1098
+					opp-hz = /bits/ 64 <267000000>;
1099
+					opp-microvolt = <1000000>;
1100
+				};
1101
+				opp-350000000 {
1102
+					opp-hz = /bits/ 64 <350000000>;
1103
+					opp-microvolt = <1025000>;
1104
+				};
1105
+				opp-420000000 {
1106
+					opp-hz = /bits/ 64 <420000000>;
1107
+					opp-microvolt = <1025000>;
1108
+				};
1109
+				opp-500000000 {
1110
+					opp-hz = /bits/ 64 <500000000>;
1111
+					opp-microvolt = <1075000>;
1112
+				};
1113
+				opp-550000000 {
1114
+					opp-hz = /bits/ 64 <550000000>;
1115
+					opp-microvolt = <1125000>;
1116
+				};
1117
+				opp-600000000 {
1118
+					opp-hz = /bits/ 64 <600000000>;
1119
+					opp-microvolt = <1150000>;
1120
+				};
1121
+				opp-700000000 {
1122
+					opp-hz = /bits/ 64 <700000000>;
1123
+					opp-microvolt = <1150000>;
1124
+				};
1125
+			};
10451126 		};
10461127 
10471128 		scaler_0: scaler@15000000 {
....@@ -1098,9 +1179,9 @@
10981179 			compatible = "samsung,exynos-sysmmu";
10991180 			reg = <0x13a00000 0x1000>;
11001181 			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1101
-			clock-names = "pclk", "aclk";
1102
-			clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
1103
-				<&cmu_disp CLK_ACLK_SMMU_DECON0X>;
1182
+			clock-names = "aclk", "pclk";
1183
+			clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
1184
+				<&cmu_disp CLK_PCLK_SMMU_DECON0X>;
11041185 			power-domains = <&pd_disp>;
11051186 			#iommu-cells = <0>;
11061187 		};
....@@ -1109,9 +1190,9 @@
11091190 			compatible = "samsung,exynos-sysmmu";
11101191 			reg = <0x13a10000 0x1000>;
11111192 			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1112
-			clock-names = "pclk", "aclk";
1113
-			clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
1114
-				<&cmu_disp CLK_ACLK_SMMU_DECON1X>;
1193
+			clock-names = "aclk", "pclk";
1194
+			clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
1195
+				<&cmu_disp CLK_PCLK_SMMU_DECON1X>;
11151196 			#iommu-cells = <0>;
11161197 			power-domains = <&pd_disp>;
11171198 		};
....@@ -1120,9 +1201,9 @@
11201201 			compatible = "samsung,exynos-sysmmu";
11211202 			reg = <0x13a20000 0x1000>;
11221203 			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1123
-			clock-names = "pclk", "aclk";
1124
-			clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1125
-				<&cmu_disp CLK_ACLK_SMMU_TV0X>;
1204
+			clock-names = "aclk", "pclk";
1205
+			clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>,
1206
+				<&cmu_disp CLK_PCLK_SMMU_TV0X>;
11261207 			#iommu-cells = <0>;
11271208 			power-domains = <&pd_disp>;
11281209 		};
....@@ -1131,9 +1212,9 @@
11311212 			compatible = "samsung,exynos-sysmmu";
11321213 			reg = <0x13a30000 0x1000>;
11331214 			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1134
-			clock-names = "pclk", "aclk";
1135
-			clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1136
-				<&cmu_disp CLK_ACLK_SMMU_TV1X>;
1215
+			clock-names = "aclk", "pclk";
1216
+			clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>,
1217
+				<&cmu_disp CLK_PCLK_SMMU_TV1X>;
11371218 			#iommu-cells = <0>;
11381219 			power-domains = <&pd_disp>;
11391220 		};
....@@ -1175,9 +1256,9 @@
11751256 			compatible = "samsung,exynos-sysmmu";
11761257 			reg = <0x15040000 0x1000>;
11771258 			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1178
-			clock-names = "pclk", "aclk";
1179
-			clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>,
1180
-				 <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>;
1259
+			clock-names = "aclk", "pclk";
1260
+			clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>,
1261
+				<&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>;
11811262 			#iommu-cells = <0>;
11821263 			power-domains = <&pd_mscl>;
11831264 		};
....@@ -1186,9 +1267,9 @@
11861267 			compatible = "samsung,exynos-sysmmu";
11871268 			reg = <0x15050000 0x1000>;
11881269 			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
1189
-			clock-names = "pclk", "aclk";
1190
-			clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>,
1191
-				 <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>;
1270
+			clock-names = "aclk", "pclk";
1271
+			clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>,
1272
+				<&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>;
11921273 			#iommu-cells = <0>;
11931274 			power-domains = <&pd_mscl>;
11941275 		};
....@@ -1197,9 +1278,9 @@
11971278 			compatible = "samsung,exynos-sysmmu";
11981279 			reg = <0x15060000 0x1000>;
11991280 			interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1200
-			clock-names = "pclk", "aclk";
1201
-			clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
1202
-				 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
1281
+			clock-names = "aclk", "pclk";
1282
+			clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>,
1283
+				<&cmu_mscl CLK_PCLK_SMMU_JPEG>;
12031284 			#iommu-cells = <0>;
12041285 			power-domains = <&pd_mscl>;
12051286 		};
....@@ -1208,9 +1289,9 @@
12081289 			compatible = "samsung,exynos-sysmmu";
12091290 			reg = <0x15200000 0x1000>;
12101291 			interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1211
-			clock-names = "pclk", "aclk";
1212
-			clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
1213
-				 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
1292
+			clock-names = "aclk", "pclk";
1293
+			clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>,
1294
+				<&cmu_mfc CLK_PCLK_SMMU_MFC_0>;
12141295 			#iommu-cells = <0>;
12151296 			power-domains = <&pd_mfc>;
12161297 		};
....@@ -1219,9 +1300,9 @@
12191300 			compatible = "samsung,exynos-sysmmu";
12201301 			reg = <0x15210000 0x1000>;
12211302 			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1222
-			clock-names = "pclk", "aclk";
1223
-			clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
1224
-				 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
1303
+			clock-names = "aclk", "pclk";
1304
+			clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>,
1305
+				<&cmu_mfc CLK_PCLK_SMMU_MFC_1>;
12251306 			#iommu-cells = <0>;
12261307 			power-domains = <&pd_mfc>;
12271308 		};
....@@ -1371,7 +1452,7 @@
13711452 		i2s1: i2s@14d60000 {
13721453 			compatible = "samsung,exynos7-i2s";
13731454 			reg = <0x14d60000 0x100>;
1374
-			dmas = <&pdma0 31 &pdma0 30>;
1455
+			dmas = <&pdma0 31>, <&pdma0 30>;
13751456 			dma-names = "tx", "rx";
13761457 			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
13771458 			clocks = <&cmu_peric CLK_PCLK_I2S1>,
....@@ -1379,10 +1460,6 @@
13791460 				 <&cmu_peric CLK_SCLK_I2S1>;
13801461 			clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
13811462 			#clock-cells = <1>;
1382
-			samsung,supports-6ch;
1383
-			samsung,supports-rstclr;
1384
-			samsung,supports-tdm;
1385
-			samsung,supports-low-rfs;
13861463 			#sound-dai-cells = <1>;
13871464 			status = "disabled";
13881465 		};
....@@ -1559,10 +1636,12 @@
15591636 		};
15601637 
15611638 		usbdrd30: usbdrd {
1562
-			compatible = "samsung,exynos5250-dwusb3";
1639
+			compatible = "samsung,exynos5433-dwusb3";
15631640 			clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1564
-				<&cmu_fsys CLK_SCLK_USBDRD30>;
1565
-			clock-names = "usbdrd30", "usbdrd30_susp_clk";
1641
+				<&cmu_fsys CLK_SCLK_USBDRD30>,
1642
+				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1643
+				<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1644
+			clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
15661645 			#address-cells = <1>;
15671646 			#size-cells = <1>;
15681647 			ranges;
....@@ -1570,6 +1649,10 @@
15701649 
15711650 			usbdrd_dwc3: dwc3@15400000 {
15721651 				compatible = "snps,dwc3";
1652
+				clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1653
+					<&cmu_fsys CLK_ACLK_USBDRD30>,
1654
+					<&cmu_fsys CLK_SCLK_USBDRD30>;
1655
+				clock-names = "ref", "bus_early", "suspend";
15731656 				reg = <0x15400000 0x10000>;
15741657 				interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
15751658 				phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
....@@ -1606,10 +1689,12 @@
16061689 		};
16071690 
16081691 		usbhost30: usbhost {
1609
-			compatible = "samsung,exynos5250-dwusb3";
1692
+			compatible = "samsung,exynos5433-dwusb3";
16101693 			clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1611
-				<&cmu_fsys CLK_SCLK_USBHOST30>;
1612
-			clock-names = "usbdrd30", "usbdrd30_susp_clk";
1694
+				<&cmu_fsys CLK_SCLK_USBHOST30>,
1695
+				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1696
+				<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1697
+			clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
16131698 			#address-cells = <1>;
16141699 			#size-cells = <1>;
16151700 			ranges;
....@@ -1617,6 +1702,10 @@
16171702 
16181703 			usbhost_dwc3: dwc3@15a00000 {
16191704 				compatible = "snps,dwc3";
1705
+				clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1706
+					<&cmu_fsys CLK_ACLK_USBHOST30>,
1707
+					<&cmu_fsys CLK_SCLK_USBHOST30>;
1708
+				clock-names = "ref", "bus_early", "suspend";
16201709 				reg = <0x15a00000 0x10000>;
16211710 				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
16221711 				phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
....@@ -1663,33 +1752,26 @@
16631752 			status = "disabled";
16641753 		};
16651754 
1666
-		amba {
1667
-			compatible = "simple-bus";
1668
-			#address-cells = <1>;
1669
-			#size-cells = <1>;
1670
-			ranges;
1755
+		pdma0: pdma@15610000 {
1756
+			compatible = "arm,pl330", "arm,primecell";
1757
+			reg = <0x15610000 0x1000>;
1758
+			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1759
+			clocks = <&cmu_fsys CLK_PDMA0>;
1760
+			clock-names = "apb_pclk";
1761
+			#dma-cells = <1>;
1762
+			#dma-channels = <8>;
1763
+			#dma-requests = <32>;
1764
+		};
16711765 
1672
-			pdma0: pdma@15610000 {
1673
-				compatible = "arm,pl330", "arm,primecell";
1674
-				reg = <0x15610000 0x1000>;
1675
-				interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1676
-				clocks = <&cmu_fsys CLK_PDMA0>;
1677
-				clock-names = "apb_pclk";
1678
-				#dma-cells = <1>;
1679
-				#dma-channels = <8>;
1680
-				#dma-requests = <32>;
1681
-			};
1682
-
1683
-			pdma1: pdma@15600000 {
1684
-				compatible = "arm,pl330", "arm,primecell";
1685
-				reg = <0x15600000 0x1000>;
1686
-				interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1687
-				clocks = <&cmu_fsys CLK_PDMA1>;
1688
-				clock-names = "apb_pclk";
1689
-				#dma-cells = <1>;
1690
-				#dma-channels = <8>;
1691
-				#dma-requests = <32>;
1692
-			};
1766
+		pdma1: pdma@15600000 {
1767
+			compatible = "arm,pl330", "arm,primecell";
1768
+			reg = <0x15600000 0x1000>;
1769
+			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1770
+			clocks = <&cmu_fsys CLK_PDMA1>;
1771
+			clock-names = "apb_pclk";
1772
+			#dma-cells = <1>;
1773
+			#dma-channels = <8>;
1774
+			#dma-requests = <32>;
16931775 		};
16941776 
16951777 		audio-subsystem@11400000 {
....@@ -1718,7 +1800,7 @@
17181800 			i2s0: i2s@11440000 {
17191801 				compatible = "samsung,exynos7-i2s";
17201802 				reg = <0x11440000 0x100>;
1721
-				dmas = <&adma 0 &adma 2>;
1803
+				dmas = <&adma 0>, <&adma 2>;
17221804 				dma-names = "tx", "rx";
17231805 				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
17241806 				#address-cells = <1>;