forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb 
 kernel/arch/arm/boot/dts/tegra20-colibri.dtsi
....@@ -1,15 +1,13 @@
11 // SPDX-License-Identifier: GPL-2.0
22 #include "tegra20.dtsi"
33 
4
+/*
5
+ * Toradex Colibri T20 Module Device Tree
6
+ * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
7
+ * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
8
+ * Colibri T20 512MB IT V1.2A
9
+ */
410 / {
5
-	model = "Toradex Colibri T20 256/512 MB";
6
-	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
7
-
8
-	aliases {
9
-		rtc0 = "/i2c@7000d000/tps6586x@34";
10
-		rtc1 = "/rtc@7000e000";
11
-	};
12
-
1311 	memory@0 {
1412 		/*
1513 		 * Set memory to 256 MB to be safe as this could be used on
....@@ -21,12 +19,11 @@
2119 
2220 	host1x@50000000 {
2321 		hdmi@54280000 {
24
-			vdd-supply = <&hdmi_vdd_reg>;
25
-			pll-supply = <&hdmi_pll_reg>;
26
-
27
-			nvidia,ddc-i2c-bus = <&i2c_ddc>;
28
-			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
29
-				GPIO_ACTIVE_HIGH>;
22
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23
+			nvidia,hpd-gpio =
24
+				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
25
+			pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26
+			vdd-supply = <&reg_3v3_avdd_hdmi>;
3027 		};
3128 	};
3229 
....@@ -35,17 +32,12 @@
3532 		pinctrl-0 = <&state_default>;
3633 
3734 		state_default: pinmux {
38
-			audio_refclk {
35
+			/* Analogue Audio AC97 to WM9712 (On-module) */
36
+			audio-refclk {
3937 				nvidia,pins = "cdev1";
4038 				nvidia,function = "plla_out";
4139 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
4240 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
43
-			};
44
-			crt {
45
-				nvidia,pins = "crtp";
46
-				nvidia,function = "crt";
47
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
48
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
4941 			};
5042 			dap3 {
5143 				nvidia,pins = "dap3";
....@@ -53,169 +45,393 @@
5345 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
5446 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
5547 			};
56
-			displaya {
57
-				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
58
-					"ld4", "ld5", "ld6", "ld7", "ld8",
59
-					"ld9", "ld10", "ld11", "ld12", "ld13",
60
-					"ld14", "ld15", "ld16", "ld17",
61
-					"lhs", "lpw0", "lpw2", "lsc0",
62
-					"lsc1", "lsck", "lsda", "lspi", "lvs";
63
-				nvidia,function = "displaya";
64
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
65
-			};
66
-			gpio_dte {
67
-				nvidia,pins = "dte";
68
-				nvidia,function = "rsvd1";
69
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
70
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
71
-			};
72
-			gpio_gmi {
73
-				nvidia,pins = "ata", "atc", "atd", "ate",
74
-					"dap1", "dap2", "dap4", "gpu", "irrx",
75
-					"irtx", "spia", "spib", "spic";
76
-				nvidia,function = "gmi";
77
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
79
-			};
80
-			gpio_pta {
81
-				nvidia,pins = "pta";
82
-				nvidia,function = "rsvd4";
83
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
85
-			};
86
-			gpio_uac {
48
+
49
+			/*
50
+			 * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
51
+			 * (All on-module), SODIMM Pin 45 Wakeup
52
+			 */
53
+			gpio-uac {
8754 				nvidia,pins = "uac";
8855 				nvidia,function = "rsvd2";
8956 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
9057 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
9158 			};
92
-			hdint {
93
-				nvidia,pins = "hdint";
94
-				nvidia,function = "hdmi";
95
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
96
-			};
97
-			i2c1 {
98
-				nvidia,pins = "rm";
99
-				nvidia,function = "i2c1";
100
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
102
-			};
103
-			i2c3 {
104
-				nvidia,pins = "dtf";
105
-				nvidia,function = "i2c3";
106
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
107
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
108
-			};
109
-			i2cddc {
110
-				nvidia,pins = "ddc";
111
-				nvidia,function = "i2c2";
112
-				nvidia,pull = <TEGRA_PIN_PULL_UP>;
113
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
114
-			};
115
-			i2cp {
116
-				nvidia,pins = "i2cp";
117
-				nvidia,function = "i2cp";
59
+
60
+			/*
61
+			 * Buffer Enables for nPWE and RDnWR (On-module,
62
+			 * see GPIO hogging further down below)
63
+			 */
64
+			gpio-pta {
65
+				nvidia,pins = "pta";
66
+				nvidia,function = "rsvd4";
11867 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
11968 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
12069 			};
121
-			irda {
122
-				nvidia,pins = "uad";
123
-				nvidia,function = "irda";
124
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
125
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
126
-			};
127
-			nand {
128
-				nvidia,pins = "kbca", "kbcc", "kbcd",
129
-					"kbce", "kbcf";
130
-				nvidia,function = "nand";
131
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
133
-			};
134
-			owc {
135
-				nvidia,pins = "owc";
136
-				nvidia,function = "owr";
137
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
138
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
139
-			};
70
+
71
+			/*
72
+			 * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
73
+			 * SYS_CLK_REQ (All on-module)
74
+			 */
14075 			pmc {
14176 				nvidia,pins = "pmc";
14277 				nvidia,function = "pwr_on";
14378 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
14479 			};
145
-			pwm {
146
-				nvidia,pins = "sdb", "sdc", "sdd";
80
+
81
+			/*
82
+			 * Colibri Address/Data Bus (GMI)
83
+			 * Note: spid and spie optionally used for SPI1
84
+			 */
85
+			gmi {
86
+				nvidia,pins = "atc", "atd", "ate", "dap1",
87
+					      "dap2", "dap4", "gmd", "gpu",
88
+					      "irrx", "irtx", "spia", "spib",
89
+					      "spic", "spid", "spie", "uca",
90
+					      "ucb";
91
+				nvidia,function = "gmi";
92
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
94
+			};
95
+			/* Further pins may be used as GPIOs */
96
+			gmi-gpio1 {
97
+				nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
98
+				nvidia,function = "hdmi";
99
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
100
+			};
101
+			gmi-gpio2 {
102
+				nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
103
+				nvidia,function = "rsvd4";
104
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
105
+			};
106
+
107
+			/* Colibri BL_ON */
108
+			bl-on {
109
+				nvidia,pins = "dta";
110
+				nvidia,function = "rsvd1";
111
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
112
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
113
+			};
114
+
115
+			/* Colibri Backlight PWM<A>, PWM<B> */
116
+			pwm-a-b {
117
+				nvidia,pins = "sdc";
147118 				nvidia,function = "pwm";
148119 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
149120 			};
150
-			sdio4 {
151
-				nvidia,pins = "atb", "gma", "gme";
152
-				nvidia,function = "sdio4";
121
+
122
+			/* Colibri DDC */
123
+			ddc {
124
+				nvidia,pins = "ddc";
125
+				nvidia,function = "i2c2";
126
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
127
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
128
+			};
129
+
130
+			/*
131
+			 * Colibri EXT_IO*
132
+			 * Note: dtf optionally used for I2C3
133
+			 */
134
+			ext-io {
135
+				nvidia,pins = "dtf", "spdi";
136
+				nvidia,function = "rsvd2";
153137 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154138 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
155139 			};
156
-			spi1 {
157
-				nvidia,pins = "spid", "spie", "spif";
158
-				nvidia,function = "spi1";
159
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
161
-			};
162
-			spi4 {
163
-				nvidia,pins = "slxa", "slxc", "slxd", "slxk";
164
-				nvidia,function = "spi4";
165
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
167
-			};
168
-			uarta {
169
-				nvidia,pins = "sdio1";
170
-				nvidia,function = "uarta";
171
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
172
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
173
-			};
174
-			uartd {
175
-				nvidia,pins = "gmc";
176
-				nvidia,function = "uartd";
177
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178
-				nvidia,tristate = <TEGRA_PIN_ENABLE>;
179
-			};
140
+
141
+			/*
142
+			 * Colibri Ethernet (On-module)
143
+			 * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
144
+			 */
180145 			ulpi {
181146 				nvidia,pins = "uaa", "uab", "uda";
182147 				nvidia,function = "ulpi";
183148 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
184149 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
185150 			};
186
-			ulpi_refclk {
151
+			ulpi-refclk {
187152 				nvidia,pins = "cdev2";
188153 				nvidia,function = "pllp_out4";
189154 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190155 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
191156 			};
192
-			usb_gpio {
193
-				nvidia,pins = "spig", "spih";
194
-				nvidia,function = "spi2_alt";
195
-				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196
-				nvidia,tristate = <TEGRA_PIN_DISABLE>;
157
+
158
+			/* Colibri HOTPLUG_DETECT (HDMI) */
159
+			hotplug-detect {
160
+				nvidia,pins = "hdint";
161
+				nvidia,function = "hdmi";
162
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
197163 			};
198
-			vi {
199
-				nvidia,pins = "dta", "dtb", "dtc", "dtd";
200
-				nvidia,function = "vi";
164
+
165
+			/* Colibri I2C */
166
+			i2c {
167
+				nvidia,pins = "rm";
168
+				nvidia,function = "i2c1";
201169 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202170 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
203171 			};
204
-			vi_sc {
172
+
173
+			/*
174
+			 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
175
+			 * today's display need DE, disable LCD_M1
176
+			 */
177
+			lm1 {
178
+				nvidia,pins = "lm1";
179
+				nvidia,function = "rsvd3";
180
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
181
+			};
182
+
183
+			/* Colibri LCD (L_* resp. LDD<*>) */
184
+			lcd {
185
+				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
186
+					      "ld4", "ld5", "ld6", "ld7",
187
+					      "ld8", "ld9", "ld10", "ld11",
188
+					      "ld12", "ld13", "ld14", "ld15",
189
+					      "ld16", "ld17", "lhs", "lsc0",
190
+					      "lspi", "lvs";
191
+				nvidia,function = "displaya";
192
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
193
+			};
194
+			/* Colibri LCD (Optional 24 BPP Support) */
195
+			lcd-24 {
196
+				nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
197
+					      "lpp", "lvp1";
198
+				nvidia,function = "displaya";
199
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
200
+			};
201
+
202
+			/* Colibri MMC */
203
+			mmc {
204
+				nvidia,pins = "atb", "gma";
205
+				nvidia,function = "sdio4";
206
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
208
+			};
209
+
210
+			/* Colibri MMCCD */
211
+			mmccd {
212
+				nvidia,pins = "gmb";
213
+				nvidia,function = "gmi_int";
214
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
216
+			};
217
+
218
+			/* Colibri MMC (Optional 8-bit) */
219
+			mmc-8bit {
220
+				nvidia,pins = "gme";
221
+				nvidia,function = "sdio4";
222
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
224
+			};
225
+
226
+			/*
227
+			 * Colibri Parallel Camera (Optional)
228
+			 * pins multiplexed with others and therefore disabled
229
+			 * Note: dta used for BL_ON by default
230
+			 */
231
+			cif-mclk {
205232 				nvidia,pins = "csus";
206233 				nvidia,function = "vi_sensor_clk";
207234 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208235 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
209236 			};
237
+			cif {
238
+				nvidia,pins = "dtb", "dtc", "dtd";
239
+				nvidia,function = "vi";
240
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
242
+			};
243
+
244
+			/* Colibri PWM<C>, PWM<D> */
245
+			pwm-c-d {
246
+				nvidia,pins = "sdb", "sdd";
247
+				nvidia,function = "pwm";
248
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
249
+			};
250
+
251
+			/* Colibri SSP */
252
+			ssp {
253
+				nvidia,pins = "slxa", "slxc", "slxd", "slxk";
254
+				nvidia,function = "spi4";
255
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
257
+			};
258
+
259
+			/* Colibri UART-A */
260
+			uart-a {
261
+				nvidia,pins = "sdio1";
262
+				nvidia,function = "uarta";
263
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
265
+			};
266
+			uart-a-dsr {
267
+				nvidia,pins = "lpw1";
268
+				nvidia,function = "rsvd3";
269
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
270
+			};
271
+			uart-a-dcd {
272
+				nvidia,pins = "lpw2";
273
+				nvidia,function = "hdmi";
274
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
275
+			};
276
+
277
+			/* Colibri UART-B */
278
+			uart-b {
279
+				nvidia,pins = "gmc";
280
+				nvidia,function = "uartd";
281
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
283
+			};
284
+
285
+			/* Colibri UART-C */
286
+			uart-c {
287
+				nvidia,pins = "uad";
288
+				nvidia,function = "irda";
289
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
290
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
291
+			};
292
+
293
+			/* Colibri USB_CDET */
294
+			usb-cdet {
295
+				nvidia,pins = "spdo";
296
+				nvidia,function = "rsvd2";
297
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
299
+			};
300
+
301
+			/* Colibri USBH_OC */
302
+			usbh-oc {
303
+				nvidia,pins = "spih";
304
+				nvidia,function = "spi2_alt";
305
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
307
+			};
308
+
309
+			/* Colibri USBH_PEN */
310
+			usbh-pen {
311
+				nvidia,pins = "spig";
312
+				nvidia,function = "spi2_alt";
313
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
314
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
315
+			};
316
+
317
+			/* Colibri VGA not supported */
318
+			vga {
319
+				nvidia,pins = "crtp";
320
+				nvidia,function = "crt";
321
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
322
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
323
+			};
324
+
325
+			/* I2C3 (Optional) */
326
+			i2c3 {
327
+				nvidia,pins = "dtf";
328
+				nvidia,function = "i2c3";
329
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
331
+			};
332
+
333
+			/* JTAG_RTCK */
334
+			jtag-rtck {
335
+				nvidia,pins = "gpu7";
336
+				nvidia,function = "rtck";
337
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
339
+			};
340
+
341
+			/*
342
+			 * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
343
+			 * (All On-module)
344
+			 */
345
+			gpio-gpv {
346
+				nvidia,pins = "gpv";
347
+				nvidia,function = "rsvd2";
348
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
349
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
350
+			};
351
+
352
+			/*
353
+			 * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
354
+			 * (All On-module); Colibri CAN_INT
355
+			 */
356
+			gpio-dte {
357
+				nvidia,pins = "dte";
358
+				nvidia,function = "rsvd1";
359
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
360
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
361
+			};
362
+
363
+			/* NAND (On-module) */
364
+			nand {
365
+				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
366
+					      "kbce", "kbcf";
367
+				nvidia,function = "nand";
368
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
369
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
370
+			};
371
+
372
+			/* Onewire (Optional) */
373
+			owr {
374
+				nvidia,pins = "owc";
375
+				nvidia,function = "owr";
376
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
378
+			};
379
+
380
+			/* Power I2C (On-module) */
381
+			i2cp {
382
+				nvidia,pins = "i2cp";
383
+				nvidia,function = "i2cp";
384
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
386
+			};
387
+
388
+			/* RESET_OUT */
389
+			reset-out {
390
+				nvidia,pins = "ata";
391
+				nvidia,function = "gmi";
392
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
394
+			};
395
+
396
+			/*
397
+			 * SPI1 (Optional)
398
+			 * Note: spid and spie used for Colibri Address/Data
399
+			 *       Bus (GMI)
400
+			 */
401
+			spi1 {
402
+				nvidia,pins = "spid", "spie", "spif";
403
+				nvidia,function = "spi1";
404
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
405
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
406
+			};
407
+
408
+			/*
409
+			 * THERMD_ALERT# (On-module), unlatched I2C address pin
410
+			 * of LM95245 temperature sensor therefore requires
411
+			 * disabling for now
412
+			 */
413
+			lvp0 {
414
+				nvidia,pins = "lvp0";
415
+				nvidia,function = "rsvd3";
416
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
417
+			};
210418 		};
211419 	};
212420 
213
-	ac97: ac97@70002000 {
421
+	tegra_ac97: ac97@70002000 {
214422 		status = "okay";
215
-		nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
216
-			GPIO_ACTIVE_HIGH>;
217
-		nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
218
-			GPIO_ACTIVE_HIGH>;
423
+		nvidia,codec-reset-gpio =
424
+			<&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
425
+		nvidia,codec-sync-gpio =
426
+			<&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
427
+	};
428
+
429
+	serial@70006040 {
430
+		compatible = "nvidia,tegra20-hsuart";
431
+	};
432
+
433
+	serial@70006300 {
434
+		compatible = "nvidia,tegra20-hsuart";
219435 	};
220436 
221437 	nand-controller@70008000 {
....@@ -243,7 +459,7 @@
243459 	};
244460 
245461 	/* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
246
-	i2c_ddc: i2c@7000c400 {
462
+	hdmi_ddc: i2c@7000c400 {
247463 		clock-frequency = <10000>;
248464 	};
249465 
....@@ -256,59 +472,45 @@
256472 		status = "okay";
257473 		clock-frequency = <100000>;
258474 
259
-		pmic: tps6586x@34 {
475
+		pmic@34 {
260476 			compatible = "ti,tps6586x";
261477 			reg = <0x34>;
262478 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
263
-
264479 			ti,system-power-controller;
265
-
266480 			#gpio-cells = <2>;
267481 			gpio-controller;
268
-
269
-			sys-supply = <&vdd_3v3_reg>;
270
-			vin-sm0-supply = <&sys_reg>;
271
-			vin-sm1-supply = <&sys_reg>;
272
-			vin-sm2-supply = <&sys_reg>;
273
-			vinldo01-supply = <&sm2_reg>;
274
-			vinldo23-supply = <&vdd_3v3_reg>;
275
-			vinldo4-supply = <&vdd_3v3_reg>;
276
-			vinldo678-supply = <&vdd_3v3_reg>;
277
-			vinldo9-supply = <&vdd_3v3_reg>;
482
+			sys-supply = <&reg_module_3v3>;
483
+			vin-sm0-supply = <&reg_3v3_vsys>;
484
+			vin-sm1-supply = <&reg_3v3_vsys>;
485
+			vin-sm2-supply = <&reg_3v3_vsys>;
486
+			vinldo01-supply = <&reg_1v8_vdd_ddr2>;
487
+			vinldo23-supply = <&reg_module_3v3>;
488
+			vinldo4-supply = <&reg_module_3v3>;
489
+			vinldo678-supply = <&reg_module_3v3>;
490
+			vinldo9-supply = <&reg_module_3v3>;
278491 
279492 			regulators {
280
-				#address-cells = <1>;
281
-				#size-cells = <0>;
282
-
283
-				sys_reg: regulator@0 {
284
-					reg = <0>;
285
-					regulator-compatible = "sys";
286
-					regulator-name = "vdd_sys";
493
+				reg_3v3_vsys: sys {
494
+					regulator-name = "VSYS_3.3V";
287495 					regulator-always-on;
288496 				};
289497 
290
-				regulator@1 {
291
-					reg = <1>;
292
-					regulator-compatible = "sm0";
293
-					regulator-name = "vdd_sm0,vdd_core";
498
+				sm0 {
499
+					regulator-name = "VDD_CORE_1.2V";
294500 					regulator-min-microvolt = <1200000>;
295501 					regulator-max-microvolt = <1200000>;
296502 					regulator-always-on;
297503 				};
298504 
299
-				regulator@2 {
300
-					reg = <2>;
301
-					regulator-compatible = "sm1";
302
-					regulator-name = "vdd_sm1,vdd_cpu";
505
+				sm1 {
506
+					regulator-name = "VDD_CPU_1.0V";
303507 					regulator-min-microvolt = <1000000>;
304508 					regulator-max-microvolt = <1000000>;
305509 					regulator-always-on;
306510 				};
307511 
308
-				sm2_reg: regulator@3 {
309
-					reg = <3>;
310
-					regulator-compatible = "sm2";
311
-					regulator-name = "vdd_sm2,vin_ldo*";
512
+				reg_1v8_vdd_ddr2: sm2 {
513
+					regulator-name = "VDD_DDR2_1.8V";
312514 					regulator-min-microvolt = <1800000>;
313515 					regulator-max-microvolt = <1800000>;
314516 					regulator-always-on;
....@@ -316,80 +518,68 @@
316518 
317519 				/* LDO0 is not connected to anything */
318520 
319
-				regulator@5 {
320
-					reg = <5>;
321
-					regulator-compatible = "ldo1";
322
-					regulator-name = "vdd_ldo1,avdd_pll*";
521
+				/*
522
+				 * +3.3V_ENABLE_N switching via FET:
523
+				 * AVDD_AUDIO_S and +3.3V
524
+				 * see also +3.3V fixed supply
525
+				 */
526
+				ldo1 {
527
+					regulator-name = "AVDD_PLL_1.1V";
323528 					regulator-min-microvolt = <1100000>;
324529 					regulator-max-microvolt = <1100000>;
325530 					regulator-always-on;
326531 				};
327532 
328
-				regulator@6 {
329
-					reg = <6>;
330
-					regulator-compatible = "ldo2";
331
-					regulator-name = "vdd_ldo2,vdd_rtc";
533
+				ldo2 {
534
+					regulator-name = "VDD_RTC_1.2V";
332535 					regulator-min-microvolt = <1200000>;
333536 					regulator-max-microvolt = <1200000>;
334537 				};
335538 
336539 				/* LDO3 is not connected to anything */
337540 
338
-				regulator@8 {
339
-					reg = <8>;
340
-					regulator-compatible = "ldo4";
341
-					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
541
+				ldo4 {
542
+					regulator-name = "VDDIO_SYS_1.8V";
342543 					regulator-min-microvolt = <1800000>;
343544 					regulator-max-microvolt = <1800000>;
344545 					regulator-always-on;
345546 				};
346547 
347
-				ldo5_reg: regulator@9 {
348
-					reg = <9>;
349
-					regulator-compatible = "ldo5";
350
-					regulator-name = "vdd_ldo5,vdd_fuse";
548
+				/* Switched via FET from regular +3.3V */
549
+				ldo5 {
550
+					regulator-name = "+3.3V_USB";
351551 					regulator-min-microvolt = <3300000>;
352552 					regulator-max-microvolt = <3300000>;
353553 					regulator-always-on;
354554 				};
355555 
356
-				regulator@10 {
357
-					reg = <10>;
358
-					regulator-compatible = "ldo6";
359
-					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
556
+				ldo6 {
557
+					regulator-name = "AVDD_VDAC_2.85V";
360558 					regulator-min-microvolt = <2850000>;
361559 					regulator-max-microvolt = <2850000>;
362560 				};
363561 
364
-				hdmi_vdd_reg: regulator@11 {
365
-					reg = <11>;
366
-					regulator-compatible = "ldo7";
367
-					regulator-name = "vdd_ldo7,avdd_hdmi";
562
+				reg_3v3_avdd_hdmi: ldo7 {
563
+					regulator-name = "AVDD_HDMI_3.3V";
368564 					regulator-min-microvolt = <3300000>;
369565 					regulator-max-microvolt = <3300000>;
370566 				};
371567 
372
-				hdmi_pll_reg: regulator@12 {
373
-					reg = <12>;
374
-					regulator-compatible = "ldo8";
375
-					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
568
+				reg_1v8_avdd_hdmi_pll: ldo8 {
569
+					regulator-name = "AVDD_HDMI_PLL_1.8V";
376570 					regulator-min-microvolt = <1800000>;
377571 					regulator-max-microvolt = <1800000>;
378572 				};
379573 
380
-				regulator@13 {
381
-					reg = <13>;
382
-					regulator-compatible = "ldo9";
383
-					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
574
+				ldo9 {
575
+					regulator-name = "VDDIO_RX_DDR_2.85V";
384576 					regulator-min-microvolt = <2850000>;
385577 					regulator-max-microvolt = <2850000>;
386578 					regulator-always-on;
387579 				};
388580 
389
-				regulator@14 {
390
-					reg = <14>;
391
-					regulator-compatible = "ldo_rtc";
392
-					regulator-name = "vdd_rtc_out,vdd_cell";
581
+				ldo_rtc {
582
+					regulator-name = "VCC_BATT";
393583 					regulator-min-microvolt = <3300000>;
394584 					regulator-max-microvolt = <3300000>;
395585 					regulator-always-on;
....@@ -397,7 +587,8 @@
397587 			};
398588 		};
399589 
400
-		temperature-sensor@4c {
590
+		/* LM95245 temperature sensor */
591
+		temp-sensor@4c {
401592 			compatible = "national,lm95245";
402593 			reg = <0x4c>;
403594 		};
....@@ -410,6 +601,14 @@
410601 		nvidia,core-pwr-good-time = <3845 3845>;
411602 		nvidia,core-pwr-off-time = <3875>;
412603 		nvidia,sys-clock-req-active-high;
604
+
605
+		/* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
606
+		i2c-thermtrip {
607
+			nvidia,i2c-controller-id = <3>;
608
+			nvidia,bus-addr = <0x34>;
609
+			nvidia,reg-addr = <0x14>;
610
+			nvidia,reg-data = <0x8>;
611
+		};
413612 	};
414613 
415614 	memory-controller@7000f400 {
....@@ -483,79 +682,87 @@
483682 		};
484683 	};
485684 
685
+	/* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
486686 	usb@c5004000 {
487687 		status = "okay";
488
-		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
489
-			GPIO_ACTIVE_LOW>;
688
+		#address-cells = <1>;
689
+		#size-cells = <0>;
690
+
691
+		asix@1 {
692
+			reg = <1>;
693
+			local-mac-address = [00 00 00 00 00 00];
694
+		};
490695 	};
491696 
492697 	usb-phy@c5004000 {
493698 		status = "okay";
494
-		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
495
-			GPIO_ACTIVE_LOW>;
699
+		nvidia,phy-reset-gpio =
700
+			<&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
701
+		vbus-supply = <&reg_lan_v_bus>;
496702 	};
497703 
498
-	sdhci@c8000600 {
499
-		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
704
+	clk32k_in: xtal3 {
705
+		compatible = "fixed-clock";
706
+		#clock-cells = <0>;
707
+		clock-frequency = <32768>;
500708 	};
501709 
502
-	clocks {
503
-		compatible = "simple-bus";
504
-		#address-cells = <1>;
505
-		#size-cells = <0>;
506
-
507
-		clk32k_in: clock@0 {
508
-			compatible = "fixed-clock";
509
-			reg = <0>;
510
-			#clock-cells = <0>;
511
-			clock-frequency = <32768>;
512
-		};
710
+	reg_lan_v_bus: regulator-lan-v-bus {
711
+		compatible = "regulator-fixed";
712
+		regulator-name = "LAN_V_BUS";
713
+		regulator-min-microvolt = <5000000>;
714
+		regulator-max-microvolt = <5000000>;
715
+		enable-active-high;
716
+		gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
513717 	};
514718 
515
-	regulators {
516
-		compatible = "simple-bus";
517
-		#address-cells = <1>;
518
-		#size-cells = <0>;
519
-
520
-		vdd_3v3_reg: regulator@100 {
521
-			compatible = "regulator-fixed";
522
-			reg = <100>;
523
-			regulator-name = "vdd_3v3";
524
-			regulator-min-microvolt = <3300000>;
525
-			regulator-max-microvolt = <3300000>;
526
-			regulator-always-on;
527
-		};
528
-
529
-		regulator@101 {
530
-			compatible = "regulator-fixed";
531
-			reg = <101>;
532
-			regulator-name = "internal_usb";
533
-			regulator-min-microvolt = <5000000>;
534
-			regulator-max-microvolt = <5000000>;
535
-			enable-active-high;
536
-			regulator-boot-on;
537
-			regulator-always-on;
538
-			gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
539
-		};
719
+	reg_module_3v3: regulator-module-3v3 {
720
+		compatible = "regulator-fixed";
721
+		regulator-name = "+V3.3";
722
+		regulator-min-microvolt = <3300000>;
723
+		regulator-max-microvolt = <3300000>;
724
+		regulator-always-on;
540725 	};
541726 
542727 	sound {
543728 		compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
544
-			         "nvidia,tegra-audio-wm9712";
545
-		nvidia,model = "Colibri T20 AC97 Audio";
546
-
729
+			     "nvidia,tegra-audio-wm9712";
730
+		nvidia,model = "Toradex Colibri T20";
547731 		nvidia,audio-routing =
548732 			"Headphone", "HPOUTL",
549733 			"Headphone", "HPOUTR",
550734 			"LineIn", "LINEINL",
551735 			"LineIn", "LINEINR",
552736 			"Mic", "MIC1";
553
-
554
-		nvidia,ac97-controller = <&ac97>;
555
-
737
+		nvidia,ac97-controller = <&tegra_ac97>;
556738 		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
557739 			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
558740 			 <&tegra_car TEGRA20_CLK_CDEV1>;
559741 		clock-names = "pll_a", "pll_a_out0", "mclk";
560742 	};
561743 };
744
+
745
+&gpio {
746
+	lan-reset-n {
747
+		gpio-hog;
748
+		gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
749
+		output-high;
750
+		line-name = "LAN_RESET#";
751
+	};
752
+
753
+	/* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
754
+	npwe {
755
+		gpio-hog;
756
+		gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
757
+		output-high;
758
+		line-name = "Tri-state nPWE";
759
+	};
760
+
761
+	/* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
762
+	rdnwr {
763
+		gpio-hog;
764
+		gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
765
+		output-low;
766
+		line-name = "Not tri-state RDnWR";
767
+	};
768
+};