gmac get mac form eeprom

hc

2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/arm/boot/dts/r8a7778.dtsi
..
..
@@ -1,6 +1,6 @@
1
1
 // SPDX-License-Identifier: GPL-2.0
2
2
 /*
3
- * Device Tree Source for Renesas r8a7778
3
+ * Device Tree Source for the R-Car M1A (R8A77781) SoC
4
4
  *
5
5
  * Copyright (C) 2013  Renesas Solutions Corp.
6
6
  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
..
..
@@ -78,11 +78,12 @@
78
78
 			<0xfe780010 4>,
79
79
 			<0xfe780024 4>,
80
80
 			<0xfe780044 4>,
81
-			<0xfe780064 4>;
82
-		interrupts =   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
83
-				GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
84
-				GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
85
-				GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
81
+			<0xfe780064 4>,
82
+			<0xfe780000 4>;
83
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
84
+			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
85
+			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
86
+			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
86
87
 		sense-bitfield-width = <2>;
87
88
 	};
88
89
 
..
..
@@ -141,7 +142,7 @@
141
142
 		interrupt-controller;
142
143
 	};
143
144
 
144
-	pfc: pin-controller@fffc0000 {
145
+	pfc: pinctrl@fffc0000 {
145
146
 		compatible = "renesas,pfc-r8a7778";
146
147
 		reg = <0xfffc0000 0x118>;
147
148
 	};
..
..
@@ -367,6 +368,30 @@
367
368
 		status = "disabled";
368
369
 	};
369
370
 
371
+	hscif0: serial@ffe48000 {
372
+		compatible = "renesas,hscif-r8a7778",
373
+			     "renesas,rcar-gen1-hscif", "renesas,hscif";
374
+		reg = <0xffe48000 96>;
375
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
376
+		clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
377
+			 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
378
+		clock-names = "fck", "brg_int", "scif_clk";
379
+		power-domains = <&cpg_clocks>;
380
+		status = "disabled";
381
+	};
382
+
383
+	hscif1: serial@ffe49000 {
384
+		compatible = "renesas,hscif-r8a7778",
385
+			     "renesas,rcar-gen1-hscif", "renesas,hscif";
386
+		reg = <0xffe49000 96>;
387
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
388
+		clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
389
+			 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
390
+		clock-names = "fck", "brg_int", "scif_clk";
391
+		power-domains = <&cpg_clocks>;
392
+		status = "disabled";
393
+	};
394
+
370
395
 	mmcif: mmc@ffe4e000 {
371
396
 		compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
372
397
 		reg = <0xffe4e000 0x100>;
..
..
@@ -376,7 +401,7 @@
376
401
 		status = "disabled";
377
402
 	};
378
403
 
379
-	sdhi0: sd@ffe4c000 {
404
+	sdhi0: mmc@ffe4c000 {
380
405
 		compatible = "renesas,sdhi-r8a7778",
381
406
 			     "renesas,rcar-gen1-sdhi";
382
407
 		reg = <0xffe4c000 0x100>;
..
..
@@ -386,7 +411,7 @@
386
411
 		status = "disabled";
387
412
 	};
388
413
 
389
-	sdhi1: sd@ffe4d000 {
414
+	sdhi1: mmc@ffe4d000 {
390
415
 		compatible = "renesas,sdhi-r8a7778",
391
416
 			     "renesas,rcar-gen1-sdhi";
392
417
 		reg = <0xffe4d000 0x100>;
..
..
@@ -396,7 +421,7 @@
396
421
 		status = "disabled";
397
422
 	};
398
423
 
399
-	sdhi2: sd@ffe4f000 {
424
+	sdhi2: mmc@ffe4f000 {
400
425
 		compatible = "renesas,sdhi-r8a7778",
401
426
 			     "renesas,rcar-gen1-sdhi";
402
427
 		reg = <0xffe4f000 0x100>;
..
..
@@ -474,14 +499,17 @@
474
499
 		audio_clk_a: audio_clk_a {
475
500
 			compatible = "fixed-clock";
476
501
 			#clock-cells = <0>;
502
+			clock-frequency = <0>;
477
503
 		};
478
504
 		audio_clk_b: audio_clk_b {
479
505
 			compatible = "fixed-clock";
480
506
 			#clock-cells = <0>;
507
+			clock-frequency = <0>;
481
508
 		};
482
509
 		audio_clk_c: audio_clk_c {
483
510
 			compatible = "fixed-clock";
484
511
 			#clock-cells = <0>;
512
+			clock-frequency = <0>;
485
513
 		};
486
514
 
487
515
 		/* Fixed ratio clocks */
..
..
@@ -535,6 +563,8 @@
535
563
 				 <&cpg_clocks R8A7778_CLK_P>,
536
564
 				 <&cpg_clocks R8A7778_CLK_P>,
537
565
 				 <&cpg_clocks R8A7778_CLK_P>,
566
+				 <&cpg_clocks R8A7778_CLK_S>,
567
+				 <&cpg_clocks R8A7778_CLK_S>,
538
568
 				 <&cpg_clocks R8A7778_CLK_P>,
539
569
 				 <&cpg_clocks R8A7778_CLK_P>,
540
570
 				 <&cpg_clocks R8A7778_CLK_P>,
..
..
@@ -551,6 +581,7 @@
551
581
 				R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
552
582
 				R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
553
583
 				R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
584
+				R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
554
585
 				R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
555
586
 				R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
556
587
 				R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
..
..
@@ -560,6 +591,7 @@
560
591
 			clock-output-names =
561
592
 				"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
562
593
 				"scif1", "scif2", "scif3", "scif4", "scif5",
594
+				"hscif0", "hscif1",
563
595
 				"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
564
596
 				"ssi2", "ssi3", "sru", "hspi";
565
597
 		};