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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/arm/boot/dts/imx6dl.dtsi
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@@ -15,7 +15,7 @@
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 		#address-cells = <1>;
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 		#size-cells = <0>;
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-		cpu@0 {
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+		cpu0: cpu@0 {
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 			compatible = "arm,cortex-a9";
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 			device_type = "cpu";
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 			reg = <0>;
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@@ -44,6 +44,8 @@
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 			arm-supply = <&reg_arm>;
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 			pu-supply = <&reg_pu>;
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 			soc-supply = <&reg_soc>;
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+			nvmem-cells = <&cpu_speed_grade>;
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+			nvmem-cell-names = "speed_grade";
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 		};
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 		cpu@1 {
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@@ -64,6 +66,7 @@
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 				396000	1175000
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 			>;
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 			clock-latency = <61036>; /* two CLK32 periods */
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+			#cooling-cells = <2>;
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 			clocks = <&clks IMX6QDL_CLK_ARM>,
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 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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 				 <&clks IMX6QDL_CLK_STEP>,
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@@ -81,14 +84,13 @@
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 		ocram: sram@900000 {
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 			compatible = "mmio-sram";
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 			reg = <0x00900000 0x20000>;
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+			ranges = <0 0x00900000 0x20000>;
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
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 		};
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-		aips1: aips-bus@2000000 {
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-			iomuxc: iomuxc@20e0000 {
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-				compatible = "fsl,imx6dl-iomuxc";
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-			};
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-
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+		aips1: bus@2000000 {
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 			pxp: pxp@20f0000 {
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 				reg = <0x020f0000 0x4000>;
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 				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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@@ -100,7 +102,7 @@
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 			};
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 		};
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-		aips2: aips-bus@2100000 {
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+		aips2: bus@2100000 {
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 			i2c4: i2c@21f8000 {
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 				#address-cells = <1>;
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 				#size-cells = <0>;
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@@ -295,6 +297,10 @@
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 	compatible = "fsl,imx6dl-hdmi";
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 };
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+&iomuxc {
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+	compatible = "fsl,imx6dl-iomuxc";
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+};
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+
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 &ipu1_csi1 {
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 	ipu1_csi1_from_ipu1_csi1_mux: endpoint {
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 		remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;