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2024-05-10 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb

 kernel/arch/arc/boot/dts/hsdk.dts
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@@ -1,9 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 /*
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@@ -11,15 +8,15 @@
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  */
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 /dts-v1/;
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-#include <dt-bindings/net/ti-dp83867.h>
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+#include <dt-bindings/gpio/gpio.h>
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 #include <dt-bindings/reset/snps,hsdk-reset.h>
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13
 
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 / {
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 	model = "snps,hsdk";
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 	compatible = "snps,hsdk";
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-	#address-cells = <1>;
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-	#size-cells = <1>;
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+	#address-cells = <2>;
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+	#size-cells = <2>;
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 	chosen {
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 		bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
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@@ -68,6 +65,14 @@
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 		clock-frequency = <33333333>;
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 	};
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+	reg_5v0: regulator-5v0 {
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+		compatible = "regulator-fixed";
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+
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+		regulator-name = "5v0-supply";
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+		regulator-min-microvolt = <5000000>;
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+		regulator-max-microvolt = <5000000>;
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+	};
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+
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 	cpu_intc: cpu-interrupt-controller {
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 		compatible = "snps,archs-intc";
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 		interrupt-controller;
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@@ -107,17 +112,17 @@
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 		#size-cells = <1>;
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 		interrupt-parent = <&idu_intc>;
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-		ranges = <0x00000000 0xf0000000 0x10000000>;
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+		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
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 		cgu_rst: reset-controller@8a0 {
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 			compatible = "snps,hsdk-reset";
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 			#reset-cells = <1>;
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-			reg = <0x8A0 0x4>, <0xFF0 0x4>;
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+			reg = <0x8a0 0x4>, <0xff0 0x4>;
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 		};
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 		core_clk: core-clk@0 {
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 			compatible = "snps,hsdk-core-pll-clock";
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-			reg = <0x00 0x10>, <0x14B8 0x4>;
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+			reg = <0x00 0x10>, <0x14b8 0x4>;
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 			#clock-cells = <0>;
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 			clocks = <&input_clk>;
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@@ -169,6 +174,36 @@
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 			#clock-cells = <0>;
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 		};
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+		gpu_core_clk: gpu-core-clk {
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+			compatible = "fixed-clock";
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+			clock-frequency = <400000000>;
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+			#clock-cells = <0>;
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+		};
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+
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+		gpu_dma_clk: gpu-dma-clk {
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+			compatible = "fixed-clock";
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+			clock-frequency = <400000000>;
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+			#clock-cells = <0>;
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+		};
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+
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+		gpu_cfg_clk: gpu-cfg-clk {
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+			compatible = "fixed-clock";
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+			clock-frequency = <200000000>;
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+			#clock-cells = <0>;
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+		};
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+
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+		dmac_core_clk: dmac-core-clk {
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+			compatible = "fixed-clock";
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+			clock-frequency = <400000000>;
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+			#clock-cells = <0>;
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+		};
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+
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+		dmac_cfg_clk: dmac-gpu-cfg-clk {
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+			compatible = "fixed-clock";
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+			clock-frequency = <200000000>;
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+			#clock-cells = <0>;
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+		};
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+
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 		gmac: ethernet@8000 {
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 			#interrupt-cells = <1>;
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 			compatible = "snps,dwmac";
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@@ -195,9 +230,6 @@
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 				compatible = "snps,dwmac-mdio";
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 				phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
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 					reg = <0>;
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-					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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-					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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-					ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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 				};
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 			};
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 		};
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@@ -206,6 +238,7 @@
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 			compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
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 			reg = <0x60000 0x100>;
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 			interrupts = <15>;
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+			resets = <&cgu_rst HSDK_USB_RESET>;
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 			dma-coherent;
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 		};
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@@ -213,6 +246,7 @@
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 			compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
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 			reg = <0x40000 0x100>;
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 			interrupts = <15>;
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+			resets = <&cgu_rst HSDK_USB_RESET>;
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 			dma-coherent;
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 		};
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@@ -228,12 +262,90 @@
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 			bus-width = <4>;
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 			dma-coherent;
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 		};
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+
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+		spi0: spi@20000 {
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+			compatible = "snps,dw-apb-ssi";
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+			reg = <0x20000 0x100>;
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+			interrupts = <16>;
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+			num-cs = <2>;
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+			reg-io-width = <4>;
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+			clocks = <&input_clk>;
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+			cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
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+				   <&creg_gpio 1 GPIO_ACTIVE_LOW>;
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+
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+			spi-flash@0 {
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+				compatible = "sst26wf016b", "jedec,spi-nor";
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+				reg = <0>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				spi-max-frequency = <4000000>;
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+			};
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+
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+			adc@1 {
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+				compatible = "ti,adc108s102";
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+				reg = <1>;
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+				vref-supply = <&reg_5v0>;
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+				spi-max-frequency = <1000000>;
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+			};
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+		};
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+
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+		creg_gpio: gpio@14b0 {
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+			compatible = "snps,creg-gpio-hsdk";
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+			reg = <0x14b0 0x4>;
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+			gpio-controller;
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+			#gpio-cells = <2>;
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+			ngpios = <2>;
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+		};
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+
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+		gpio: gpio@3000 {
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+			compatible = "snps,dw-apb-gpio";
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+			reg = <0x3000 0x20>;
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+
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+			gpio_port_a: gpio-controller@0 {
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+				compatible = "snps,dw-apb-gpio-port";
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+				gpio-controller;
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+				#gpio-cells = <2>;
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+				snps,nr-gpios = <24>;
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+				reg = <0>;
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+			};
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+		};
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+
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+		gpu_3d: gpu@90000 {
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+			compatible = "vivante,gc";
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+			reg = <0x90000 0x4000>;
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+			clocks = <&gpu_dma_clk>,
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+				 <&gpu_cfg_clk>,
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+				 <&gpu_core_clk>,
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+				 <&gpu_core_clk>;
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+			clock-names = "bus", "reg", "core", "shader";
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+			interrupts = <28>;
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+		};
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+
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+		dmac: dmac@80000 {
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+			compatible = "snps,axi-dma-1.01a";
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+			reg = <0x80000 0x400>;
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+			interrupts = <27>;
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+			clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
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+			clock-names = "core-clk", "cfgr-clk";
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+
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+			dma-channels = <4>;
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+			snps,dma-masters = <2>;
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+			snps,data-width = <3>;
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+			snps,block-size = <4096 4096 4096 4096>;
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+			snps,priority = <0 1 2 3>;
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+			snps,axi-max-burst-len = <16>;
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+		};
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 	};
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 	memory@80000000 {
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-		#address-cells = <1>;
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-		#size-cells = <1>;
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+		#address-cells = <2>;
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+		#size-cells = <2>;
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 		device_type = "memory";
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-		reg = <0x80000000 0x40000000>;  /* 1 GiB */
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+		reg = <0x0 0x80000000 0x0 0x40000000>;  /* 1 GB lowmem */
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+		/*     0x1 0x00000000 0x0 0x40000000>;     1 GB highmem */
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 	};
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 };